Input interface protection circuit

Abstract

The utility model provides an input interface protection circuit. The input interface protection circuit comprises an external input; the electrostatic discharge protection circuit is electrically connected to the connecting end of the external input, the electrostatic discharge protection circuit is grounded, and the connecting end of the electrostatic discharge protection circuit is electrically connected with a first resistor; the connecting end of the first resistor is electrically connected with a first diode, a second diode and a second resistor. The input interface protection circuit provided by the utility model is provided with two stages of protection circuits, namely a first-stage electrostatic discharge protection circuit and a second-stage forward and reverse voltage clamping protection circuit, so that a safer protection function and a higher antistatic grade can be provided; the forward amplitude limiting voltage value is determined by the high-current parallel voltage stabilizing circuit, and the adjustable range of the forward amplitude limiting voltage value is large, namely + 1.24 V to + 18.0 V, so that the forward amplitude limiting circuit can be more conveniently applied to various level input signals, and has stronger universality and portability.

Description

Technical Field

[0001] The utility model relates to the field of interface protection circuits, in particular to an input interface protection circuit. Background Art

[0002] Electronic equipment refers to equipment that is composed of electronic components such as integrated circuits, transistors, and electron tubes, and uses electronic technology (including) software to function, including electronic computers and robots controlled by electronic computers, numerical control or program control systems, etc.

[0003] When electronic devices are in use, especially the external interfaces of electronic devices, they are always threatened by static electricity in the use environment. If interface protection measures are not taken, when the interface comes into contact with the human body, air or other objects with electric charge, it will inevitably cause static electricity discharge to damage the chip circuit. In addition, there are many types of interfaces with different voltages, so various protection circuits are needed to protect the circuit, which reduces the versatility of the interface protection circuit.

[0004] Therefore, it is necessary to provide an input interface protection circuit to solve the above technical problems. Utility Model Content

[0005] The utility model provides an input interface protection circuit, which solves the problem that electrostatic discharge damages chip circuits and various protection circuits are required for different voltages, reducing the versatility of the protection circuit.

[0006] In order to solve the above technical problems, the utility model provides an input interface protection circuit, comprising:

[0007] External input;

[0008] An electrostatic discharge protection circuit, wherein the electrostatic discharge protection circuit is electrically connected to the connection end of the external input, and the electrostatic discharge protection circuit is grounded, the connection end of the electrostatic discharge protection circuit is electrically connected to a first resistor, the connection ends of the first resistor are electrically connected to a first diode, a second diode, and a second resistor, respectively, the anode of the first diode is grounded, the connection end of the second diode is electrically connected to a PNP transistor, the connection circuit of the second diode and the PNP transistor is electrically connected to a first capacitor and a second capacitor, respectively, and the connection ends of the two resistors are electrically connected to a processor;

[0009] A third capacitor, the third capacitor is electrically connected to the connection end of the PNP transistor, the connection circuit of the third capacitor and the PNP transistor is electrically connected to a third resistor and a voltage regulator diode, respectively, the voltage regulator diode and the other connection end of the third capacitor are both connected to a sixth resistor, the voltage regulator diode and the sixth resistor are both grounded, the connection end of the third resistor is respectively connected to a fourth resistor and a fifth resistor, the connection end of the fourth resistor is electrically connected to an input power supply, and the connection end of the fifth resistor is electrically connected to the sixth resistor.

[0010] Preferably, the electrostatic discharge protection circuit is a bidirectional transient suppression diode.

[0011] Preferably, the first diode and the second diode are both medium-power transistors.

[0012] Preferably, the two resistors, the first capacitor, the second capacitor and the PNP transistor are all grounded.

[0013] Preferably, the second resistor is a path discharge resistor, which is used to prevent path charge accumulation from forming high-voltage discharge that damages the processor input port.

[0014] Preferably, the fourth resistor is a current limiting resistor of a voltage stabilizer.

[0015] Preferably, the third capacitor plays a role of power supply filtering.

[0016] Compared with the related art, the input interface protection circuit provided by the utility model has the following beneficial effects:

[0017] The utility model provides an input interface protection circuit, which is provided with two-level protection circuits: a first-level electrostatic discharge protection circuit and a second-level forward and reverse voltage clamping protection circuit, so as to provide a safer protection function and a higher anti-static level; the forward limiting voltage value is determined by a high-current parallel voltage stabilizing circuit, and the forward limiting voltage value has a large adjustable range, that is, +1.24V∽+18.0V, and can be more conveniently applied to a variety of level input signals, and has strong versatility and portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 The present invention is a schematic structural diagram of a preferred embodiment of an input interface protection circuit provided by the present invention.

[0019] Numbers in the figure: 1. external input, 2. electrostatic discharge protection circuit, 3. first resistor, 4. second resistor, 5. first diode, 6. second diode, 7. processor, 8. first capacitor, 9. second capacitor, 10. PNP transistor, 11. third resistor, 12. Zener diode, 13. third capacitor, 14. fourth resistor, 15. fifth resistor, 16. input power supply, 17. sixth resistor. DETAILED DESCRIPTION

[0020] The utility model is further described below in conjunction with the accompanying drawings and implementation modes.

[0021] Please refer to Figure 1 ,in, Figure 1 The schematic diagram of a preferred embodiment of an input interface protection circuit provided by the utility model is as follows: An input interface protection circuit comprises: an external input 1;

[0022] An electrostatic discharge protection circuit 2, wherein the electrostatic discharge protection circuit 2 is electrically connected to the connection end of the external input, and the electrostatic discharge protection circuit 2 is grounded, the connection end of the electrostatic discharge protection circuit 2 is electrically connected to a first resistor 3, the connection ends of the first resistor 3 are electrically connected to a first diode 5, a second diode 6 and a second resistor 4, respectively, the positive electrode of the first diode 5 is grounded, the connection end of the second diode 6 is electrically connected to a PNP transistor 10, the connection circuit of the second diode 6 and the PNP transistor 10 is electrically connected to a first capacitor 8 and a second capacitor 9, respectively, and the connection ends of the two resistors 4 are electrically connected to a processor 7;

[0023] A third capacitor 13, the third capacitor 13 is electrically connected to the connection end of the PNP transistor 10, the connection circuit of the third capacitor 13 and the PNP transistor 10 is electrically connected to a third resistor 11 and a voltage-stabilizing diode 12, respectively, the voltage-stabilizing diode 12 and the other connection end of the third capacitor 13 are both connected to a sixth resistor 17, the voltage-stabilizing diode 12 and the sixth resistor 17 are both grounded, the connection end of the third resistor 11 is respectively connected to a fourth resistor 14 and a fifth resistor 15, the connection end of the fourth resistor 14 is electrically connected to an input power supply 16, and the connection end of the fifth resistor 15 is electrically connected to the sixth resistor 17.

[0024] The electrostatic discharge protection circuit 2 is a bidirectional transient suppression diode.

[0025] The first diode 5 and the second diode 6 are both medium-power transistors.

[0026] The two resistors 4 , the first capacitor 8 , the second capacitor 9 and the PNP transistor 10 are all grounded.

[0027] The second resistor 4 is a path discharge resistor, which is used to prevent the accumulation of path charges to form high-voltage discharge and damage the input port of the processor 7.

[0028] The fourth resistor 14 is a current limiting resistor of the voltage stabilizer.

[0029] The third capacitor 13 plays a role of power supply filtering.

[0030] The electrostatic discharge protection circuit 2 is mainly a TVS diode V1 directly connected to the external input port. The TVS diode is the first-level protection circuit. When the interface has a high voltage of electrostatic discharge, the TVS diode will break down and discharge to reduce the voltage value of the high voltage.

[0031] The first diode 5 and the second diode 6 are forward and reverse connected Schottky diodes to form a forward and reverse voltage clamping protection circuit. The second diode 6 is connected in the forward direction to connect to the high current parallel voltage stabilizing circuit to complete the forward voltage limiting protection function, and the first diode 5 is connected in the reverse direction to directly ground to complete the reverse voltage limiting protection function;

[0032] The resistor, capacitor, PNP transistor and adjustable precision parallel regulator form a high current parallel voltage regulator circuit, the main function of which is to provide a protection threshold voltage value for the forward voltage limiting second diode 6. The regulated voltage value Va generated by the high current parallel voltage regulator circuit is applied to the cathode of the second diode 6 through the filtering first capacitor 8 and the second capacitor 9. The regulated voltage value Va generated by the high current parallel voltage regulator circuit is slightly higher than the actual value of the input signal; when the input signal voltage value is lower than the regulated voltage value Va, the second diode 6 is turned off, and when the input signal voltage value is higher than the regulated voltage value Va, the second diode 6 is turned off. The second diode 6 is turned on, which causes the emitter voltage of the PNP transistor 10 to increase, and then the voltage of the reference pin of the voltage reference source chip Zener diode 12 increases, which in turn reduces the base voltage of the PNP transistor 10, thereby increasing the conductivity of the PNP transistor 10, and the current flows from the emitter to the collector to the ground. Finally, the cathode voltage of the second diode 6 remains Va, and the final limiting voltage value is approximately Va plus the conduction voltage value of the Schottky diode, thereby playing a forward overvoltage limiting role. The voltage range of the stabilizing voltage value Va is: +1.24V∽+18.0V;

[0033] When the signal input interface protection circuit plays a protective role, it will not affect the power supply of the protection circuit, and will not interfere with other circuits of the system through the power supply. It has power isolation and excellent electromagnetic compatibility.

[0034] The regulated voltage value Va generated by the high current parallel voltage regulator circuit is set to +3.3V, and the conduction voltage of the Schottky diode is about 0.3V, that is, the forward limiting voltage value of the input port is set to about +3.6V, and the reverse limiting function is realized by the reverse connection of the first diode 5, and the reverse limiting voltage value of the input port is set to about -0.3V, and the final limiting output level range is -0.3V∽+3.6V. The limiting output level is less than the maximum withstand voltage range of the processor port, which can effectively protect the safety of the processor port;

[0035] The method for determining the regulated voltage value Va generated by the high current parallel regulated circuit is Va=(1+R3 / R4)*VREF. In this embodiment, VREF=1.24V;

[0036] The interface ESD and surge protection functions of the input signal are +3.3V CMOS level and the signal frequency is 10Mbps. The electrostatic and surge protection levels meet the following requirements:

[0037] IEC61000-4-2(ESD)±25kV(air),±20kV(contact);

[0038] IEC61000-4-5(LIGHTING)4.0A(8 / 20μs);

[0039] The adjustable range of the forward limiting voltage is +1.24V∽+18.0V.

[0040] The working principle of an input interface protection circuit provided by the utility model is as follows:

[0041] The external input 1 signal is directly connected to the electrostatic discharge protection circuit 2, and the electrostatic discharge protection circuit 2 realizes the first-level electrostatic discharge protection function. The electrostatic discharge protection circuit 2 is connected to the first resistor 3, and the first resistor 3 realizes the current limiting protection function when the electrostatic input is applied. Then the first resistor 3 is connected to the cathode of the first diode 5 and the anode of the second diode 6. The anode of the first diode 5 is grounded, and the cathode of the second diode 6 is connected to the output of the high-current parallel voltage regulator circuit. The first capacitor 8 and the second capacitor 9 are output filters. The input of the processor 7 is connected to the second resistor 4, and the second resistor 4 is a path discharge resistor to prevent the accumulation of path charges to form high-voltage discharge and damage the input port of the processor 7. The input power supply 16 is the input power supply of the high-current parallel voltage regulator circuit, the fourth resistor 14 is the current limiting resistor of the voltage regulator, the third resistor 11 provides the base voltage path of the PNP transistor, the third capacitor 13 plays the role of power supply filtering, and the fifth resistor 15 and the sixth resistor 17 jointly determine the voltage regulation value Va.

[0042] Compared with the related art, the input interface protection circuit provided by the utility model has the following beneficial effects:

[0043] By setting up two levels of protection circuits: the first level electrostatic discharge protection circuit and the second level forward and reverse voltage clamping protection circuit, it can provide safer protection functions and higher anti-static levels; the forward limiting voltage value is determined by the high current parallel voltage stabilization circuit, and the forward limiting voltage value has a large adjustable range, that is, +1.24V∽+18.0V, which can be more conveniently applied to a variety of level input signals, and has strong versatility and portability.

[0044] The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the specification and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An input interface protection circuit, characterized in that: include: External input; An electrostatic discharge protection circuit, wherein the electrostatic discharge protection circuit is electrically connected to the connection end of the external input, and the electrostatic discharge protection circuit is grounded, the connection end of the electrostatic discharge protection circuit is electrically connected to a first resistor, the connection ends of the first resistor are electrically connected to a first diode, a second diode, and a second resistor, respectively, the anode of the first diode is grounded, the connection end of the second diode is electrically connected to a PNP transistor, the connection circuit of the second diode and the PNP transistor is electrically connected to a first capacitor and a second capacitor, respectively, and the connection ends of the two resistors are electrically connected to a processor; A third capacitor, the third capacitor is electrically connected to the connection end of the PNP transistor, the connection circuit of the third capacitor and the PNP transistor is electrically connected to a third resistor and a voltage regulator diode, respectively, the voltage regulator diode and the other connection end of the third capacitor are both connected to a sixth resistor, the voltage regulator diode and the sixth resistor are both grounded, the connection end of the third resistor is respectively connected to a fourth resistor and a fifth resistor, the connection end of the fourth resistor is electrically connected to an input power supply, and the connection end of the fifth resistor is electrically connected to the sixth resistor.

2. The input interface protection circuit according to claim 1, characterized in that: The electrostatic discharge protection circuit is a bidirectional transient suppression diode.

3. The input interface protection circuit according to claim 1, characterized in that: The first diode and the second diode are both medium power transistors.

4. The input interface protection circuit according to claim 1, characterized in that: The two resistors, the first capacitor, the second capacitor and the PNP transistor are all grounded.

5. The input interface protection circuit according to claim 1, characterized in that: The second resistor is a path discharge resistor, which is used to prevent the path charge accumulation from forming high-voltage discharge to damage the processor input port.

6. The input interface protection circuit according to claim 1, characterized in that: The fourth resistor is a current limiting resistor of the voltage stabilizer.

7. The input interface protection circuit according to claim 1, characterized in that: The third capacitor plays a role of power supply filtering.

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