Embedded multi-chip integrated mixed packaging structure

Abstract

The utility model discloses an embedded multi-chip integrated mixed packaging structure, which relates to the technical field of semiconductor packaging and comprises a substrate, a controller, a memory chip, a flash memory chip and epoxy resin for packaging the controller, the memory chip and the flash memory chip on the substrate. The controller is fixed on the top surface of the substrate through the DAF film, and the controller is electrically connected with the substrate through a gold wire; the number of the memory chips is two, the two memory chips are both fixed on the top surface of the substrate through the DAF film, according to the scheme, through integrated packaging of multiple chips and an embedded design concept, the large-capacity memory chips, the large-capacity flash memory chip and the controller are stacked on one surface, higher performance and larger capacity in a small-size packaging structure are achieved, and the size of the controller is reduced. The effects of miniaturization and thinning of intelligent products are achieved, so that the iterative development of terminal products is promoted; by utilizing the advantage of high integration level, the circuit design can be simplified for terminal manufacturers, the shipment period is shortened, and the cost is correspondingly reduced.

Description

Technical Field

[0001] The utility model relates to an embedded multi-chip integrated hybrid packaging structure, belonging to the technical field of semiconductor packaging. Background Art

[0002] In the traditional packaging form, the eMMC and LPDDR are isolated and tiled, and chips with different functions can only be arranged on one surface. With a fixed outer size, it is impossible to carry out packaging and design with higher integration. Utility Model Content

[0003] The utility model aims to overcome the deficiencies of the prior art and provide an embedded multi-chip integrated hybrid packaging structure.

[0004] To achieve the above-mentioned purpose, the technical solution adopted by the utility model is: an embedded multi-chip integrated hybrid packaging structure, comprising a substrate, a controller, a memory chip, a flash memory chip and an epoxy resin that encapsulates the controller, the memory chip and the flash memory chip on the substrate; the controller is fixed on the top surface of the substrate through a DAF film, and the controller is electrically connected to the substrate through a gold wire; two memory chips are provided, and the two memory chips are fixed on the top surface of the substrate through a DAF film, and the two memory chips are respectively located on both sides of the controller and electrically connected to the substrate; the flash memory chip is fixed above the two memory chips through the DAF film, the flash memory chip is electrically connected to the substrate, and the two sides of the flash memory chip are respectively flush with the outer sides of the two memory chips.

[0005] Preferably, the two memory chips are both double-layer stacked structures, the upper memory chip and the lower memory chip are connected and fixed via a DAF film, and both layers of memory chips are electrically connected to the substrate via gold wires.

[0006] Preferably, the flash memory chip is a double-layer stacked structure, the upper and lower layers of flash memory chips are connected and fixed by a DAF film, and the upper and lower layers of flash memory chips are electrically connected by gold wires, and each layer of flash memory chips is electrically connected to the substrate by gold wires.

[0007] Preferably, two ends of the epoxy resin are flush with two ends of the substrate.

[0008] Preferably, solder balls are soldered on the bottom surface of the substrate.

[0009] Due to the application of the above technical solution, the utility model has the following advantages compared with the prior art:

[0010] The utility model discloses an embedded multi-chip integrated hybrid packaging structure, which, through the integrated packaging of multiple chips and utilizing the embedded design concept, stacks large-capacity memory chips, flash memory chips and controllers on one surface, thereby realizing higher performance and larger capacity in a small-volume packaging structure, achieving the effect of miniaturization and thinning of smart products, thereby promoting the iterative development of terminal products; utilizing the advantages of high integration, it is possible for terminal manufacturers to simplify circuit design, shorten delivery cycles and reduce costs accordingly. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The technical solution of the utility model is further described below in conjunction with the accompanying drawings:

[0012] Attached Figure 1 The present invention is a schematic structural diagram of an embedded multi-chip integrated hybrid packaging structure.

[0013] In the figure: 1. substrate; 2. controller; 3. memory chip; 4. flash memory chip; 5. epoxy resin; 6. DAF film; 7. gold wire; 8. solder ball. DETAILED DESCRIPTION

[0014] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0015] As attached Figure 1 As shown, an embedded multi-chip integrated hybrid packaging structure described in the utility model includes a substrate 1, a controller 2, a memory chip 3, a flash memory chip 4, and an epoxy resin 5 that encapsulates the controller 2, the memory chip 3 and the flash memory chip 4 on the substrate 1, wherein the two ends of the epoxy resin 5 are flush with the two ends of the substrate 1 to facilitate packaging.

[0016] The controller 2 is fixed on the top surface of the substrate 1 through the DAF film 6, and the controller 2 is electrically connected to the substrate 1 through the gold wire 7; two memory chips 3 are provided, and the two memory chips 3 are fixed on the top surface of the substrate 1 through the DAF film 6, and the two memory chips 3 are respectively located on both sides of the controller 2 and electrically connected to the substrate 1; the flash memory chip 4 is fixed above the two memory chips 3 through the DAF film 6, the flash memory chip 4 is electrically connected to the substrate 1, and the two sides of the flash memory chip 4 are respectively flush with the outer sides of the two memory chips 3. By embedding the controller 2 in the middle area of ​​the two memory chips 3 and then fixing the flash memory chip 4 above the two memory chips 3, a more space-saving effect can be achieved.

[0017] The two memory chips 3 are both double-layer stacked structures. The upper memory chip 3 is fixedly connected to the lower memory chip 3 via a DAF film 6 . Both layers of memory chips 3 are electrically connected to the substrate 1 via gold wires 7 .

[0018] The flash memory chip 4 is a double-layer stacked structure, the upper and lower layers of flash memory chips 4 are connected and fixed by a DAF film 6, and the upper and lower layers of flash memory chips 4 are electrically connected by a gold wire 7, and each layer of flash memory chips 4 is electrically connected to the substrate 1 through the gold wire 7.

[0019] The above-mentioned memory chip 3 is stacked up through the buried wire technology to meet the high capacity requirement, and then the memory chip 3 and the controller 2 are embedded under the flash memory chip 4. The ultra-thin wafer stacking technology, ultra-low line arc buried wire technology and narrow channel plastic packaging material filling technology are adopted, so that the packaging structure of this scheme can achieve the designed high-density and low-power consumption performance.

[0020] Solder balls 8 are soldered on the bottom surface of the substrate 1 .

[0021] The processing process of the packaging structure of this scheme is as follows:

[0022] Step 1: Substrate design;

[0023] Design the substrate that meets the requirements according to the requirements.

[0024] Step 2: Paste the controller;

[0025] The controller is tightly combined with the substrate through the wire bonding process to achieve electrical conduction with the substrate.

[0026] Step 3: Mount the memory chip;

[0027] The memory chip is mounted on the substrates on both sides of the controller and connected to the substrates through a wire embedding process to achieve conduction.

[0028] Step 4: Mount the flash memory chip;

[0029] The flash memory chip is mounted on top of the memory chip, and the chip is connected to the substrate through the same wire bonding process to achieve electrical conduction.

[0030] Step 5: Plastic sealing;

[0031] Use special plastic sealing materials to seal the entire surface at one time.

[0032] Step 6: Planting the ball;

[0033] Select appropriate solder balls and carry out ball planting.

[0034] Step 7: Cut into pieces;

[0035] Use a cutting knife to cut the Strip into individual particles.

[0036] Compared with the prior art, the packaging structure of this solution is an integrated packaging of multiple chips. By utilizing the embedded design concept, a large-capacity memory chip 3, a flash memory chip 4 and a controller 2 are stacked on one surface, achieving the effect of miniaturization and thinning of smart products, thereby promoting the iterative development of terminal products.

[0037] The above are only specific application examples of the utility model and do not constitute any limitation to the protection scope of the utility model; any technical solutions formed by equivalent transformation or equivalent replacement shall fall within the protection scope of the utility model.

Claims

1. An embedded multi-chip integrated hybrid packaging structure, characterized in that: The invention comprises a substrate (1), a controller (2), a memory chip (3), a flash memory chip (4), and an epoxy resin (5) for encapsulating the controller (2), the memory chip (3) and the flash memory chip (4) on the substrate (1); the controller (2) is fixed on the top surface of the substrate (1) through a DAF film (6), and the controller (2) is electrically connected to the substrate (1) through a gold wire (7); two memory chips (3) are provided, and the two memory chips (3) are fixed on the top surface of the substrate (1) through a DAF film (6), and the two memory chips (3) are respectively located on both sides of the controller (2) and are electrically connected to the substrate (1); the flash memory chip (4) is fixed above the two memory chips (3) through the DAF film (6), the flash memory chip (4) is electrically connected to the substrate (1), and the two sides of the flash memory chip (4) are respectively flush with the outer sides of the two memory chips (3).

2. The embedded multi-chip integrated hybrid packaging structure according to claim 1, characterized in that: The two memory chips (3) are both double-layer stacked structures, the upper memory chip (3) and the lower memory chip (3) are connected and fixed via a DAF film (6), and the two layers of memory chips (3) are electrically connected to the substrate (1) via gold wires (7).

3. The embedded multi-chip integrated hybrid packaging structure according to claim 1, characterized in that: The flash memory chip (4) is a double-layer stacked structure, the upper and lower layers of flash memory chips (4) are connected and fixed via a DAF film (6), and the upper and lower layers of flash memory chips (4) are electrically connected via a gold wire (7), and each layer of flash memory chips (4) is electrically connected to the substrate (1) via the gold wire (7).

4. The embedded multi-chip integrated hybrid packaging structure according to claim 1, characterized in that: The two ends of the epoxy resin (5) are flush with the two ends of the substrate (1).

5. The embedded multi-chip integrated hybrid packaging structure according to claim 1, characterized in that: A tin ball (8) is welded on the bottom surface of the substrate (1).

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