S2500 high-performance intensive universal control module

Abstract

The utility model discloses an S2500 high-performance intensive general control module, which comprises a main chip and a VPX connector, the model of the main chip is a Tengyun S2500 / 64 core processor, a PCIE Switch controller and an ASPEED BMC chip are arranged between the main chip and the VPX connector, in the S2500 high-performance intensive general control module, the domestic Tengyun S2500 / 64 core processor is used as a core to complete data comprehensive processing at the front end, and the VPX connector is used for connecting the Tengyun S2500 / 64 core processor. And an operation resource support is provided for realizing functions of task management, system management, data fusion, comprehensive detection, comprehensive identification and the like. And meanwhile, the processor can provide PCIE, DDR4 and debugging serial interfaces to the outside, so that the intellectualization and the high performance of the module are improved.

Description

Technical Field

[0001] The utility model relates to the technical field of power electronics, in particular to an S2500 high-performance intensive universal control module. Background Art

[0002] With the continuous improvement of modern technology, in application scenarios such as radar signal processing and data processing that require high-speed and intensive computing, the requirements for the integration of control modules are becoming increasingly higher. Not only that, but they also need to maintain a high-performance working state. Therefore, it is imperative to design a high-performance and intensive general control module. Utility Model Content

[0003] In order to overcome the above-mentioned deficiencies, the utility model provides an S2500 high-performance intensive universal control module.

[0004] The utility model achieves the above-mentioned purpose through the following technical solutions:

[0005] An S2500 high-performance intensive universal control module includes a main chip and a VPX connector. The model of the main chip is the Tengyun S2500 / 64 core processor. A PCIE Switch controller and an ASPEED BMC chip are arranged between the main chip and the VPX connector.

[0006] Preferably, the model of the PCIE Switch controller is PEX8796, the main chip is connected to the PCIE Switch controller via 1 PCIE X16, the model of the ASPEED BMC chip is AST2400, the main chip is connected to the ASPEED BMC chip via 1 PCIE X1, the Tengyun S2500 / 64 core processor can lead to 1 PCIE X16 and 1 PCIE X1, and the 1 PCIE X1 interface of the main chip is used to connect to the BMC chip (AST2400) for expanding the IPMB interface and display interface.

[0007] Preferably, one PCIE X8 of the PCIE Switch controller is connected to the VPX connector via a 10GbE network control chip, so as to expand two 10GBase-KR Ethernet interfaces; one PCIE X8 is connected to another 10GbE network control chip and the VPX connector, so as to expand two 10GXAUI Ethernet interfaces;

[0008] There are also 3 PCIE X8 signals connected to the VPX connector, which can be expanded through the rear plug-in board. These 3 PCIE X8 signals can be split into 2 PCIE X4 signals; 1 PCIE X4 signal is used to connect to Netcom's WX1860AL2 chip, used to expand 2 1000GBase-X interfaces, and then output to the VPX connector; 1 PCIE X1 signal is used to connect to the i210 chip, used to expand the network interface, and led out to the front panel; 1 PCIE X1 signal is used to connect to the 88SE9215 chip, used to expand the SATA interface, and can connect to a SATA hard drive; 1 PCIE X1 signal is used to connect to the upd720201 chip, used to expand the front panel USB interface.

[0009] Preferably, a CPLD chip is provided between the ASPEED BMC chip and the main chip, and AST2400 is used as a management controller. Sensors are used to monitor and collect board-level temperature, voltage, current and other signals, analyze position identification coding information, and be responsible for system power-on and reset monitoring, and cooperate with the CPLD chip EF2L15BG256B to complete the power timing management of the entire board.

[0010] Preferably, the CPLD chip model is EF2L15BG256B.

[0011] Preferably, the model of the 10GbE network control chip is Intel 85299.

[0012] The beneficial effect of the utility model is that the S2500 high-performance intensive universal control module uses the domestic Tengyun S2500 / 64 core processor as the core to complete the front-end data comprehensive processing and provide computing resource support for the realization of tasks management, system management, data fusion, comprehensive detection, comprehensive identification and other functions. At the same time, the processor can provide PCIE, DDR4, and debug serial port interfaces to the outside, which improves the intelligence and high performance of the module. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will be described by way of examples with reference to the accompanying drawings, in which:

[0014] Figure 1 It is a principle block diagram of the utility model;

[0015] Figure 2 This is a PCIE bus connection schematic diagram of the utility model;

[0016] Figure 3 It is a block diagram of the health status monitoring and management unit of the utility model;

[0017] Figure 4 It is a design block diagram of the IPMB interface of the utility model.

[0018] Figure 5 It is a hot-swap design block diagram of the utility model.

[0019] Figure 6 This is a block diagram of a PCIE clock network of the present utility model.

[0020] Figure 7 This is a system reset block diagram of the utility model.

[0021] Figure 8 This is a power-on timing relationship diagram of the domestically produced Tengyun S2500 / 64 core processor of the utility model. DETAILED DESCRIPTION

[0022] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0023] like Figure 1 As shown, an S2500 high-performance dense universal control module includes a main chip and a VPX connector. The model of the main chip is Tengyun S2500 / 64 core processor. A PCIE Switch controller and an ASPEED BMC chip are arranged between the main chip and the VPX connector.

[0024] The processor unit is based on the Tengyun S2500 / 64 core processor, including DDR4 memory controller, PCIE, serial port and other parts. The Tengyun S2500 / 64 core processor is a domestic processing chip launched by Tianjin Feiteng Information Technology Co., Ltd. It adopts the ARM-V8 64bit architecture. It optimizes storage access latency by integrating efficient processor cores, large-scale consistent storage architecture based on data affinity, and hierarchical two-dimensional Mesh interconnection network, providing industry-leading computing performance, memory access bandwidth and IO expansion capabilities. The peak processing capacity of the Tengyun S2500 / 64 core processor reaches 563.2GFlops@2.2GHz, which can meet the system performance requirements; the chip has 64 ARM64 processing cores and a typical power consumption of 136W.

[0025] The Tengyun S2500 / 64 core processor contains 4 UART controllers, 1 SPI interface, 1 LPC interface, 2 I2C controllers and 4 8-bit GPIO interfaces; it connects to Flash through the SPI interface to store local configuration and startup (Uboot) information; it brings out JTAG, UART and other interfaces for debugging, and brings out I2C, LPC, GPIO for system use; it provides 1 16x PCIE3.0 interface, 1 FIT interface for interconnecting multiple CPUs and 1 1x PCIE3.0 interface to the outside, and can further expand SATA, Ethernet, VGA, USB and other interfaces to meet the needs of electronic disk storage and external interconnection bus expansion, and meet the functional performance requirements of the general control module.

[0026] Tengyun S2500 / 64 core processor integrates 8 DDR4 memory controllers MC0, MC1, MC2, MC3, MC4, MC5, MC6 and MC7. Taking into account a series of environmental factors such as heat dissipation, vibration, and impact, the design adopts the board-mounted memory particle method to complete the board memory unit design. At the same time, in order to save layout and improve layout utilization, 8 channels of 4GB each are used to achieve the technical indicator memory capacity of 32GB.

[0027] In this design, DDR4 memory chip CXDQ3BFAM-WG is selected as the DDR4 memory chip of the board. CXDQ3BFAM-WG is an 8Gbit memory chip launched by Changxin. Because a channel requires a total of 4GB capacity, each channel requires 5 memory chips (including 1pcs ECC chip). The main technical indicators of Changxin CXDQ3BFAM-WG memory are as follows.

[0028] like Figure 2 As shown, the model of the PCIE Switch controller is PEX8796, the main chip is connected to the PCIE Switch controller via 1 PCIE X16, the model of the ASPEED BMC chip is AST2400, the main chip is connected to the ASPEED BMC chip via 1 PCIE X1, the Tengyun S2500 / 64 core processor can lead out 1 PCIE X16 and 1 PCIE X1, the 1 PCIE X1 interface of the main chip is used to connect the BMC chip, used to expand the IPMB interface and display interface, in addition to the necessary interfaces, the module also requires 3 PCI-E3.0x8 expansion buses to expand to the VPX connector. 3 PCI-E3.0x8 (each PCI-E x8 can be configured as 2 x4) are led out by PEX8796, and PCI-E 3.0x8 is directly output by the processor PCIE bus.

[0029] Specifically, one PCIE X8 of the PCIE Switch controller is connected to the VPX connector via a 10GbE network control chip, so as to expand two 10GBase-KR Ethernet interfaces; one PCIE X8 is connected to another 10GbE network control chip and the VPX connector, so as to expand two 10G XAUI Ethernet interfaces;

[0030] There are also 3 PCIE X8 signals connected to the VPX connector, which can be expanded through the rear plug-in board. These 3 PCIE X8 signals can be split into 2 PCIE X4 signals; 1 PCIE X4 signal is used to connect to Netcom's WX1860AL2 chip, used to expand 2 1000GBase-X interfaces, and then output to the VPX connector; 1 PCIE X1 signal is used to connect to the i210 chip, used to expand the network interface, and led out to the front panel; 1 PCIE X1 signal is used to connect to the 88SE9215 chip, used to expand the SATA interface, and can connect to a SATA hard drive; 1 PCIE X1 signal is used to connect to the upd720201 chip, used to expand the front panel USB interface.

[0031] like Figure 3 As shown, the BMC health status monitoring and management unit is based on AST2400 of Xinye Technology, which can collect and monitor data such as temperature, voltage, current, CPU unit status, etc., and can also realize remote status monitoring and management. A CPLD chip is arranged between the ASPEEDBMC chip and the main chip. AST2400 is used as a management controller. It monitors and collects board-level temperature, voltage, current and other signals through sensors, analyzes position identification coding information, is responsible for system power-on and reset monitoring, and cooperates with the CPLD chip EF2L15BG256B to complete the power timing management of the entire board.

[0032] In order to monitor the system temperature, a digital temperature sensor is added to the system, which can monitor the temperature range of -55--+125℃ with an accuracy of ±2℃. The CPU temperature is collected and the information is sent to the BMC unit through I2C.

[0033] In order to monitor the working condition of the system, its built-in ADC channel is used to monitor the voltage and current status of 5V, 3.3V, 2.5V, 1.2V, 1.1V, 1.0 and 12V. The system can read its output data through the I2C interface. If an abnormality occurs, an alarm and reset interrupt signal will be generated.

[0034] The BMC unit has an NSCI interface, which is connected to the I350 network card through this interface. Remote customers can monitor and capture the hardware status information of the local blade.

[0035] At the same time, the BMC unit can also obtain the CPU main frequency, model, number of cores and other working status through I2C and report it to the system.

[0036] Specifically, the CPLD chip model is EF2L15BG256B.

[0037] Specifically, the model of the 10GbE network control chip is Intel 85299.

[0038] The 2-way 10GbE-KR Ethernet optical interface design adopts the Intel 85299 solution, which can meet the latest network requirements of enterprise data centers. It is applied on servers and supports the hypervisor data sorting function. It effectively balances the network load on the CPU core, improves data throughput and CPU utilization, and shows excellent performance in multi-CPU processor systems. The 2-way 10GbE-XAUI interface design also adopts the Intel 82599 solution.

[0039] The 82599 network controller has excellent noise immunity and supports 300-meter fiber connections, making it suitable for servers and high-end devices. It can easily integrate any PCI Express X8 into a 10 Gigabit network and optimizes performance so that system I / O is no longer a bottleneck for high-end network applications.

[0040] The 82599 network controller with two fully integrated 10 Gigabit Ethernet media access control (MAC) and SFP+ ports is an ideal solution for deploying multiple networks and critical network applications on high-performance servers.

[0041] The 82599 interface configuration resources are relatively rich, supporting 2-way 10GBASE-KR / KX, 2-way SFI or 2-way XAUI interfaces.

[0042] The 1-channel Gigabit Ethernet interface design adopts the Intel I210 solution, which has a fully integrated Gigabit Ethernet media access control (MAC) and physical layer (PHY) blade. At the same time, the solution has the characteristics of low power consumption and easy software adaptation.

[0043] Intel I210 single-port Gigabit Ethernet controller with advanced power saving and flexible I / O virtualization technology. The Intel I210 series builds on Intel's history of delivering Ethernet product design flexibility and inbox driver support. The 1Gb port has enhanced power saving and market-leading flexible I / O virtualization including VMDq and SR-IOV. The I210 supports IEEE802.3az EEE so during periods of low network activity, EEE reduces the power consumption of the Ethernet connection by negotiating with the switch port to transition to a low power idle (LPI) state. This will reduce power to approximately 50% of its normal operation saving power in the network and switch ports. When an increase in traffic is detected the controller and switch quickly returns to full power to handle the increased traffic, supporting 1000BASE-T and 100BASE-T.

[0044] The main technical indicators of I210 network controller are as follows:

[0045] Support PCIe Gen2x1 host interface, support x1, x2, x4 adaptive;

[0046] Support 1-port 1GbE network interface;

[0047] MDI interface supports 1000BASE-T, 100BASE-TX (IEEE 802.3);

[0048] SerDes interface supports 1000BASE-BX and 1000BASE-KX;

[0049] SGMII supports external PHY to expand Gigabit electrical port;

[0050] Supports 1 NCSI interface.

[0051] The later Gigabit Ethernet interface design adopts the solution of Netcom WX1860AL2, which can provide dual-channel Gigabit Ethernet (1000MBase-X). At the same time, this solution has the characteristics of low power consumption and easy software adaptation. The main technical indicators of this chip are as follows:

[0052] Support PCIE V2.1 standard;

[0053] Supports up to 2 Gigabit Ethernet channels, each supporting MDI interface output;

[0054] Support 802.1q VLAN protocol;

[0055] Support network signal self-detection;

[0056] The module is designed with the onboard AST2400 BMC chip, with a main frequency of 400MHz; it supports 1 VGA, a display resolution of up to 1080P, a maximum video memory of 512MB DDR3, and supports 2D graphics rendering.

[0057] ASPEED's AST2400 is the core control chip of the BMC unit. It adopts ARM9 architecture, 400MHz core frequency, 16-bit DDR2 / DDR3 memory controller, and has multiple Gigabit Ethernet, I2C, SPI, VGA and other interfaces. The rich interface types can facilitate communication with various functional units of the system and are compatible with various sensors. The chip has been used in the server BMC field for many years, with mature system applications and low power consumption.

[0058] In order to facilitate users to remotely manage and monitor the universal dense universal control module without the need for users to operate in front of the machine, the AST2400 WEBSERVER management interface can support the KVM OVER IP function.

[0059] This module needs to provide 1 RS232 full-function serial port resource, which can be achieved by using the UART interface of the Feiteng S2500 chip. The S2500 integrates 4 UARTs, one of which is a 9-line full-function serial port, and three are 3-line serial ports. The debug serial port is UART1, the full-function serial port is UART0, and the 3-line serial ports are UART2 and UART3. Use the corresponding level conversion chip to lead out 1 RS232 function interface and 1 RS232 debug interface respectively.

[0060] The serial port of Feiteng S2500 supports a maximum baud rate of 115.2Kbps.

[0061] The full-function RS232 conversion chip can be selected from the domestic UM3243EEUS produced by Yinglian Electronics. This chip supports 3V to 5.5V power supply, 0.1μA automatic shutdown current, 250kbps baud rate, 3 transmitters / 5 receivers, and an intelligent RS-232 transceiver with enhanced ESD protection.

[0062] The technical requirements of this module are to provide at least 4 USB interfaces and 4 USB2.0 interfaces on the front panel. The USB interfaces are derived from the IO expansion chip upd720201.

[0063] The module needs to provide at least 2 SATA interfaces; this blade uses 88SE9215 SATA controller to expand SATA interfaces and provide 4 SATA interfaces. Onboard 2-way SATA solid state disk. The board reserves msata connector to expand msata SSD hard disk.

[0064] The sensors on the module monitor the temperature, voltage, fan working status, power supply and other information of each core component in real time. The BMC chip AST2400 obtains the data from the sensor, encapsulates it with the standard IPMI protocol and sends it to the intelligent platform management bus through the physical layer I2C protocol. The I2C isolation chip is implemented using the domestic NCA9617 of Naxin Micro.

[0065] The hot-swap unit is implemented using the domestically produced BT9352, and the soft-start time is set at around 2ms, which can suppress the surge current when the blade is powered on.

[0066] The BT9352 uses an external N-channel MOSFET to produce a nearly ideal diode. It replaces a high-power Schottky diode and the associated heat sink, saving power and board area. The ideal diode function enables low-loss power supply hold-up applications.

[0067] Fast turn-on reduces the voltage drop across the load during supply switching. If the input supply fails or is shorted, fast turn-off minimizes reverse current.

[0068] The controller can be powered from a 2.9V to 18V supply. When low, an external power supply is required. During undervoltage or overvoltage conditions, the power path is disabled. The controller also features an open MOSFET detection circuit that indicates if the voltage drop across the pass MOSFET is too large in the on state.

[0069] The clock chip uses Ningbo Aola Au5411 clock buffer. Au5411 has 10 LVPECL, CML, HCSL, LVDS and LVCMOS level clock outputs, which fully meet the needs of blade use.

[0070] The following table lists the main clock sources required in the general control module. The clock sources in the table can be divided into two different types of clock sources. The first type is the CORE clock and the DDR clock. The clocks they output are mainly used for processor core logic operations and DDR work.

[0071] The second category is the clocks of high-speed interfaces such as PCIE and SGMII. The clocks they output are mainly to provide low-frequency reference clocks for various high-speed interface blades.

[0072] Table 1 High-performance intensive general control module

[0073]

[0074] The clock signal is crucial to the general control module, so most of the clocks required on the chip use differential clock inputs to obtain clock signals with stronger noise resistance and higher signal integrity.

[0075] The reference of Tengyun S2500 / 64 core mainly includes 50M reference clock and 33M LPC clock. The 25MHz clock is the reference clock of Gigabit Ethernet PHY, which is realized by two 25MHz crystal oscillators. The PCIE channel related clock is realized by clock buffer, which can ensure the homology of PCIE reference clock. A 100MHz differential clock source is input to the clock buffer. The clock buffer chip uses Aola AU5411, and then generates PCIE reference clock and distributes it to various PCIE devices. AU5411 supports 4 clock inputs and 10 clock outputs.

[0076] The PCIE clock topology of this module is as follows Figure 6 shown.

[0077] The following table lists the timing requirements of the reset signal for each device and the actual situation of the device.

[0078] Table 2 Time requirements of reset signals for each device

[0079]

[0080] The reset topology diagram of this module is as follows Figure 7 shown.

[0081] System reset can be triggered in two ways, one is the whole machine reset signal, and the other is the CPLD logic soft reset; when the BMC receives any of the reset triggers, it will send the PWR_BTN# signal to the CPLD. After the CPLD receives the PWR_BTN# signal, it sends a reset signal to the CPU. After the CPU internal reset is completed, it will reply to the CPLD with a Reset# signal. Finally, the CPLD is triggered by this signal to reset all peripheral devices. PCIE device reset is also performed by CPLD acquisition system reset, and the reset duration and timing are controllable.

[0082] The module is based on the domestically produced Tengyun S2500 / 64 core processor. The blade is provided with 12V and 3.3V power through the backplane from the chassis power blade, which is input into the blade from the P0 port of the blade VPX connector and is close to the voltage regulator to ensure clean power supply.

[0083] The requirements for power-on sequence of Tengyun S2500 / 64 core processor are as follows: Figure 8 shown.

[0084] Among them, PWR_BTN_EN is the power-on signal, which is valid at low level; ATX_EN is the power-on signal, which is valid at low level; RESET_N is the hot reset signal, which is valid at low level; POR_N is the power-on reset signal, which is valid at low level; PCIE_SLOT_RST_N is the reset signal of all bus and interface standard PCIE device ends.

[0085] In addition to the key Feiteng processor core unit, the general control module also includes a variety of peripheral interface chips such as graphics cards, IO expansion chips, Ethernet, etc., which require multiple voltage levels. The overall power-on timing of the general control module is shown in the figure below. After each power supply is powered on in sequence and the processor is reset, each interface chip is reset to complete the initialization.

[0086] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. An S2500 high-performance intensive universal control module, characterized in that: It includes a main chip and a VPX connector. The main chip model is Tengyun S2500 / 64-core processor. A PCIE Switch controller and ASPEED BMC chip are provided between the main chip and the VPX connector.

2. The S2500 high performance intensive universal control module according to claim 1, characterized in that: The model of the PCIE switch controller is PEX8796, the main chip is connected to the PCIE switch controller via 1 PCIE X16, the model of the ASPEED BMC chip is AST2400, and the main chip is connected to the ASPEED BMC chip via 1 PCIEX1.

3. The S2500 high performance intensive universal control module according to claim 2, characterized in that: One PCIE X8 of the PCIE switch controller is connected to the VPX connector via a 10GbE network control chip, so as to expand two 10GBase-KR Ethernet interfaces; one PCIE X8 is connected to another 10GbE network control chip and the VPX connector, so as to expand two 10G XAUI Ethernet interfaces; There are also 3 PCIE X8 signals connected to the VPX connector, which can be expanded through the rear plug-in board. These 3 PCIEX8 signals can be split into 2 PCIE X4 signals; 1 PCIE X4 signal is used to connect to Netcom's WX1860AL2 chip to expand 2 1000GBase-X interfaces and then output to the VPX connector; 1 PCIEX1 signal is used to connect to the i210 chip to expand the network interface and lead out to the front panel; 1 PCIE X1 signal is used to connect to the 88SE9215 chip to expand the SATA interface and can connect to a SATA hard drive; 1 PCIEX1 signal is used to connect to the upd720201 chip to expand the front panel USB interface.

4. The S2500 high performance intensive universal control module according to claim 2, characterized in that: A CPLD chip is arranged between the ASPEEDBMC chip and the main chip.

5. The S2500 high performance intensive universal control module according to claim 4, characterized in that: The CPLD chip model is EF2L15BG256B.

6. The S2500 high performance intensive universal control module according to claim 3, characterized in that: The model of the 10GbE network control chip is Intel 85299.

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