MicroTCA framework case management module

Abstract

The utility model discloses a MicroTCA architecture chassis management module, which comprises a main chip, a network switching unit, a PCIE switching unit and an MCMC interface, the main chip, the network switching unit and the PCIE switching unit are all electrically connected with the MCMC interface, the model of the main chip is HC32F4A0SITB-LQFP176MCU, in the MicroTCA architecture chassis management module, the design of the MCMC is based on advanced hardware and software technologies, the design of the MCMC is simplified, and the design of the MCMC is simplified. And accurate control and management of each AMC module in the system are ensured. The system has strong data processing and communication capabilities, can perform high-speed data exchange and instruction transmission with the AMC module, and realizes real-time monitoring and dynamic adjustment of the system state. The MCMC supports a plurality of management protocols and standards, so that the MCMC can be seamlessly connected with other management systems or devices, and a cross-platform and cross-network management function is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, and in particular to a MicroTCA architecture chassis management module. Background Art

[0002] The technical background of MicroTCA mainly stems from the growing demand for bandwidth and signal processing capabilities in the telecommunications field in recent years. Traditional processor systems based on CPCI and VME buses face bottlenecks in bus bandwidth and cannot meet the system requirements of high throughput and low latency. In order to solve these problems, the PICMG Association proposed the MicroTCA architecture based on the ATCA architecture. The technical background of MicroTCA reflects the pursuit of high performance, high bandwidth, flexibility and reliability. It is compatible with the high performance and high bandwidth characteristics of ATCA, and combines the flexibility of AMC to create a highly integrated solution. This integration not only reduces costs, but also reduces system space and scale, making the use of AMC modules more convenient. The original intention of MicroTCA was to build a standardized hardware platform to support various types of AMC modules. These AMC modules can be flexibly configured according to application requirements to meet different performance and functional requirements. The hardware management structure of MicroTCA largely draws on the perfect AdvancedTCA management architecture, which makes MicroTCA more efficient and convenient in system management and maintenance.

[0003] Therefore, how to ensure accurate control and management of each AMC module in the system is a current research direction of MicroTCA. Utility Model Content

[0004] In order to overcome the above-mentioned deficiencies, the utility model provides a MicroTCA architecture chassis management module.

[0005] The utility model achieves the above-mentioned purpose through the following technical solutions:

[0006] A MicroTCA architecture chassis management module comprises a main chip, a network switching unit, a PCIE switching unit and an MCMC interface, wherein the main chip, the network switching unit and the PCIE switching unit are electrically connected to the MCMC interface;

[0007] The model of the main chip is HC32F4A0SITB-LQFP176MCU.

[0008] As a preferred embodiment, the main chip is connected to the MCMC interface through an IPBM-L bus, and IPMB-L is the main communication channel between the MCMC and the AMC module. It provides a standardized interface that allows the MCMC to monitor, configure and control the AMC module. Through IPMB-L, the MCMC can collect the status information of the AMC, send control commands, and perform operations such as fault detection and recovery. The IPMB-L bus adopts a serial communication mode, which has a high data transmission rate and stability, ensuring that the communication between the MCMC and the AMC is fast and reliable. And the MCMC is required to have 12 IPMBs. Since the HC32F4A0SITB only has 4 I2Cs, the remaining 10 I2Cs use GPIO to simulate the I2C protocol for communication, and the MCH of the MCMC part adopts a modular design, which reduces the design difficulty and maintenance cost. And a decoupled design form is adopted to reduce the design difficulty. There are also two I2Cs for IPMB-0, which mainly handle the acquisition of power supply status, the acquisition of fan status, and the establishment of communication with the power supply module, and the fan management module, that is, EMMC, for communication. Therefore, the use of Huada Semiconductor's MCU meets the communication requirements.

[0009] Preferably, the model of the network switching unit is CTC2118, and the network switching unit is electrically connected to the MCMC interface through the UART communication protocol. CTC2118 (TsingMa.AX) is a highly integrated switching chip that integrates switching, management and PHY, and is designed to meet the full access needs of the Internet of Everything era with a single chip. The chip forwarding capacity is 28Gbps, and the port form is 8GE+4xQSGMII / SGMII+4xSGMII, providing 100M and 1G port access capabilities. An 8-port Gigabit PHY is integrated inside the chip, and a Shengke 8-port or 4-port Gigabit PHY with optoelectronic multiplexing ports can be selected to meet L2 applications of 28 ports and below, and typically supports 24x1G electrical + 4x1G optical port forms. In addition, the chip integrates a RISC-V MCU with a main frequency of 125MHz, which supports supporting WEB management applications.

[0010] Preferably, the PCIE switching unit includes PEX_8796, which is electrically connected to the MCMC interface. PEX8796 is a 96-channel, 24-port PCIe Gen3 switching device developed using 40nm technology. PEX8796 provides multi-host PCI Express switching capabilities, enabling users to connect multiple hosts to their respective endpoints through scalable, high-bandwidth, non-blocking interconnects to connect to various applications, including servers, storage, communications and graphics platforms. In addition to the high channel / port count, the device also provides two NT ports and clock isolation capabilities. Due to its backward compatibility, designing with PCIe Gen3 switches in mixed (Gen1, Gen2 and Gen3) systems enables designers to ensure that their designs fully support Gen3 when migrating to the next generation of endpoints. PEX8796 is ideal for fan-out, aggregation and point-to-point traffic modes. Including PLX's proprietary visionPAK debug software, which allows, for example, observation of the internal receive eye after equalization and access to the device's internal debug registers, the PEX8796 is a 96-channel, 24-port PCIe Gen3 switch developed in 40nm technology. The PEX8796 provides multi-host PCI Express switching capabilities, enabling users to connect multiple hosts to their respective endpoints through a scalable, high-bandwidth, non-blocking interconnect to connect to a variety of applications, including servers, storage, communications, and graphics platforms. In addition to the high channel / port count, the device also provides two NT ports and clock isolation capabilities. Due to its backward compatibility, designing with PCIe Gen3 switches in mixed (Gen1, Gen2 and Gen3) systems enables designers to ensure that their designs fully support Gen3 when migrating to next-generation endpoints. The PEX8796 is ideal for fan-out, aggregation, and point-to-point traffic patterns. Includes PLX's proprietary visionPAK debug software. Fully meets MCMC's PCIe switching needs.

[0011] Preferably, the PEX_8796 is electrically connected to N10G-X2, and N10G-X2 is electrically connected to two SFP+ interfaces to support the network requirements of AMC. The N10G-X2 chip is a network controller chip that uses reconfigurable processor technology and high security. It has completely independent intellectual property rights and supports dual-port 40G, 2 / 4 / 8-port 10G interfaces and 8-port 1G network applications; supports 2PF, 128VF; supports RSS, up to 256 queues; supports checksum unloading and TSO; supports 5-tuple packet filtering and redirection; supports flow control mechanism; supports giant frame transmission; according to the different rates and number of ports, it can be divided into a variety of application forms. Therefore, this time, only two 10G interfaces are selected to meet the communication requirements and can be based on subsequent needs.

[0012] Preferably, the MCMC interface is electrically connected to a temperature detection unit and a voltage detection unit for receiving external temperature detection signals and voltage detection signals.

[0013] The beneficial effects of the utility model are as follows: in the MicroTCA architecture chassis management module, the design of MCMC is based on advanced hardware and software technologies, ensuring accurate control and management of each AMC module in the system. It has powerful data processing and communication capabilities, can exchange data and transmit instructions with the AMC module at high speed, and realize real-time monitoring and dynamic adjustment of the system status. MCMC supports multiple management protocols and standards, so that MCMC can be seamlessly connected with other management systems or devices to realize cross-platform and cross-network management functions. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The present invention will be described by way of examples with reference to the accompanying drawings, in which:

[0015] Figure 1 It is the MCMC system architecture diagram of the utility model.

[0016] Figure 2 The utility model discloses a chassis structure of the MicroTCA. DETAILED DESCRIPTION

[0017] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0018] The abbreviations and key terms appearing in this manual are defined as follows:

[0019] PCIe: Peripheral Component Interconnect Express, peripheral component interconnect standard

[0020] IPMI: Intelligent Platform Management Interface

[0021] ATCA: Advanced Telecom Computing Architecture

[0022] MicroTCA: Micro Telecom Computing Architecture

[0023] MCMC: MicroTCA Carrier Management Controller

[0024] AMC: Advanced Mezzanine Card

[0025] SRIO: Serial RapidIO, serial rapid input and output

[0026] GbE: Gigabit Ethernet

[0027] like Figure 1 and Figure 2 As shown, a MicroTCA architecture chassis management module includes a main chip, a network switching unit, a PCIE switching unit and an MCMC interface. The main chip, the network switching unit and the PCIE switching unit are electrically connected to the MCMC interface. The model of the main chip is HC32F4A0SITB-LQFP176MCU, which is an ARMv7-M architecture 32bit Cortex-M4 CPU, integrating FPU, MPU, DSP supporting SIMD instructions, full instruction tracking unit ETM, and CoreSight standard debugging unit. The maximum operating main frequency is 240MHz, and the computing performance of 300DMIPS or 825Coremarks can fully meet the computing management functions required by the current MCMC part. The chip also supports low-power operation, and peripherals can be turned off independently to meet the application scenarios that are sensitive to power consumption during operation.

[0028] Specifically, the main chip and the MCMC interface are connected through the IPBM-L bus, and IPMB-L is the main communication channel between the MCMC and the AMC module. It provides a standardized interface that allows the MCMC to monitor, configure and control the AMC module. Through IPMB-L, the MCMC can collect the status information of the AMC, send control commands, and perform operations such as fault detection and recovery. The IPMB-L bus adopts a serial communication method, which has a high data transmission rate and stability, ensuring that the communication between the MCMC and the AMC is fast and reliable. And the MCMC is required to have 12 IPMBs. Since the HC32F4A0SITB only has 4 I2Cs, the remaining 10 I2Cs use GPIO to simulate the I2C protocol for communication, and the MCH of the MCMC part adopts a modular design, which reduces the design difficulty and maintenance cost. And a decoupled design form is adopted to reduce the design difficulty. There are also two I2Cs for IPMB-0, which mainly handle the acquisition of power supply status, the acquisition of fan status, and the establishment of communication with the power supply module, and the fan management module, that is, EMMC, for communication. Therefore, the use of Huada Semiconductor's MCU meets the communication requirements.

[0029] Specifically, the model of the network switching unit is CTC2118, which is electrically connected to the MCMC interface through the UART communication protocol. CTC2118 (TsingMa.AX) is a highly integrated switching chip that integrates switching, management and PHY, and is designed to meet the full access needs of the Internet of Everything era with a single chip. The chip forwarding capacity is 28Gbps, and the port form is 8GE+4xQSGMII / SGMII+4xSGMII, providing 100M and 1G port access capabilities. An 8-port Gigabit PHY is integrated inside the chip, and a Gigabit PHY with 8 electrical ports or 4 optoelectronic multiplexing ports from Shengke can be selected to meet L2 applications of 28 ports and below, and typically supports 24x1G electrical + 4x1G optical port forms. In addition, the chip integrates a RISC-V MCU with a main frequency of 125MHz, which supports supporting WEB management applications.

[0030] Specifically, the PCIE switching unit includes PEX_8796, which is electrically connected to the MCMC interface. PEX8796 is a 96-channel, 24-port PCIe Gen3 switching device developed using 40nm technology. PEX8796 provides multi-host PCIExpress switching capabilities, enabling users to connect multiple hosts to their respective endpoints through scalable, high-bandwidth, non-blocking interconnects to connect to various applications, including servers, storage, communications, and graphics platforms. In addition to the high channel / port count, the device also provides two NT ports and clock isolation capabilities. Due to its backward compatibility, designing with PCIe Gen3 switches in mixed (Gen1, Gen2, and Gen3) systems enables designers to ensure that their designs fully support Gen3 when migrating to the next generation of endpoints. PEX8796 is ideal for fan-out, aggregation, and point-to-point traffic modes. Including PLX's proprietary visionPAK debug software, which allows, for example, observation of the internal receive eye after equalization and access to the device's internal debug registers, the PEX8796 is a 96-channel, 24-port PCIe Gen3 switch developed in 40nm technology. The PEX8796 provides multi-host PCI Express switching capabilities, enabling users to connect multiple hosts to their respective endpoints through a scalable, high-bandwidth, non-blocking interconnect to connect to a variety of applications, including servers, storage, communications, and graphics platforms. In addition to the high channel / port count, the device also provides two NT ports and clock isolation capabilities. Due to its backward compatibility, designing with PCIe Gen3 switches in mixed (Gen1, Gen2 and Gen3) systems enables designers to ensure that their designs fully support Gen3 when migrating to next-generation endpoints. The PEX8796 is ideal for fan-out, aggregation, and point-to-point traffic patterns. Includes PLX's proprietary visionPAK debug software. Fully meets MCMC's PCIe switching needs.

[0031] Specifically, the PEX_8796 is electrically connected to N10G-X2, and N10G-X2 is electrically connected to two SFP+ interfaces to support the network requirements of AMC. The N10G-X2 chip is a network controller chip that uses reconfigurable processor technology and high security. It has completely independent intellectual property rights and supports dual-port 40G, 2 / 4 / 8-port 10G interfaces and 8-port 1G network applications; supports 2PF, 128VF; supports RSS, up to 256 queues; supports checksum unloading and TSO; supports 5-tuple packet filtering and redirection; supports flow control mechanism; supports giant frame transmission; according to the different rates and number of ports, it can be divided into multiple application forms. Therefore, this time, only two 10G interfaces are selected to meet the communication requirements and can be based on subsequent needs.

[0032] Specifically, the MCMC interface is electrically connected to a temperature detection unit and a voltage detection unit, and is used for receiving external temperature detection signals and voltage detection signals.

[0033] The MicroTCA architecture chassis management module reduces on-site maintenance costs and maintenance time. Through the decoupling design method, it reduces the difficulty of design and maintenance costs. It has high reliability. The design follows the standards of the MicroTCA architecture, uses highly reliable components and good manufacturing processes to ensure that the module has a long service life. In actual applications, the MCMC can operate stably with a low failure rate, thereby improving the reliability of the entire system. In addition, this module also has strong management capabilities and high-speed data transmission capabilities, which can meet various complex application scenarios. The actual design is designed in accordance with the latest standard MicroTCA.4, and the software also complies with this protocol. The efficient management algorithm makes the chassis management stable and reliable. It supports a variety of management functions, with remote monitoring, configuration and other functions, so that system administrators can easily manage and maintain the chassis of the entire architecture. This design not only reduces the cost of system maintenance, but also improves the availability and flexibility of the entire MCMC. Thus, it meets the design requirements of the MicroTCA architecture.

[0034] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A MicroTCA chassis management module, characterized in that: It includes a main chip, a network switching unit, a PCIE switching unit and a MCMC interface, and the main chip, the network switching unit and the PCIE switching unit are electrically connected to the MCMC interface; The model of the main chip is HC32F4A0SITB-LQFP176MCU.

2. The MicroTCA chassis management module according to claim 1, characterized in that: The main chip and the MCMC interface are connected via an IPBM-L bus.

3. The MicroTCA chassis management module according to claim 1, characterized in that: The model of the network switching unit is CTC2118, and the network switching unit is electrically connected to the MCMC interface via the UART communication protocol.

4. The MicroTCA chassis management module according to claim 1, characterized in that: The PCIE switching unit includes PEX_8796, and PEX_8796 is electrically connected to the MCMC interface.

5. The MicroTCA chassis management module according to claim 4, characterized in that: The PEX_8796 is electrically connected to N10G-X2, and N10G-X2 is electrically connected to two SFP+ interfaces.

6. The MicroTCA chassis management module according to claim 1, characterized in that: The MCMC interface is electrically connected to a temperature detection unit and a voltage detection unit.

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