Display device

Abstract

The present disclosure relates to a display device, and more particularly, to a display device capable of reducing a dead zone area while improving current driving capabilities of a pull-up transistor and a pull-down transistor. According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; a plurality of pixels arranged in the display area of the substrate; and a gate driving circuit disposed in the non-display area of the substrate and connected to the transistor of each of the plurality of pixels. The gate driving circuit includes a pull-up transistor and a pull-down transistor. At least one of the pull-up transistor and the pull-down transistor includes a plurality of sub-transistors including a plurality of gate electrodes, and wherein the plurality of sub-transistors share at least one of the plurality of gate electrodes.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0053474 filed in the Korean Intellectual Property Office on April 24, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a display device, and more particularly, to a display device capable of reducing a dead zone area while improving current driving capabilities of a pull-up transistor and a pull-down transistor. Background Art

[0004] Thin film transistors (TFTs) have been used in various fields. In particular, thin film transistors have been used as switching and driving elements in flat panel display devices such as liquid crystal displays (LCDs), organic light emitting diode (OLED) displays, and electrophoretic displays. Utility Model Content

[0005] Aspects of the present disclosure may provide a display device in which current driving capabilities of a pull-up transistor and a pull-down transistor are improved and the size of a dead zone is reduced.

[0006] The objects of the present disclosure are not limited to the above-mentioned objects, and additional objects of the present disclosure not mentioned herein will be clearly understood by those skilled in the art through the following description of the present disclosure.

[0007] According to an embodiment of the present disclosure, a display device includes: a substrate having a display area and a non-display area; a plurality of pixels arranged in the display area of ​​the substrate; and a gate driving circuit arranged in the non-display area of ​​the substrate and connected to a transistor of each of the plurality of pixels, wherein the gate driving circuit includes a pull-up transistor and a pull-down transistor, wherein at least one of the pull-up transistor and the pull-down transistor includes a plurality of sub-transistors including a plurality of gate electrodes, and wherein the plurality of sub-transistors share at least one of the plurality of gate electrodes.

[0008] In an embodiment, the plurality of gate electrodes include: a first gate electrode disposed on the substrate; a second gate electrode disposed on the first gate electrode; and a third gate electrode disposed on the second gate electrode.

[0009] In an embodiment, the plurality of sub-transistors share the second gate electrode.

[0010] In an embodiment, the plurality of sub-transistors include a first sub-transistor and a second sub-transistor connected in parallel.

[0011] In an embodiment, the first sub-transistor includes: a first gate electrode; a second gate electrode; and a first active layer disposed between the first gate electrode and the second gate electrode.

[0012] In an embodiment, the second sub-transistor includes: a second gate electrode; a third gate electrode; and a second active layer disposed between the second gate electrode and the third gate electrode.

[0013] In an embodiment, a portion of the first active layer corresponding to the first drain electrode of the first sub-transistor and a portion of the second active layer corresponding to the second drain electrode of the second sub-transistor are connected to each other.

[0014] In an embodiment, the first drain electrode and the second drain electrode are connected to each other through a contact hole of the insulating layer.

[0015] In an embodiment, a portion of the first active layer corresponding to the first source electrode of the first sub-transistor and a portion of the second active layer corresponding to the second source electrode of the second sub-transistor are connected to each other.

[0016] In an embodiment, the first source electrode and the second source electrode are connected to each other through a contact hole of the insulating layer.

[0017] In an embodiment, the first gate electrode, the second gate electrode, and the third gate electrode are connected to each other through a contact hole of the insulating layer.

[0018] In an embodiment, the first active layer and the second active layer include the same semiconductor material.

[0019] In an embodiment, the first active layer and the second active layer each include an oxide semiconductor material.

[0020] In an embodiment, the oxide semiconductor material includes an oxide semiconductor including indium gallium zinc oxide (IGZO) or indium gallium zinc tin oxide (IGZTO).

[0021] In an embodiment, the first gate electrode, the second gate electrode, and the third gate electrode overlap each other.

[0022] In an embodiment, the first active layer and the second active layer overlap each other.

[0023] According to the display device disclosed in the present invention, since the pull-up transistor and the pull-down transistor include a plurality of sub-transistors connected in parallel, the current driving capability of the pull-up transistor and the pull-down transistor can be improved. In addition, since the plurality of sub-transistors share at least one gate electrode, the size of the pull-up transistor and the pull-down transistor can be reduced. Therefore, the size of the gate drive circuit including the pull-up transistor and the pull-down transistor can be reduced, and therefore, the area of ​​the non-display region (e.g., dead zone) in which the gate drive circuit is arranged can be reduced.

[0024] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects and features of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the attached drawings.

[0026] Figure 1 is a perspective view of a display device according to an embodiment.

[0027] Figure 2 is a plan view of a display device according to an embodiment.

[0028] Figure 3 is a block diagram of a display device according to one embodiment.

[0029] Figure 4 is a circuit diagram of a pixel of a display device according to one embodiment.

[0030] Figure 5 yes Figure 3 Block diagram of the first sub-gate driver.

[0031] Figure 6 yes Figure 5 A circuit diagram of an n-th stage implementation of FIG.

[0032] Figure 7 It is a graphic Figure 6 A plan view of the layout of the ninth transistor.

[0033] Figure 8 is along Figure 7 A cross-sectional view taken along line II'.

[0034] Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II'.

[0035] Fig.10 is included in Figure 3 A circuit diagram of one stage in an emission control driver. DETAILED DESCRIPTION

[0036] The advantages and features of the present disclosure and methods of achieving the same will become apparent with reference to the exemplary embodiments described in detail below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the exemplary embodiments described below, but can be implemented in various different forms, which are described to complete the present disclosure and allow those of ordinary skill in the art to which the present disclosure belongs to fully appreciate the scope of the present disclosure and the scope of the subject matter defined in the claims.

[0037] In the present disclosure, an element or layer referred to as being "on" another element or layer includes both the case where the element or layer is directly on another element or layer and the case where the element or layer is on another element or layer with one or more other elements or layers between them. Throughout the specification, the same reference numerals indicate the same parts. The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings are examples and may be simplified or exaggerated to enhance understanding, and the embodiments of the present disclosure are not limited to those illustrated in the drawings.

[0038] It will be understood that although the terms "first", "second", etc. may be used to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. Therefore, without departing from the teachings of the present disclosure, the first component discussed below may be referred to as the second component.

[0039] Each feature of the various exemplary embodiments of the present disclosure may be partially or completely coupled or combined with each other, and may be technically capable of various interlocks and drives, and each exemplary embodiment may be implemented independently of each other or may be implemented together in an associated relationship.

[0040] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

[0041] Figure 1 1 is a perspective view of a display device 10 according to an embodiment. As used herein, the terms "upper", "top" and "top surface" refer to an upward direction relative to a display panel (ie, Figure 1 The terms "lower", "bottom", and "bottom surface" as used herein refer to the downward direction relative to the display panel (i.e., the direction opposite to the third direction DR3). In addition, "left", "right", "upper", and "lower" refer to directions when the display device 10 is viewed from above. For example, "left" refers to the opposite direction of the first direction DR1, "right" refers to the first direction DR1, "upper" refers to the second direction DR2, and "lower" refers to the opposite direction of the second direction DR2.

[0042] The display device 10 displays an image on the screen through the display area DA, and can be adopted as all or part of various devices. Examples of applications of the display device 10 may include, but are not limited to, smartphones, mobile phones, tablet personal computers, personal digital assistants (PDAs), portable multimedia players (PMPs), televisions, game consoles, wristwatch-type electronic devices, head-mounted displays, displays of personal computers, laptop computers, car navigation systems, dashboard displays of cars, digital cameras, video cameras, external billboards, electronic billboards, various medical devices, various inspection devices, various home appliances such as refrigerators and washing machines, Internet of Things devices, etc.

[0043] In addition, the display device 10 may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro light-emitting diode. Hereinafter, an organic light-emitting display device will be described as an example of the display device 10, and unless there is a need for special distinction, the organic light-emitting display device applied to the embodiment will be simply referred to as the display device 10. However, the embodiment is not limited to the organic light-emitting display device, and other display devices described above or known in the art may be applied within the same scope of the technical spirit.

[0044] The display device 10 may include a display panel 100 , a display driving circuit 200 , and a circuit board 300 .

[0045] In a plan view, the display panel 100 may be formed in a rectangular shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. The corners where the short sides in the first direction DR1 and the long sides in the second direction DR2 intersect may be rounded to have a curvature or may be a right angle. The planar shape of the display panel 100 is not limited to a rectangular shape, and the display panel 100 may be formed in another polygonal shape, a circular shape, or an elliptical shape, for example. The display panel 100 may be formed flat, but the embodiment is not limited thereto. For example, the display panel 100 may include a bent portion at the left and right edges and having a constant curvature or a varying curvature. Alternatively, the display panel 100 may be flexible so that the display panel 1000 can be bent, curved, folded, or curled.

[0046] The display panel 100 may be divided into a display area DA displaying an image or a video and a non-display area NDA disposed around the display area DA in a plan view according to whether display is performed.

[0047] The display area DA may include a plurality of pixels. A pixel is a basic unit for displaying a picture. A pixel may include, but is not limited to, a red pixel, a green pixel, and a blue pixel. A pixel may also include a white pixel. In a plan view, a plurality of pixels may be arranged alternately. For example, the pixels may be arranged in a matrix or an array, but the present disclosure is not limited thereto.

[0048] The non-display area NDA may be arranged around the display area DA. A black matrix may be arranged in the non-display area NDA to prevent light emitted from adjacent pixels from leaking through the non-display area NDA. In addition, the non-display area NDA may include circuits such as a driver circuit for controlling or driving a plurality of pixels and a plurality of lines for applying an electrical signal to each of the plurality of pixels. Figure 2 and Figure 3 The components in the non-display area NDA are further described.

[0049] like Figure 1 As shown in the figure, the non-display area NDA may surround the display area DA. That is, the display area DA may be formed in an overall quadrilateral shape, and the non-display area NDA may be arranged around four sides of the display area DA. However, the present disclosure is not limited thereto, and the display area DA may be partially surrounded by the non-display area NDA. For example, the non-display area NDA may be arranged only around three sides of the display area DA. In this case, the other side of the display area DA may form an edge of the display device 10.

[0050] The display driving circuit 200 may be formed as an integrated circuit (IC) and attached to the display panel 100 by a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but the present disclosure is not limited thereto. For example, the display driving circuit 200 may be attached to the circuit board 300.

[0051] The circuit board 300 may be attached to the pad DP using an anisotropic conductive film (see Figure 2 ) on. Therefore, the lead of the circuit board 300 can be electrically connected to the pad DP. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on a film.

[0052] Figure 2 is a plan view of a display device 10 according to one embodiment. Figure 3 is a block diagram of a display device 10 according to one embodiment.

[0053] Reference Figure 2 and Figure 3, pixels PX, gate lines GL connected to the pixels PX, emission lines EML, data lines DL, and driving voltage lines VDL may be arranged on the display panel 100. The gate lines GL and the emission lines EML may extend in a first direction DR1, and the data lines DL and the driving voltage lines VDL may extend in a second direction DR2 crossing the first direction DR1. The driving voltage lines VDL may extend in the second direction DR2 in the display area DA. The driving voltage lines VDL may include a plurality of lines extending in the second direction DR2 and connected to each other in the non-display area NDA.

[0054] Each of the plurality of pixels PX may be connected to at least one of the plurality of gate lines GL, at least one of the plurality of data lines DL, at least one of the plurality of emission lines EML, and a driving voltage line VDL. Figure 2 An example is illustrated in which each of the plurality of pixels PX is connected to three gate lines GL, one data line DL, one emission line EML, and a driving voltage line VDL, but the embodiment is not limited thereto. For example, each of the plurality of pixels PX may be connected to two or less gate lines GL instead of three gate lines GL, or may be connected to four or more gate lines GL.

[0055] Each of the plurality of pixels PX may include a driving transistor, at least one switching transistor, a light emitting element, and a capacitor. The driving transistor and the at least one switching transistor may be thin film transistors. The at least one switching transistor may be turned on or off according to a gate signal applied from a gate line to act as a switching element. For example, when a transistor arranged between a data line and a gate electrode of a driving transistor is turned on by a gate signal, a data voltage of the data line may be applied to the gate electrode of the driving transistor. The light emitting element in each pixel PX may be an organic light emitting diode including a first electrode, an organic light emitting layer, and a second electrode. The light emitting element may emit light according to a driving current of the driving transistor. A capacitor may be used to keep the data voltage applied to the gate electrode of the driving transistor constant.

[0056] like Figure 3 As shown in FIG. 2 , the display driving circuit 200 may include a timing controller 210 , a data driver 220 , and a plurality of voltage lines.

[0057] The timing controller 210 may receive the digital video data DDATA and the timing signal from the circuit board 300. The timing controller 210 may generate the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3 for controlling the operation timing of each of the first gate driver 410, the second gate driver 420, and the third gate driver 430 according to the timing signal, may generate the emission control signal ECS for controlling the operation timing of the emission control driver 450, and may generate the data control signal DCS for controlling the operation timing of the data driver 220. For example, the timing controller 210 may generate the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3 according to the timing signal. In addition, the timing controller 210 may output the first gate control signal GCS1 to the first gate driver 410, the second gate control signal GCS2 to the second gate driver 420, and the third gate control signal GCS3 to the third gate driver 430.

[0058] The timing controller 210 may output first, second, and third gate control signals GCS1, GCS2, and GCS3 to the first, second, and third gate drivers 410, 420, and 430, respectively, through the gate control lines GCL, and output the emission control signal ECS to the emission control driver 450. The timing controller 210 may output the data signal DATA and the data control signal DCS to the data driver 220.

[0059] The data driver 220 may convert the data signal DATA into an analog data voltage to output the analog data voltage to the data line DL through the fan-out line FL.

[0060] Each of the plurality of voltage lines may be supplied with a voltage from a power supply unit. The plurality of voltage lines may include a driving voltage line VDL for applying a driving voltage ELVDD and a common voltage line for applying a common voltage. The driving voltage ELVDD may be a high potential voltage for driving an organic light emitting diode or other light emitting element in a pixel PX, and the common voltage may be a low potential voltage for driving an organic light emitting diode or other light emitting element in a pixel PX. For example, the driving voltage ELVDD may have a higher potential than the common voltage.

[0061] The non-display area NDA may include a gate driving circuit 400 for applying a gate signal to the gate line GL, a fan-out line FL between the data line DL and the display driving circuit 200, and a pad DP connected to the display driving circuit 200. The display driving circuit 200 and the pad DP may be arranged adjacent to an edge of a lower side of the display panel 100.

[0062] The gate driving circuit 400 may be electrically connected to the display driving circuit 200 through the gate control lines GCL. The gate driving circuit 400 may receive first, second, and third gate control signals GCS1, GCS2, and GCS3 and an emission control signal ECS from the display driving circuit 200 through the gate control lines GCL.

[0063] The gate driving circuit 400 may generate gate signals according to the first gate control signal GCS1, the second gate control signal GCS2, and the third gate control signal GCS3 and sequentially output the gate signals to the gate lines GL. In addition, the gate driving circuit 400 may generate emission signals according to the emission control signal ECS and sequentially output the emission signals to the emission lines EML.

[0064] The gate drive circuit 400 may include a plurality of thin film transistors. The gate drive circuit 400 may be formed on the same layer or layers as the thin film transistors in which the pixels PX are formed or may be formed using the same layer or layers as the thin film transistors in which the pixels PX are formed. The gate drive circuit 400 may be arranged in the non-display area NDA on both sides (i.e., the left and right sides) of the display area DA. This structure may advantageously reduce the length of the non-display area NDA on each of the left and right sides of the display area DA in the first direction DR1. However, the embodiment is not limited thereto. For example, the gate drive circuit 400 may be arranged on the left or right side of the display area DA.

[0065] The gate driving circuit 400 may include a first gate driver 410 , a second gate driver 420 , a third gate driver 430 , and an emission control driver 450 .

[0066] Figure 2 and Figure 3 An example is illustrated in which the first gate driver 410 includes a first sub-gate driver 411 disposed on one side of the non-display area NDA (e.g., on the left side of the non-display area NDA) and a second sub-gate driver 412 disposed on the other side of the non-display area NDA (e.g., on the right side of the non-display area NDA), and each of the first sub-gate driver 411 and the second sub-gate driver 412 applies a gate signal. The present disclosure is not limited thereto. Alternatively, the gate driving circuit 400 may include one first gate driver 410 that may be disposed on one side or the other side of the non-display area NDA.

[0067] The second gate driver 420 and the third gate driver 430 may be arranged on different sides of the non-display area NDA. Figure 3As shown in the figure, when the second gate driver 420 is arranged on one side of the non-display area NDA, the third gate driver 430 may be arranged on the other side of the non-display area NDA, and conversely, when the second gate driver 420 is arranged on the other side of the non-display area NDA, the third gate driver 430 may be arranged on one side of the non-display area NDA.

[0068] At least two voltage lines among a plurality of voltage lines for applying voltage to the gate lines GL may be connected to each of the first gate driver 410, the second gate driver 420, and the third gate driver 430. One or more voltage lines for applying voltage to the emission lines EML may be connected to the emission control driver 450.

[0069] Figure 4 is a circuit diagram of a pixel PX of a display device 10 according to an embodiment.

[0070] Reference Figure 4 , the pixel PX may include a light emitting element LEL (e.g., an organic light emitting diode) as a display element and a pixel circuit PC connected to the light emitting element LEL. The pixel circuit PC may include a first transistor T1 to a fifth transistor T5 and a first capacitor C1 and a second capacitor C2. The first transistor T1 may be a driving transistor in which the magnitude of the source-drain current is determined according to the gate-source voltage, and each of the second transistor T2 to the fifth transistor T5 may be a switching transistor that is turned on / off according to the gate-source voltage (substantially the gate voltage). The first transistor T1 to the fifth transistor T5 may be implemented as a thin film transistor. Depending on the type of transistor (p-type or n-type) and / or operating conditions, the first electrode of each of the first transistor T1 to the fifth transistor T5 may be a source electrode or a drain electrode, and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a source electrode, the second electrode may be a drain electrode.

[0071] The pixel PX may be connected to a first gate line GWL transmitting a first gate signal GW, a second gate line GIL transmitting a second gate signal GI, a third gate line GRL transmitting a third gate signal GR, an emission line EML transmitting an emission signal EM, and a data line DL transmitting an analog data voltage.

[0072] The first gate driver 410 (e.g., the first sub-gate driver 411 and the second sub-gate driver 412) may apply the first gate signal GW to the first gate line GWL. The second gate driver 420 may apply the second gate signal GI to the second gate line GIL. The third gate driver 430 may apply the third gate signal GR to the third gate line GRL. The emission control driver 450 may apply the emission signal EM to the emission line EML.

[0073] The driving voltage line VDL may transmit the driving voltage ELVDD to the fifth transistor T5. The initialization voltage line VIL may transmit the initialization voltage VINT to the fourth transistor T4. The reference voltage line VRL may transmit the reference voltage VREF to the first electrode of the third transistor T3. Meanwhile, according to the pixel structure, the initialization voltage line VIL may include a plurality of initialization voltage lines VIL (e.g., a first initialization voltage line and a second initialization voltage line transmitting initialization voltages of different magnitudes).

[0074] The plurality of first transistors T1 to the fifth transistor T5 may include an oxide semiconductor material. Since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large despite the long driving time. That is, in the case of an oxide semiconductor, since the color change of the image caused by the voltage drop is not large even during low-frequency driving, low-frequency driving is possible. Therefore, a display device 10 that prevents the generation of leakage current and has reduced power consumption can be realized by including a plurality of first transistors T1 to the fifth transistor T5 of an oxide semiconductor material. In addition, in the case of using an oxide semiconductor transistor, it is not necessary to form a low-temperature polycrystalline silicon (LTPS) semiconductor transistor by a crystallization process of excimer laser annealing (ELA), and therefore the manufacturing cost of the display panel 100 can be reduced, so as to facilitate the realization of a large-area display device 10.

[0075] The oxide semiconductor is sensitive to light, so that fluctuations in the amount of current may occur due to light from the outside. Therefore, it may be considered to position a metal layer below the oxide semiconductor to absorb or reflect light from the outside. The metal layer positioned below the oxide semiconductor of each of the first transistor T1 to the fifth transistor T5 may be used as a lower gate electrode (e.g., an opposing gate electrode). That is, the first transistor T1 to the fifth transistor T5 may be a dual-gate transistor having two gate electrodes (e.g., a first gate electrode and a second gate electrode, or a gate electrode and an opposing gate electrode).

[0076] The first transistor T1 has a first gate electrode connected to the first node N1 (or gate node), a second gate electrode GE2 connected to the third node N3, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. The second gate electrode GE2 of the first transistor T1 can be connected to the second electrode of the first transistor T1 to be controlled by the voltage applied to the second electrode of the first transistor T1, which can improve the output saturation characteristics of the first transistor T1. The first electrode of the first transistor T1 can be connected to the driving voltage line VDL via the fifth transistor T5, and the second electrode of the first transistor T1 can be connected to the pixel electrode (e.g., anode electrode) of the light emitting element LEL. The first transistor T1 can be used as a driving transistor, and can control the size (e.g., current amount) of the driving current Id flowing to the light emitting element LEL by receiving the data signal DATA according to the switching operation of the second transistor T2.

[0077] The second transistor T2 (e.g., a data writing transistor) includes a gate electrode connected to the first gate line GWL, a first electrode connected to the data line DL, and a second electrode connected to the first node N1 (or the first gate electrode of the first transistor T1). The second transistor T2 can be turned on according to the first gate signal GW transmitted to the first gate line GWL to electrically connect the data line DL to the first node N1, and can transmit the data signal DATA from the data line DL to the first node N1.

[0078] The third transistor T3 (e.g., the first initialization transistor) includes a gate electrode connected to the third gate line GRL, a first electrode connected to the reference voltage line VRL, and a second electrode connected to the first node N1 (or the first gate electrode of the first transistor T1). The third transistor T3 can be turned on or off according to the third gate signal GR transmitted to the third gate line GRL, and transmits the reference voltage VREF from the reference voltage line VRL to the first node N1 when turned on.

[0079] The fourth transistor T4 (e.g., the second initialization transistor) includes a gate electrode connected to the second gate line GIL, a first electrode connected to the third node N3 (or the second electrode of the first transistor T1), and a second electrode connected to the initialization voltage line VIL. The fourth transistor T4 can be turned on or off according to the second gate signal GI transmitted to the second gate line GIL, and transmits the initialization voltage VINT from the initialization voltage line VIL to the third node N3 when turned on.

[0080] The fifth transistor T5 (e.g., a light emitting transistor) includes a gate electrode connected to the emission line EML, a first electrode connected to the driving voltage line VDL, and a second electrode connected to the second node (or the first electrode of the first transistor T1). The fifth transistor T5 can be turned on or off according to the emission signal EM transmitted to the emission line EML.

[0081] The first capacitor C1 may be connected between the first node N1 and the third node N3. The first electrode of the first capacitor C1 may be connected to the first gate electrode of the first transistor T1, and the second electrode of the first capacitor C1 may be connected to the second gate electrode GE2 and the second electrode of the first transistor T1, the first electrode of the fourth transistor T4, and the pixel electrode (e.g., the anode electrode) of the light emitting element LEL. The first capacitor C1 may be a storage capacitor and may store a voltage corresponding to the threshold voltage of the first transistor T1 and the data signal.

[0082] The second capacitor C2 may be connected between the third node N3 and the driving voltage line VDL. The first electrode of the second capacitor C2 may be connected to the driving voltage line VDL, and the second electrode of the second capacitor C2 may be connected to the second gate electrode GE2 and the second electrode of the first transistor T1, the second electrode of the first capacitor C1, the first electrode of the fourth transistor T4, and the pixel electrode of the light emitting element LEL. The capacitance of the first capacitor C1 may be greater than the capacitance of the second capacitor C2.

[0083] The light emitting element LEL may include a pixel electrode (e.g., an anode electrode) and an opposite electrode (e.g., a cathode electrode) facing the pixel electrode, and a common voltage ELVSS may be applied to the opposite electrode. The opposite electrode may be connected to a common voltage line VSL that transmits the common voltage ELVSS. The opposite electrode may be a common electrode commonly shared by a plurality of pixels PX.

[0084] Figure 5 yes Figure 3 4 is a block diagram of the first sub-gate driver 411.

[0085] like Figure 5 As shown in , the first sub-gate driver 411 may include a plurality of stages.

[0086] Each of the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1 may receive a gate high voltage VGH, a first gate low voltage VGL1, a second gate low voltage VGL2, a first clock signal CLK1, and a second clock signal CLK2. To this end, each of the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1 may be connected to a gate high voltage line GHL, a first gate low voltage line GLL1, a second gate low voltage line GLL2, a first clock line CL1, and a second clock line CL2.

[0087] The gate high voltage line GHL may provide a gate high voltage VGH. The first gate low voltage line GLL1 may provide a first gate low voltage VGL1. The second gate low voltage line GLL2 may provide a second gate low voltage VGL2. The first clock line CL1 may provide a first clock signal CLK1. The second clock line CL2 may provide a second clock signal CLK2. The gate high voltage VGH may be greater than the first gate low voltage VGL1 and the second gate low voltage VGL2. The second gate low voltage VGL2 may be lower than the first gate low voltage VGL1. The first clock signal CLK1 and the second clock signal CLK2 may have different phases. In this case, the gate high voltage VGH, the high voltage of the first clock signal CLK1, and the high voltage of the second clock signal CLK2 may be greater than the threshold voltage of each transistor in the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1. In addition, the first gate low voltage VGL1, the second gate low voltage VGL2, the low voltage of the first clock signal CLK1, and the low voltage of the second clock signal CLK2 may be lower than the threshold voltage of each transistor in the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1.

[0088] Each of the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1 may output a corresponding first gate signal and a carry signal. For example, the nth stage ST_n may output an nth first gate signal GW_n and an nth carry signal CR_n. The nth first gate signal GW_n from the nth stage ST_n may be applied to the nth first gate line. The nth carry signal CR_n from the nth stage ST_n may be applied to at least one of the n-1th stage ST_n-1 and the n+1th stage ST_n+1.

[0089] Each of the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1 may be connected to at least one of the previous stage and the next stage. Figure 6 ) can be connected to the n-1th stage ST_n-1 and the (n+1)th stage ST_n+1.

[0090] Each of the n-1th stage ST_n-1, the nth stage ST_n, and the n+1th stage ST_n+1 can be set by a carry signal from a previous stage and reset by a carry signal from a subsequent stage. For example, the nth stage ST_n can be set by an n-1th carry signal CR_n-1 from the n-1th stage ST_n-1 and can be reset by an n+1th carry signal CR_n+1 from the n+1th stage. When set, the nth stage ST_n asserts or activates its nth first gate signal GW_n. When reset, the nth stage ST_n deactivates its nth first gate signal GW_n.

[0091] During one frame period, the first stage among the plurality of stages that first outputs the first gate signal may be set by a frame line mark signal instead of a carry signal. In addition, during one frame period, the first stage among the plurality of stages that last outputs or asserts the first gate signal may be reset by a carry signal from a separate dummy stage. The dummy stage may not output the first gate signal.

[0092] Figure 6 yes Figure 5 Circuit diagram of the nth stage ST_n.

[0093] like Figure 6 As shown in , the nth stage ST_n may include a node control unit NC, a carry output unit CRU, and a gate output unit GTU.

[0094] The nth stage ST_n may include a first transistor M1 to a tenth transistor M10, a first capacitor SC1, and a second capacitor SC2. For example, the node control unit NC may include a third transistor M3 to an eighth transistor M8. The carry output unit CRU may include a first transistor M1, a second transistor M2, and a first capacitor SC1. The gate output unit GTU may include a ninth transistor M9, a tenth transistor M10, and a second capacitor SC2. In this case, the ninth transistor M9 and the tenth transistor M10 may be output transistors that output the nth first gate signal GW_n. For example, the ninth transistor M9 may be a pull-up transistor, and the tenth transistor M10 may be a pull-down transistor.

[0095] A gate electrode of the first transistor M1 may be connected to the set node NQ, a drain electrode of the first transistor M1 may be connected to the second clock line CL2 , and a source electrode of the first transistor M1 may be connected to the carry output terminal COT_n of the nth stage ST_n.

[0096] A gate electrode of the second transistor M2 may be connected to the reset node NQB, a drain electrode of the second transistor M2 may be connected to the carry output terminal COT_n of the nth stage ST_n, and a source electrode of the second transistor M2 may be connected to the second gate low voltage line GLL2.

[0097] A gate electrode of the third transistor M3 may be connected to the set node NQ, a drain electrode of the third transistor M3 may be connected to the first clock line CL1 , and a source electrode of the third transistor M3 may be connected to the reset node NQB.

[0098] The gate electrode of the fourth transistor M4 may be connected to the start signal line or the gate output terminal GOT_n-1 of the n-1th stage ST_n-1, the drain electrode of the fourth transistor M4 may be connected to the gate high voltage line GHL, and the source electrode of the fourth transistor M4 may be connected to the set node NQ. In this case, for example, the above-mentioned frame line mark signal may be applied to the start signal line.

[0099] A gate electrode of the fifth transistor M5 may be connected to the first clock line CL1 , a drain electrode of the fifth transistor M5 may be connected to the gate high voltage line GHL, and a source electrode of the fifth transistor M5 may be connected to the reset node NQB.

[0100] A gate electrode of the sixth transistor M6 may be connected to the second clock line CL2 , a drain electrode of the sixth transistor M6 may be connected to the set node NQ, and a source electrode of the sixth transistor M6 may be connected to a source electrode of the seventh transistor M7 .

[0101] A gate electrode of the seventh transistor M7 may be connected to the reset node NQB, a drain electrode of the seventh transistor M7 may be connected to the carry output terminal COT_n of the nth stage ST_n, and a source electrode of the seventh transistor M7 may be connected to the source electrode of the sixth transistor M6.

[0102] The gate electrode of the eighth transistor M8 can be connected to the gate output terminal GOT_n+2 of the n+2th stage ST_n+2 (not shown), the drain electrode of the eighth transistor M8 can be connected to the set node NQ, and the source electrode of the eighth transistor M8 can be connected to the gate output terminal GOT_n of the nth stage ST_n.

[0103] The gate electrode of the ninth transistor M9 may be connected to the set node NQ, the drain electrode of the ninth transistor M9 may be connected to the second clock line CL2, and the source electrode of the ninth transistor M9 may be connected to the gate output terminal GOT_n of the nth stage ST_n. At the same time, the gate electrode of the ninth transistor M9 may include a first gate electrode GE1 (hereinafter referred to as the first lower gate electrode GE1), a second gate electrode GE2 (hereinafter referred to as the first common gate electrode GE2) and a third gate electrode GE3 (hereinafter referred to as the first upper gate electrode GE3). Here, the first lower gate electrode GE1, the first common gate electrode GE2 and the first upper gate electrode GE3 of the ninth transistor M9 may be connected to each other. The ninth transistor M9 may include, for example, a ninth-first sub-transistor M9-1 and a ninth-second sub-transistor M9-2. The ninth-first sub-transistor M9-1 may include a first lower gate electrode GE1, a first common gate electrode GE2, a first drain electrode DE1 and a first source electrode SE1 (see Figure 7). The first lower gate electrode GE1 and the first common gate electrode GE2 of the ninth-first sub-transistor M9-1 may be connected to the set node NQ, the first drain electrode DE1 of the ninth-first sub-transistor M9-1 may be connected to the second clock line CL2, and the first source electrode SE1 of the ninth-first sub-transistor M9-1 may be connected to the gate output terminal GOT_n of the n-th stage ST_n. The ninth-second sub-transistor M9-2 may include a first upper gate electrode GE3, a first common gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2 (see Figure 7 ). The first upper gate electrode GE3 and the first common gate electrode GE2 of the ninth-second sub-transistor M9-2 may be connected to the set node NQ, the second drain electrode DE2 of the ninth-second sub-transistor M9-2 may be connected to the second clock line CL2, and the second source electrode SE2 of the ninth-second sub-transistor M9-2 may be connected to the gate output terminal GOT_n of the n-th stage ST_n.

[0104] The gate electrode of the tenth transistor M10 may be connected to the reset node NQB, the drain electrode of the tenth transistor M10 may be connected to the gate output terminal GOT_n of the nth stage ST_n, and the source electrode of the tenth transistor M10 may be connected to the first gate low voltage line GLL1. Meanwhile, the gate electrode of the tenth transistor M10 may include a first gate electrode GE11 (hereinafter referred to as the second lower gate electrode GE11), a second gate electrode GE22 (hereinafter referred to as the second common gate electrode GE22), and a third gate electrode GE33 (hereinafter referred to as the second upper gate electrode GE33). Here, the second lower gate electrode GE11, the second common gate electrode GE22, and the second upper gate electrode GE33 of the tenth transistor M10 may be connected to each other. The tenth transistor M10 may include, for example, a tenth-first sub-transistor M10-1 and a tenth-second sub-transistor M10-2. The tenth-first sub-transistor M10-1 may include a second lower gate electrode GE11, a second common gate electrode GE22, a third drain electrode, and a third source electrode. The second lower gate electrode GE11 and the second common gate electrode GE22 of the tenth-first sub-transistor M10-1 may be connected to the reset node NQB, the third drain electrode of the tenth-first sub-transistor M10-1 may be connected to the gate output terminal GOT_n of the n-th stage ST_n, and the third source electrode of the tenth-first sub-transistor M10-1 may be connected to the first gate low voltage line GLL1. The tenth-second sub-transistor M10-2 may include a second upper gate electrode GE33, a second common gate electrode GE22, a fourth drain electrode, and a fourth source electrode. The second upper gate electrode GE33 and the second common gate electrode GE22 of the tenth-second sub-transistor M10-2 may be connected to the reset node NQB, the fourth drain electrode of the tenth-second sub-transistor M10-2 may be connected to the gate output terminal GOT_n of the n-th stage ST_n, and the fourth source electrode of the tenth-second sub-transistor M10-2 may be connected to the first gate low voltage line GLL1.

[0105] A first electrode of the first capacitor SC1 may be connected to the set node NQ, and a second electrode of the first capacitor SC1 may be connected to the carry output terminal COT_n of the n-th stage ST_n.

[0106] A first electrode of the second capacitor SC2 may be connected to the reset node NQB, and a second electrode of the second capacitor SC2 may be connected to the first gate low voltage line GLL1 .

[0107] According to the present disclosure, since the ninth transistor M9 as a pull-up transistor includes the ninth-first sub-transistor M9-1 and the ninth-second sub-transistor M9-2 connected in parallel, the current driving capability of the ninth transistor M9 can be improved. In addition, since the ninth-first sub-transistor M9-1 and the ninth-second sub-transistor M9-2 share the first common gate electrode GE2, the size of the ninth transistor M9 can be reduced. In other words, the pull-up transistor can be reduced in size while improving its current driving capability.

[0108] According to the present disclosure, since the tenth transistor M10 as a pull-down transistor includes the tenth-first sub-transistor M10-1 and the tenth-second sub-transistor M10-2 connected in parallel, the current driving capability of the tenth transistor M10 can be improved. In addition, since the tenth-first sub-transistor M10-1 and the tenth-second sub-transistor M10-2 share at least the second common gate electrode GE22, the size of the tenth transistor M10 can be reduced. In other words, the pull-down transistor can be reduced in size while improving its current driving capability.

[0109] In addition, according to the present disclosure, as the sizes of the ninth transistor M9 and the tenth transistor M10 are reduced, the size of the gate driving circuit 400 can be reduced. When the size of the gate driving circuit 400 is reduced, the area of ​​the non-display region (eg, dead zone) in which the gate driving circuit 400 is arranged can be reduced.

[0110] Figure 7 It is a graphic Figure 6 FIG. 1 is a plan view of the layout of the ninth transistor M9.

[0111] The ninth transistor M9 may include a channel region CH, a gate electrode GE, a drain electrode DE, and a source electrode SE. For example, a ninth-first sub-transistor M9-1 of the ninth transistor M9 may include a first channel region CH1, a first lower gate electrode GE1, a first common gate electrode GE2, a first drain electrode DE1, and a first source electrode SE1, and a ninth-second sub-transistor M9-2 of the ninth transistor M9 may include a second channel region CH2, a first upper gate electrode GE3, a first common gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2.

[0112] The first channel region CH1 of the ninth transistor M9 (or the ninth-first sub-transistor M9-1) may be arranged in an overlapping region between the first active layer ACT1 and at least one of the first lower gate electrode GE1 and the first common gate electrode GE2. For example, the region of the first active layer ACT1 overlapped by the first common gate electrode GE2 may be the above-mentioned first channel region CH1. In addition, the regions of the first active layer ACT1 arranged on both sides of the first channel region CH1 may be the first drain electrode DE1 and the first source electrode SE1, respectively.

[0113] The second channel region CH2 of the ninth transistor M9 (or the ninth-second sub-transistor M9-2) may be arranged in an overlapping region between the second active layer ACT2 and at least one of the first upper gate electrode GE3 and the first common gate electrode GE2. For example, the region of the second active layer ACT2 overlapped by the first upper gate electrode GE3 may be the above-mentioned second channel region CH2. In addition, the regions of the second active layer ACT2 arranged on both sides of the second channel region CH2 may be the second drain electrode DE2 and the second source electrode SE2, respectively.

[0114] The first lower gate electrode GE1 may overlap the first and second channel regions CH1 and CH2, the first common gate electrode GE2, and the first upper gate electrode GE3. The first lower gate electrode GE1 may block light from being introduced into the first and second channel regions CH1 and CH2 of the first and second active layers ACT1 and ACT2.

[0115] The first active layer ACT1 may be arranged on the first lower gate electrode GE1. The first active layer ACT1 may overlap the first lower gate electrode GE1. The first active layer ACT1 may include a first channel region CH1, a first drain electrode DE1, and a first source electrode SE1. The above-mentioned first channel region CH1 may be arranged in a portion of the first active layer ACT1 overlapping the first lower gate electrode GE1. The first active layer ACT1 may be an oxide semiconductor. For example, the first active layer ACT1 may include an oxide semiconductor including indium gallium zinc oxide (IGZO) or an oxide semiconductor including indium gallium zinc tin oxide (IGZTO).

[0116] The first common gate electrode GE2 may be disposed on the first active layer ACT1. The first common gate electrode GE2 may overlap the first active layer ACT1. The above-mentioned first channel region CH1 may be disposed in a portion of the first active layer ACT1 overlapping the first common gate electrode GE2.

[0117] The second active layer ACT2 may be arranged on the first common gate electrode GE2. The second active layer ACT2 may overlap the first common gate electrode GE2. The second active layer ACT2 may include a second channel region CH2, a second drain electrode DE2, and a second source electrode SE2. The above-mentioned second channel region CH2 may be arranged in a portion of the second active layer ACT2 that overlaps with the first common gate electrode GE2. The second active layer ACT2 may be connected to the first active layer ACT1 through a first contact hole CT1 and a sixth contact hole CT6 that penetrate the insulating layer. For example, the second drain electrode DE2 of the second active layer ACT2 may be connected to the first drain electrode DE1 of the first active layer ACT1 through the first contact hole CT1, and the second source electrode SE2 of the second active layer ACT2 may be connected to the first source electrode SE1 of the first active layer ACT1 through the sixth contact hole CT6. The second active layer ACT2 may be an oxide semiconductor. For example, the second active layer ACT2 may include an oxide semiconductor including indium gallium zinc oxide (IGZO) or an oxide semiconductor including indium gallium zinc tin oxide (IGZTO). In this case, the second active layer ACT2 and the first active layer ACT1 may include the same semiconductor material (e.g., the same oxide semiconductor material). For example, each of the first active layer ACT1 and the second active layer ACT2 may be an oxide semiconductor including indium gallium zinc oxide (IGZO). As another example, each of the first active layer ACT1 and the second active layer ACT2 may be an oxide semiconductor including indium gallium zinc tin oxide (IGZTO).

[0118] The first upper gate electrode GE3 may be arranged on the second active layer ACT2. The first upper gate electrode GE3 may overlap the second active layer ACT2. The above-mentioned second channel region CH2 may be arranged in a portion of the second active layer ACT2 overlapping with the first upper gate electrode GE3. The first upper gate electrode GE3 may be connected to the first common gate electrode GE2 through a third contact hole CT3 penetrating the insulating layer, and the first upper gate electrode GE3 may be connected to the first lower gate electrode GE1 through a fifth contact hole CT5 penetrating the insulating layer.

[0119] The first lower gate electrode GE1, the first active layer ACT1, the first common gate electrode GE2, the second active layer ACT2, and the first upper gate electrode GE3 described above may overlap with each other. For example, the first lower gate electrode GE1, the first active layer ACT1, the first common gate electrode GE2, the second active layer ACT2, and the first upper gate electrode GE3 may overlap with each other. Figure 7 The plan views overlap each other in a perpendicular third direction DR3.

[0120] The node connection electrode NCE may be disposed on the first upper gate electrode GE3. The node connection electrode NCE may be connected to the first upper gate electrode GE3 through a fourth contact hole CT4 penetrating the insulating layer. At the same time, the node connection electrode NCE may be connected to Figure 6 Therefore, the above-mentioned first lower gate electrode GE1, the first common gate electrode GE2, and the first upper gate electrode GE3 may be connected to the set node NQ through the node connection electrode NCE.

[0121] The clock connection electrode CCE and the output connection electrode OCE may be arranged on the node connection electrode NCE or in a conductive layer above a layer in which the node connection electrode NCE is formed. The clock connection electrode CCE may be connected to the second drain electrode DE2 through a second contact hole CT2 penetrating the insulating layer. At the same time, the clock connection electrode CCE may be connected to Figure 6 . Therefore, the first drain electrode DE1 and the second drain electrode DE2 described above can be connected to the second clock line CL2 through the clock connection electrode CCE. The output connection electrode OCE can be connected to the second source electrode SE2 through the seventh contact hole CT7 penetrating the insulating layer. At the same time, the output connection electrode OCE can be connected to Fig. 9 Therefore, the first source electrode SE1 and the second source electrode SE2 described above may be connected to the gate output terminal GOT_n of the n-th stage ST_n through the output connection electrode OCE.

[0122] Figure 8 is along Figure 7 A cross-sectional view taken along line II' of Fig. 9 is along Figure 7 A cross-sectional view taken along line II-II'.

[0123] like Figure 8 and Fig. 9 As shown in , the display device 10 may include a substrate SUB, a barrier layer BR, a buffer layer BF, a thin film transistor layer TFTL, a light emitting element layer EMTL, and an encapsulation layer ENC. The barrier layer BR, the buffer layer BF, the thin film transistor layer TFTL, the light emitting element layer EMTL, and the encapsulation layer ENC may be sequentially arranged on the substrate SUB along a third direction DR3.

[0124] The substrate SUB may be a rigid substrate or a flexible substrate capable of bending, folding or curling. The substrate SUB may be formed of an insulating material such as glass, quartz or a polymer resin. Examples of polymer materials may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CTA), cellulose acetate propionate (CAP) or a combination thereof. Alternatively, the substrate SUB may include a metal material.

[0125] The barrier layer BR may be disposed on the substrate SUB. The barrier layer BR may be a layer for protecting the transistors of the thin film transistor layer TFTL and the light emitting layer of the light emitting element layer EMTL from moisture penetrating through the substrate SUB which may be susceptible to moisture penetration. The barrier layer BR may be formed as a plurality of inorganic layers alternately stacked. For example, the barrier layer BR may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0126] The first lower gate electrode GE1 may be disposed on the barrier layer BR.

[0127] The buffer layer BF may be disposed on the first lower gate electrode GE1. The buffer layer BF may be disposed on the entire surface of the substrate SUB including the first lower gate electrode GE1. The buffer layer BF may be a layer for protecting the transistors of the thin film transistor layer TFTL and the light emitting layer of the light emitting element layer EMTL from moisture that penetrates through the substrate SUB that may be susceptible to moisture penetration. The buffer layer BF may be formed as a plurality of inorganic layers alternately stacked. For example, the buffer layer BF may be formed of a plurality of layers in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0128] The first active layer ACT1 may be disposed on the buffer layer BF. For example, the first active layer ACT1 may be disposed on the buffer layer BF so that the first channel region CH1 of the first active layer ACT1 overlaps the first lower gate electrode GE1 in the third direction DR3. For example, the first active layer ACT1 may be an oxide semiconductor. For example, the first active layer ACT1 may include an oxide semiconductor including indium gallium zinc oxide (IGZO) or an oxide semiconductor including indium gallium zinc tin oxide (IGZTO).

[0129] The first gate insulating layer GTI1 may be disposed on the first active layer ACT1. For example, the first gate insulating layer GTI1 may be disposed on the entire surface of the substrate SUB including the first active layer ACT1. The first gate insulating layer GTI1 may include tetraethoxysilane (TEOS), silicon nitride (SiNx), and silicon oxide (SiO 2 For example, the first gate insulating layer GTI1 may have a double-layer structure in which a silicon nitride layer having a thickness of 40 nm and a tetraethoxysilane layer having a thickness of 80 nm are sequentially stacked.

[0130] The first common gate electrode GE2 may be disposed on the first gate insulating layer GTI1. The first common gate electrode GE2 may be disposed on the first gate insulating layer GTI1 to overlap the first channel region CH1 of the first active layer ACT1.

[0131] The second gate insulating layer GTI2 may be disposed on the first common gate electrode GE2. The second gate insulating layer GTI2 may be disposed on the entire surface of the substrate SUB including the first common gate electrode GE2. The second gate insulating layer GTI2 may include the same material and structure as the first gate insulating layer GTI1 described above.

[0132] The second active layer ACT2 may be arranged on the second gate insulating layer GTI2. For example, the second active layer ACT2 may be arranged on the second gate insulating layer GTI2 so that the second channel region CH2 of the second active layer ACT2 overlaps with the first common gate electrode GE2 in the third direction DR3. In addition, the second active layer ACT2 may overlap with the first active layer ACT1 in the third direction DR3. The second drain electrode DE2 of the second active layer ACT2 may be connected to the first drain electrode DE1 of the first active layer ACT1 by the first contact hole CT1 penetrating the second gate insulating layer GTI2 and the first gate insulating layer GTI1, and the second source electrode SE2 of the second active layer ACT2 may be connected to the first source electrode SE1 of the first active layer ACT1 by the sixth contact hole CT6 penetrating the second gate insulating layer GTI2 and the first gate insulating layer GTI1.

[0133] The second active layer ACT2 may be a semiconductor such as an oxide semiconductor. For example, the second active layer ACT2 may include an oxide semiconductor including indium gallium zinc oxide (IGZO) or an oxide semiconductor including indium gallium zinc tin oxide (IGZTO).

[0134] The third gate insulating layer GTI3 may be disposed on the second active layer ACT2. The third gate insulating layer GTI3 may be disposed on the entire surface of the substrate SUB including the second active layer ACT2. The third gate insulating layer GTI3 may include the same material and structure as the first gate insulating layer GTI1 described above.

[0135] The first upper gate electrode GE3 may be arranged on the third gate insulating layer GTI3. The first upper gate electrode GE3 may be arranged on the third gate insulating layer GTI3 to overlap with the second channel region CH2 of the second active layer ACT2. The first upper gate electrode GE3 may be connected to the first common gate electrode GE2 through a third contact hole CT3 penetrating the third gate insulating layer GTI3 and the second gate insulating layer GTI2. In addition, the first upper gate electrode GE3 may be connected to the first lower gate electrode GE1 through a fifth contact hole CT5 penetrating the third gate insulating layer GTI3, the second gate insulating layer GTI2, the first gate insulating layer GTI1, and the buffer layer BF.

[0136] The interlayer insulating layer ITL may be disposed on the first upper gate electrode GE3. The interlayer insulating layer ITL may be disposed on the entire surface of the substrate SUB including the first upper gate electrode GE3. The interlayer insulating layer ITL may include an inorganic layer, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Meanwhile, the interlayer insulating layer ITL may include a plurality of inorganic layers.

[0137] The node connection electrode NCE may be disposed on the interlayer insulating layer ITL. The node connection electrode NCE may be connected to the first upper gate electrode GE3 through a fourth contact hole CT4 penetrating the interlayer insulating layer ITL.

[0138] The first planarization layer VA1 may be disposed on the node connection electrode NCE. The first planarization layer VA1 may be disposed on the entire surface of the substrate SUB including the node connection electrode NCE. The first planarization layer VA1 may be formed as an organic layer such as a layer of acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0139] The clock connection electrode CCE and the output connection electrode OCE may be arranged on the first planarization layer VA1. The clock connection electrode CCE may be connected to the second drain electrode DE2 of the second active layer ACT2 through a second contact hole CT2 penetrating the first planarization layer VA1, the interlayer insulating layer ITL, and the third gate insulating layer GTI3, and the output connection electrode OCE may be connected to the second source electrode SE2 of the second active layer ACT2 through a seventh contact hole CT7 penetrating the first planarization layer VA1, the interlayer insulating layer ITL, and the third gate insulating layer GTI3.

[0140] The second planarization layer VA2 may be disposed on the clock connection electrode CCE and the output connection electrode OCE. The second planarization layer VA2 may be disposed on the entire surface of the substrate SUB including the clock connection electrode CCE and the output connection electrode OCE. The second planarization layer VA2 may include the same material and structure as the above-mentioned first planarization layer VA1.

[0141] The dam PDL (or pixel defining layer) may be arranged on the second planarization layer VA2. The dam PDL is used to define the emission area of ​​the pixel. To this end, the dam PDL may be arranged to expose a partial area of ​​the pixel electrode (e.g., the anode electrode) on the second planarization layer VA2. The dam PDL may cover the edge of the pixel electrode. The dam PDL may be formed of an organic layer such as a layer of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0142] The common electrode CM may be arranged on the dam PDL. Meanwhile, the light emitting element LEL may include a pixel electrode, a light emitting layer on the pixel electrode, and a common electrode CM contacting the light emitting layer. The emission region refers to a region where the pixel electrode, the light emitting layer, and the common electrode CM are sequentially stacked and holes from the pixel electrode and electrons from the common electrode CM are combined with each other in the light emitting layer to emit light. In this case, the pixel electrode may be an anode electrode of the light emitting element, and the common electrode CM may be a cathode electrode of the light emitting element LEL.

[0143] The light emitting layer may include an organic material to emit a predetermined color. For example, the light emitting layer may include a hole transport layer, an organic material layer, and an electron transport layer. The organic material layer may include a host material and a dopant material. The organic material layer may include a material that emits light of a predetermined wavelength and may be formed using a phosphorescent material or a fluorescent material.

[0144] The organic material layer may include different regions containing different types of organic materials or layers to emit light of different colors. For example, the organic material layer may include a first light-emitting layer in a first emission region that emits light of a first color. The organic material layer may include a phosphorescent material including a host material and a dopant material, the host material including carbazole biphenyl (CBP) or mCP (1,3-bis(carbazole-9-yl)), and the dopant material including at least one selected from the group consisting of PIQIr(acac) (bis(1-phenylisoquinoline) iridium acetylacetonate), PQIr(acac) (bis(1-phenylquinoline) iridium acetylacetonate), PQIr(tris(1-phenylquinoline) iridium) and PtOEP (octaethylporphyrin platinum). Alternatively, the organic material layer of the first light-emitting layer of the first emission region may be a fluorescent material including PBD:Eu(DBM)3(benzene) or perylene, but the present disclosure is not limited thereto.

[0145] The organic material layer of the second light-emitting layer in the second emission region that emits light of the second color may be a phosphorescent material including a host material containing CBP or mCP and a dopant material containing Ir(ppy)3(factris(2-phenylpyridine)iridium. Alternatively, the organic material layer of the second light-emitting layer in the second emission region that emits light of the second color may be a fluorescent material including tris(8-hydroxyquinoline)aluminum (Alq3), but the present disclosure is not limited thereto.

[0146] The organic material layer of the third light emitting layer in the third emission region emitting light of the third color may be a phosphorescent material including a host material including CBP or mCP and a dopant material including (4,6-F2ppy)2Irpic or L2BD111, but the present disclosure is not limited thereto.

[0147] The common electrode CM mentioned above may be arranged on the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer. The common electrode CM may be arranged to cover the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer. The common electrode CM may be a common layer commonly arranged in the first light-emitting layer to the third light-emitting layer. A capping layer may be formed on the common electrode CM.

[0148] In the top emission structure, the common electrode CM may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the common electrode CM is formed of a semi-transmissive conductive material, luminous efficiency can be improved due to a microcavity effect.

[0149] In a top emission structure that emits light toward the common electrode CM relative to the light emitting layer, the pixel electrode may be formed of a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may be formed to have a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and ITO (ITO / APC / ITO) to increase reflectivity. The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0150] The spacer may be disposed on the dam PDL. The spacer may be used to support a mask during a process of manufacturing the light emitting layer. The spacer may be formed of an organic layer such as a layer of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0151] The encapsulation layer ENC may be formed on the light emitting element layer EMTL. The encapsulation layer ENC may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer EMTL. In addition, the encapsulation layer ENC may include at least one organic layer to protect the light emitting element layer EMTL from foreign matter such as dust. For example, the encapsulation layer ENC may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0152] The first inorganic encapsulation layer TFE1 may be arranged on the common electrode CM, the organic encapsulation layer TFE2 may be arranged on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be arranged on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed of a multilayer in which one or more inorganic layers of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked. The organic encapsulation layer TFE2 may be an organic layer such as a layer of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0153] At the same time, although not shown, Figure 6 The tenth transistor M10 may have the same Figure 7 , Figure 8 and Fig. 9 The ninth transistor M9 has the same configuration.

[0154] Fig.10 is included in Figure 3 1 is a circuit diagram of a stage (e.g., nth stage ST_n) in the emission control driver 450. The emission control driver 450 as described above applies an emission signal EM to an emission line EML. The emission line EML includes a plurality of emission lines, and for any integer n less than or equal to the number of emission lines EML, the nth stage applies an nth emission signal EM_n to the nth emission line.

[0155] like Fig.10 As shown in , the nth stage ST_n may include a node control unit NC, a carry output unit CRU, and a gate output unit GTU.

[0156] The nth stage ST_n may include a first transistor X1 to an eighth transistor X8, a ninth transistor M9 and a tenth transistor M10, an eleventh transistor X11 to a fifteenth transistor X15, a first capacitor XC1, a second capacitor XC2, a third capacitor XC3 and a fourth capacitor XC4. For example, the node control unit NC may include a first transistor X1 to an eighth transistor X8, an eleventh transistor X11, a twelfth transistor X12, a fifteenth transistor X15, a third capacitor XC3 and a fourth capacitor XC4. The carry output unit CRU may include a thirteenth transistor X13, a fourteenth transistor X14 and a first capacitor XC1. The gate output unit GTU may include a ninth transistor M9, a tenth transistor M10 and a second capacitor XC2. In this case, the ninth transistor M9 and the tenth transistor M10 may be output transistors that output the nth emission signal EM_n. For example, the ninth transistor M9 may be a pull-up transistor, and the tenth transistor M10 may be a pull-down transistor.

[0157] A gate electrode of the first transistor X1 may be connected to the first clock line CL1 , a drain electrode of the first transistor X1 may be connected to the gate output terminal GOT_n- 1 of the n-1th stage, and a source electrode of the first transistor X1 may be connected to the first set node NQ1 .

[0158] A gate electrode of the second transistor X2 may be connected to the first set node NQ1, a drain electrode of the second transistor X2 may be connected to the first clock line CL1, and a source electrode of the second transistor X2 may be connected to the first reset node NQB1. Meanwhile, the second transistor X2 may include a second-first sub-transistor X2-1 and a second-second sub-transistor X2-2 connected in series between the first clock line CL1 and the first reset node NQB1.

[0159] A gate electrode of the third transistor X3 may be connected to the first clock line CL1 , a drain electrode of the third transistor X3 may be connected to the gate high voltage line GHL, and a source electrode of the third transistor X3 may be connected to the first reset node NQB1 .

[0160] A gate electrode of the fourth transistor X4 may be connected to the second set node NQ2 , a drain electrode of the fourth transistor X4 may be connected to the third clock line CL3 , and a source electrode of the fourth transistor X4 may be connected to the drain electrode of the fifth transistor X5 .

[0161] A gate electrode of the fifth transistor X5 may be connected to the first reset node NQB1 , a drain electrode of the fifth transistor X5 may be connected to the source electrode of the fourth transistor X4 , and a source electrode of the fifth transistor X5 may be connected to the first gate low voltage line GLL1 .

[0162] A gate electrode of the sixth transistor X6 may be connected to the second reset node NQB2 , a drain electrode of the sixth transistor X6 may be connected to the third clock line CL3 , and a source electrode of the sixth transistor X6 may be connected to the drain electrode of the seventh transistor X7 .

[0163] A gate electrode of the seventh transistor X7 may be connected to the third clock line CL3 , a drain electrode of the seventh transistor X7 may be connected to the source electrode of the sixth transistor X6 , and a source electrode of the seventh transistor X7 may be connected to the third reset node NQB3 .

[0164] A gate electrode of the eighth transistor X8 may be connected to the first set node NQ1 , a drain electrode of the eighth transistor X8 may be connected to the third reset node NQB3 , and a source electrode of the eighth transistor X8 may be connected to the second gate low voltage line GLL2 .

[0165] The gate electrode of the ninth transistor M9 may be connected to the second set node NQ2, the drain electrode of the ninth transistor M9 may be connected to the gate high voltage line GHL, and the source electrode of the ninth transistor M9 may be connected to the gate output terminal GOT_n of the nth stage ST_n. Meanwhile, the gate electrode of the ninth transistor M9 may include a first gate electrode GE1 (hereinafter referred to as the first lower gate electrode GE1), a second gate electrode GE2 (hereinafter referred to as the first common gate electrode GE2), and a third gate electrode GE3 (hereinafter referred to as the first upper gate electrode GE3). Here, the first lower gate electrode GE1, the first common gate electrode GE2, and the first upper gate electrode GE3 of the ninth transistor M9 may be connected to each other. The ninth transistor M9 may include, for example, a ninth-first sub-transistor M9-1 and a ninth-second sub-transistor M9-2. The ninth-first sub-transistor M9-1 may include a first lower gate electrode GE1, a first common gate electrode GE2, a first drain electrode DE1, and a first source electrode SE1. The first lower gate electrode GE1 and the first common gate electrode GE2 of the ninth-first sub-transistor M9-1 may be connected to the set node NQ, the first drain electrode DE1 of the ninth-first sub-transistor M9-1 may be connected to the second clock line CL2, and the first source electrode SE1 of the ninth-first sub-transistor M9-1 may be connected to the gate output terminal GOT_n of the n-th stage ST_n. The ninth-second sub-transistor M9-2 may include a first upper gate electrode GE3, a first common gate electrode GE2, a second drain electrode DE2, and a second source electrode SE2. The first upper gate electrode GE3 and the first common gate electrode GE2 of the ninth-second sub-transistor M9-2 may be connected to the second set node NQ2, the second drain electrode DE2 of the ninth-second sub-transistor M9-2 may be connected to the gate high voltage line GHL, and the second source electrode SE2 of the ninth-second sub-transistor M9-2 may be connected to the gate output terminal GOT_n of the n-th stage ST_n.

[0166] The gate electrode of the tenth transistor M10 may be connected to the third reset node NQB3, the drain electrode of the tenth transistor M10 may be connected to the gate output terminal GOT_n of the nth stage ST_n, and the source electrode of the tenth transistor M10 may be connected to the first gate low voltage line GLL1. Meanwhile, the gate electrode of the tenth transistor M10 may include a first gate electrode GE11 (hereinafter referred to as the second lower gate electrode GE11), a second gate electrode GE22 (hereinafter referred to as the second common gate electrode GE22), and a third gate electrode GE33 (hereinafter referred to as the second upper gate electrode GE33). Here, the second lower gate electrode GE11, the second common gate electrode GE22, and the second upper gate electrode GE33 of the tenth transistor M10 may be connected to each other. The tenth transistor M10 may include, for example, a tenth-first sub-transistor M10-1 and a tenth-second sub-transistor M10-2. The tenth-first sub-transistor M10-1 may include a second lower gate electrode GE11, a second common gate electrode GE22, a third drain electrode, and a third source electrode. The second lower gate electrode GE11 and the second common gate electrode GE22 of the tenth-first sub-transistor M10-1 may be connected to the third reset node NQB3, the third drain electrode of the tenth-first sub-transistor M10-1 may be connected to the gate output terminal GOT_n of the n-th stage ST_n, and the third source electrode of the tenth-first sub-transistor M10-1 may be connected to the first gate low voltage line GLL1. The tenth-second sub-transistor M10-2 may include a second upper gate electrode GE33, a second common gate electrode GE22, a fourth drain electrode, and a fourth source electrode. The second upper gate electrode GE33 and the second common gate electrode GE22 of the tenth-second sub-transistor M10-2 may be connected to the third reset node NQB3, the fourth drain electrode of the tenth-second sub-transistor M10-2 may be connected to the gate output terminal GOT_n of the n-th stage ST_n, and the fourth source electrode of the tenth-second sub-transistor M10-2 may be connected to the first gate low voltage line GLL1.

[0167] A gate electrode of the eleventh transistor X11 may be connected to the gate high voltage line GHL, a drain electrode of the eleventh transistor X11 may be connected to the first reset node NQB1 , and a source electrode of the eleventh transistor X11 may be connected to the second reset node NQB2 .

[0168] A gate electrode of the twelfth transistor X12 may be connected to the gate high voltage line GHL, a drain electrode of the twelfth transistor X12 may be connected to the first set node NQ1 , and a source electrode of the twelfth transistor X12 may be connected to the second set node NQ2 .

[0169] A gate electrode of the thirteenth transistor X13 may be connected to the second set node NQ2 , a drain electrode of the thirteenth transistor X13 may be connected to the gate high voltage line GHL, and a source electrode of the thirteenth transistor X13 may be connected to the carry output terminal COT_n of the nth stage ST_n.

[0170] A gate electrode of the fourteenth transistor X14 may be connected to the third reset node NQB3 , a drain electrode of the fourteenth transistor X14 may be connected to the carry output terminal COT_n of the nth stage ST_n, and a source electrode of the fourteenth transistor X14 may be connected to the second gate low voltage line GLL2 .

[0171] The gate electrode of the fifteenth transistor X15 may be connected to the reset signal line RL, the drain electrode of the fifteenth transistor X15 may be connected to the first set node NQ1, and the source electrode of the fifteenth transistor X15 may be connected to the first gate low voltage line GLL1. Here, the reset signal line RL may transmit a reset signal ESR. The reset signal ESR may have, for example, the same level as the gate high voltage VGH. In another embodiment, the reset signal ESR may be an n+1 carry signal from a subsequent stage (e.g., the n+1 stage) of the emission control driver 450. For example, the reset signal ESR may be simultaneously applied to the gate electrode of the fifteenth transistor X15 provided in all stages of the emission control driver 450.

[0172] A first electrode of the first capacitor XC1 may be connected to the gate high voltage line GHL, and a second electrode of the first capacitor XC1 may be connected to the carry output terminal COT_n of the n-th stage ST_n.

[0173] A first electrode of the second capacitor XC2 may be connected to the third reset node NQB3 , and a second electrode of the second capacitor XC2 may be connected to the first gate low voltage line GLL1 .

[0174] A first electrode of the third capacitor XC3 may be connected to the second set node NQ2 , and a second electrode of the third capacitor XC3 may be connected to the source electrode of the fourth transistor X4 .

[0175] A first electrode of the fourth capacitor XC4 may be connected to the second reset node NQB2 , and a second electrode of the fourth capacitor XC4 may be connected to the source electrode of the sixth transistor X6 .

[0176] At the same time, although not shown, Fig.10 At least one of the ninth transistor M9 and the tenth transistor M10 may have the same Figure 7 , Figure 8 and Fig. 9 The ninth transistor M9 has the same configuration.

[0177] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the described embodiments without departing substantially from the principles of the present disclosure. Therefore, the described embodiments of the present disclosure disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, characterized in that: include: A substrate having a display area and a non-display area; a plurality of pixels, the plurality of pixels being arranged in the display area of ​​the substrate; as well as a gate driving circuit disposed in the non-display area of ​​the substrate and connected to the transistor of each of the plurality of pixels, Wherein, the gate drive circuit includes a pull-up transistor and a pull-down transistor, wherein at least one of the pull-up transistor and the pull-down transistor comprises a plurality of sub-transistors including a plurality of gate electrodes, and The plurality of sub-transistors share at least one of the plurality of gate electrodes.

2. The display device according to claim 1, characterized in that The plurality of gate electrodes include: a first gate electrode, the first gate electrode being arranged on the substrate; a second gate electrode disposed on the first gate electrode; and A third gate electrode is disposed on the second gate electrode.

3. The display device according to claim 2, characterized in that: The plurality of sub-transistors share the second gate electrode.

4. The display device according to claim 3, characterized in that The plurality of sub-transistors include a first sub-transistor and a second sub-transistor connected in parallel.

5. The display device according to claim 4, characterized in that: The first sub-transistor comprises: the first gate electrode; the second gate electrode; and A first active layer is disposed between the first gate electrode and the second gate electrode.

6. The display device according to claim 5, characterized in that: The second sub-transistor comprises: the second gate electrode; the third gate electrode; and A second active layer is disposed between the second gate electrode and the third gate electrode.

7. The display device according to claim 6, characterized in that: A portion of the first active layer corresponding to the first drain electrode of the first sub-transistor and a portion of the second active layer corresponding to the second drain electrode of the second sub-transistor are connected to each other.

8. The display device according to claim 6, characterized in that: A portion of the first active layer corresponding to the first source electrode of the first sub-transistor and a portion of the second active layer corresponding to the second source electrode of the second sub-transistor are connected to each other.

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