Nand flash memory testing device
By designing a Nand flash memory test device containing multiple SoC platforms and microcontrollers, the problem of low compatibility testing efficiency of Nand flash memory on different SoC platforms is solved, and compatibility testing on multiple platforms is realized, simplifying the Test the process and improve efficiency.
Patent Information
- Application Number
- CN202420827328.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-19
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-04-19
AI Technical Summary
Nand flash memory has low compatibility testing efficiency on different SoC platforms, and requires different systems to be built for each platform for testing. The process is complex and low efficiency.
Design a Nand flash memory test device, including multiple SoC platforms, microcontrollers and upper computers of different models, send test instructions to multiple SoC platforms through the microcontroller, realize the compatibility test of the flash memory to be tested on different models of platforms, simplifying Test process.
The one-time compatibility test of the flash memory to be tested on multiple SoC platforms is realized, which improves the testing efficiency, reduces the need for building systems for different SoC platforms, and improves the comprehensiveness and reliability of the test.
Smart Images
Figure CN222337929U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the field of memory testing, in particular to a Nand flash memory testing device. Background Art
[0002] Nand flash memory is a type of flash memory, also known as flash memory. Due to its advantages such as large capacity, fast rewrite speed, and many erasable times, it is widely used as a carrier for storing information in routers, optical modems, energy storage boards and other fields that require high stability. In response to different application requirements, a variety of different models of Nand flash memory have been produced.
[0003] For new models of Nand flash memory produced by storage manufacturers, it is necessary to perform compatibility tests on various platforms to ensure that the Nand flash memory can be mounted on different SoC (System on Chip) platforms and run stably. However, since there are many models of SoC platforms, the mainstream SoC platforms in China include MTK, RealTek, HiSilicon, ZTE Micro, Qualcomm, Broadcom, etc. In order to implement compatibility tests on Nand flash memory on various mainstream platforms, it is necessary to build different systems for different SoC platforms for testing, which makes the testing process complicated and the testing efficiency low. Utility Model Content
[0004] The main purpose of the utility model is to provide a Nand flash memory testing device, aiming to solve the problem of low efficiency of Nand flash memory compatibility testing.
[0005] To achieve the above object, the utility model provides a Nand flash memory test device, the Nand flash memory test device comprising:
[0006] Several SoC platforms of different models, each of which is equipped with a dynamic random access memory (DRAM), and each of the several SoC platforms is electrically connected to the flash memory to be tested, so as to test the compatibility of the flash memory to be tested on the several SoC platforms;
[0007] A single chip microcomputer is communicatively connected with the plurality of SoC platforms.
[0008] In some embodiments, the SoC platform includes a compatibility testing module and a data transmission module. The compatibility testing module is electrically connected to the flash memory to be tested and is used to perform a compatibility test on the flash memory to be tested; the data transmission module is electrically connected to the compatibility testing module and the single-chip microcomputer and is used to collect test data of the SoC platform and send it to the single-chip microcomputer.
[0009] In some embodiments, each of the SoC platforms is provided with at least one SPI interface (Serial Peripheral Interface) and at least one PPI interface (Parallel Peripheral Interface) for connecting different models of the flash memory to be tested.
[0010] In some embodiments, each of the SoC platforms is provided with four SPI interfaces and four PPI interfaces to form four SPI interface buses and four PPI interface buses; the flash memory to be tested is electrically connected to one of the SPI interface buses and one of the PPI interface buses respectively.
[0011] In some embodiments, the single chip microcomputer is electrically connected to the plurality of SoC platforms using an SPI bus.
[0012] In some embodiments, the Nand flash memory testing device further includes a host computer, and the host computer is communicatively connected with the single-chip microcomputer.
[0013] In some embodiments, the host computer is communicatively connected to the single chip microcomputer via a USB interface.
[0014] In some embodiments, the Nand flash memory testing device further includes a test socket, the flash memory to be tested is arranged on the test socket, and the test socket is electrically connected to the SoC platform.
[0015] In some embodiments, the Nand flash memory testing device further includes a power supply module, which is electrically connected to the SoC platform and is used to provide power to each of the SoC platforms.
[0016] In some embodiments, the power supply module includes a plurality of power on-off switches, and the plurality of power on-off switches are electrically connected to a plurality of the SoC platforms respectively.
[0017] The utility model sends test instructions to multiple SOC platforms of different models through a single chip microcomputer. Each SOC platform tests the flash memory to be tested according to the test instructions, so that the compatibility test of the flash memory to be tested on different types of SoC platforms can be completed at one time. Users do not need to build different systems for different SoC platforms, which greatly improves the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1 This is a structural schematic diagram of an embodiment of a Nand flash memory testing device of the utility model;
[0019] Figure 2 This is a structural schematic diagram of another embodiment of the Nand flash memory testing device of the utility model;
[0020] Figure 3 The figure is a schematic structural diagram of another embodiment of the Nand flash memory testing device of the present utility model.
[0021] Reference numerals:
[0022] 100. Single chip microcomputer; 200. SoC platform; 210. Dynamic random access memory; 220. Compatibility test module; 230. Data transmission module; 300. Flash memory to be tested; 400. Host computer. DETAILED DESCRIPTION
[0023] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the scheme in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.
[0024] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back...) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.
[0025] It should also be noted that when an element is referred to as being "fixed on" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element at the same time. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or there may be an intermediate element at the same time.
[0026] In addition, the descriptions of "first", "second", etc. in the present utility model are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present utility model.
[0027] The utility model provides a Nand flash memory test device, referring to Figure 1 , the Nand flash memory test device comprises:
[0028] Several different types of SoC platforms 200, each of which is equipped with a dynamic random access memory 210, and each of the SoC platforms 200 is electrically connected to a flash memory 300 to be tested, so as to test the compatibility of the flash memory 300 to be tested on the several SoC platforms 200;
[0029] The single-chip microcomputer 100 is communicatively connected with a plurality of SoC platforms 200 .
[0030] The Nand flash memory test device is mainly used to test the compatibility of the flash memory 300 to be tested on different platforms. Therefore, multiple SoC platforms 200 are of different models, and the flash memory 300 to be tested is electrically connected to all SoC platforms 200 at the same time, which is convenient for batch testing of the compatibility of the flash memory 300 to be tested, thereby improving the test efficiency. Specifically, the number of SoC platforms 200 can be selected as needed. For example, if the flash memory 300 to be tested needs to be applied to six different models of SoC platforms 200, the six different models of SoC platforms 200 are integrated on the same substrate, and each SoC platform 200 is independently configured with a dynamic random access memory 210 (hereinafter referred to as DRAM memory), so that each batch of flash memory 300 to be tested can continuously test its compatibility on six different SoC platforms 200. Of course, this is only exemplary and not restrictive. Among them, DRAM is used to store various applications, operating systems and other data, can provide temporary storage, and the read / write speed of DRAM is relatively fast, which can quickly provide the required data to the processor, thereby accelerating the operation speed and response speed of the system.
[0031] Among them, the SoC platform 200, as the core component of the test device, can run a specific test program to verify the compatibility of the flash memory 300 to be tested with the specific SoC platform 200. By using multiple different models of SoC platforms 200, it can be ensured that the application environment of various flash memories 300 to be tested is covered, and the comprehensiveness and reliability of the compatibility test are improved. The single-chip microcomputer 100 is connected to multiple SoC platforms 200 in communication, providing test control, data collection and analysis functions, and can remotely connect to other terminals through modules such as Bluetooth and Wi-Fi, so that users can remotely manage the test device, collect and read test data, and conduct comprehensive analysis and evaluation, which helps to improve test efficiency while reducing the cost and risk of manual intervention.
[0032] During testing, test instructions are sent to multiple SoC platforms 200 through the single-chip microcomputer 100. Each SoC platform 200 tests the flash memory 300 to be tested connected to it according to the test instructions, and sends the test data to the single-chip microcomputer 100 to analyze and process the test status of the SoC platform 200 and the test status of the flash memory 300 to be tested.
[0033] The utility model sends test instructions to multiple SOC platforms 200 of different models through the single-chip microcomputer 100. Each SOC platform 200 tests the flash memory 300 to be tested according to the test instructions, so that the flash memory 300 to be tested can complete the compatibility test of the flash memory 300 to be tested on different models of SoC platforms 200 at one time. Users do not need to build different systems for different SoC platforms 200, which greatly improves the test efficiency.
[0034] like Figure 2 As shown, in some embodiments, the SoC platform 200 includes a compatibility testing module 220 and a data transmission module 230. The compatibility testing module 220 is electrically connected to the flash memory 300 to be tested, and is used to perform a compatibility test on the flash memory 300 to be tested; the data transmission module 230 is electrically connected to the compatibility testing module 220 and the single-chip computer 100, and is used to collect test data of the SoC platform 200 and send it to the single-chip computer 100.
[0035] Among them, after the multiple SoC platforms 200 receive the test instructions sent by the single-chip computer 100, the compatibility test module 220 tests the flash memory 300 to be tested according to the test instructions, and comprehensively evaluates the compatibility and stability of the flash memory 300 to be tested in different environments, so as to find potential problems and defects of the flash memory 300 to be tested and improve its quality and reliability. The data transmission module 230 reads the test data from the compatibility test module 220 and sends the test data to the single-chip computer 100 for processing to obtain the test status of the flash memory 300 to be tested.
[0036] like Figure 3 As shown, in some embodiments, each SoC platform 200 is provided with at least one SPI interface and at least one PPI interface for connecting different types of flash memory 300 to be tested.
[0037] The flash memory 300 to be tested generally has two interfaces, namely SPI and PPI. In order to enable the SoC platform 200 to test the flash memory 300 to be tested with both interfaces, each SoC platform 200 is correspondingly provided with at least one SPI interface and at least one PPI interface to expand the test application scope of this embodiment. Specifically, if the interface of the flash memory 300 to be tested is SPI, the flash memory 300 to be tested is connected to the SPI interface of the SoC platform 200; if the interface of the flash memory 300 to be tested is PPI, the flash memory 300 to be tested is connected to the PPI interface of the SoC platform 200.
[0038] like Figure 3 As shown, in some embodiments, each SoC platform 200 is provided with four SPI interfaces and four PPI interfaces to form four SPI interface buses and four PPI interface buses; the flash memory 300 to be tested is electrically connected to one SPI interface bus and one PPI interface bus respectively.
[0039] Since different types of SoC platforms 200 support different numbers of interfaces, but at least support eight interfaces, in this embodiment, each SoC platform 200 is only provided with four SPI interfaces and four PPI interfaces ( Figure 3 Only two SPI interfaces and two PPI interfaces are shown in the figure), ensuring that all models of SoC platforms 200 can be implemented. It can be understood that if the SoC platform 200 undergoing compatibility testing can support more interfaces, more flash memory devices 300 to be tested can also be tested at the same time by setting more interfaces.
[0040] The bus is a shared communication channel that can connect multiple devices, including processors, memory, peripherals, etc. It provides a unified communication interface and protocol, making system design simpler and communication between devices simpler and more reliable. For example, by setting up the SPI bus, you only need to add a GPIO (General Purpose Input / Output) pin on the SoC platform 200 to add an SPI interface, which can improve the utilization rate of the SPI interface. Then, the interface on the flash memory 300 to be tested is directly connected to the bus, so that the connection between the flash memory 300 to be tested and each SoC platform 200 can be realized, which is more convenient and quick.
[0041] like Figure 3 As shown, in some embodiments, the single-chip microcomputer 100 is electrically connected to several SoC platforms 200 using the SPI bus. The single-chip microcomputer 100 uses the SPI bus to communicate with multiple SoC platforms 200 of different models, and can send test instructions to multiple SoC platforms 200 simultaneously, with simple communication and fast data transmission rate.
[0042] like Figure 3 As shown, in some embodiments, the Nand flash memory test device further includes a host computer 400, which is in communication connection with the single-chip computer 100. By adding the host computer 400, the single-chip computer 100 only needs to simply process various data of the test process, and then transmit the processed data to the host computer 400 for further analysis and processing, so as to improve the test efficiency of the entire test device.
[0043] like Figure 3 As shown, in some embodiments, the host computer 400 is connected to the single-chip microcomputer 100 through a USB interface. The USB interface is a universal serial bus interface that can be used to connect a computer and other external devices. The USB interface generally supports high-speed data transmission, high transmission efficiency, and supports hot-swap function. Users can plug and unplug USB devices without shutting down the computer or device, which is very convenient to use.
[0044] In some embodiments, the Nand flash memory test device further includes a test socket, and the flash memory 300 to be tested is disposed on the test socket, and the test socket is electrically connected to the SoC platform 200. The test socket is provided to facilitate the connection or port between the flash memory 300 to be tested and the SoC platform 200, and it is easier to set different types of interfaces on the test socket to test different types of flash memories 300 to be tested.
[0045] In some embodiments, the Nand flash memory test device further includes a power supply module, which is electrically connected to the SoC platform 200 and is used to provide power to each SoC platform 200. It is understandable that the power supply module can provide different voltages for different models of SoC platforms 200 so that the SoC platform 200 can work normally.
[0046] In some embodiments, the power supply module includes a plurality of power on-off switches, and the power supply module is electrically connected to a plurality of SoC platforms 200 through the plurality of power on-off switches. When any SoC platform 200 has a test abnormality / failure, the power supply module can control the power on-off switch corresponding to the SoC platform 200 to power off and shut down the SoC platform 200, so as to perform targeted maintenance to eliminate the fault, and other SoC platforms 200 are tested as usual, which reduces the impact on the overall test progress and improves the test efficiency.
[0047] The above description is only a partial or preferred embodiment of the present invention. Neither the text nor the drawings can limit the scope of protection of the present invention. All equivalent structural changes made by using the contents of the present invention specification and drawings under the overall concept of the present invention, or direct / indirect application in other related technical fields are included in the scope of protection of the present invention.
Claims
1. A Nand flash memory test device, characterized in that: include: Several SoC platforms of different models, each of which is equipped with a dynamic random access memory, and each of the SoC platforms is electrically connected to a flash memory to be tested, so as to test the compatibility of the flash memory to be tested on the several SoC platforms; A single chip microcomputer is communicatively connected with the plurality of SoC platforms.
2. The Nand flash memory test device according to claim 1, characterized in that: The SoC platform includes a compatibility testing module and a data transmission module. The compatibility testing module is electrically connected to the flash memory to be tested and is used to perform a compatibility test on the flash memory to be tested. The data transmission module is electrically connected to the compatibility testing module and the single-chip microcomputer and is used to collect test data of the SoC platform and send it to the single-chip microcomputer.
3. The Nand flash memory testing device according to claim 2, characterized in that: Each of the SoC platforms is provided with at least one SPI interface and at least one PPI interface for connecting different models of the flash memory to be tested.
4. The Nand flash memory testing device according to claim 3, characterized in that: Each of the SoC platforms is provided with four SPI interfaces and four PPI interfaces to form four SPI interface buses and four PPI interface buses; the flash memory to be tested is electrically connected to one of the SPI interface buses and one of the PPI interface buses respectively.
5. The Nand flash memory testing device according to claim 1, characterized in that: The single chip microcomputer is electrically connected to the plurality of SoC platforms by using an SPI bus.
6. The Nand flash memory test device according to claim 5, characterized in that: The Nand flash memory testing device also includes a host computer, which is communicatively connected with the single-chip microcomputer.
7. The Nand flash memory testing device according to claim 6, characterized in that: The host computer is connected to the single-chip computer through a USB interface.
8. The Nand flash memory testing device according to claim 1, characterized in that: The Nand flash memory testing device further comprises a test socket, the flash memory to be tested is arranged on the test socket, and the test socket is electrically connected to the SoC platform.
9. The Nand flash memory testing device according to any one of claims 1 to 8, characterized in that: The Nandflash memory testing device further comprises a power supply module, which is electrically connected to the SoC platform and is used to provide electric energy to each of the SoC platforms.
10. The Nand flash memory testing device according to claim 9, characterized in that: The power supply module includes a plurality of power on-off switches, and the power supply module is electrically connected to a plurality of the SoC platforms respectively through the plurality of power on-off switches.