Semiconductor device and integrated circuit

Abstract

A semiconductor device includes a substrate, a front-end module circuit over the substrate and configured to provide radio frequency communication, and a wafer-level wafer-size package circuit over and connected to the front-end module circuit, the wafer-level wafer-size package circuit configured to provide radio frequency communication between the front-end module circuit and the wafer-level wafer-size package circuit. The wafer level wafer size package circuitry is configured to provide passive elements for radio frequency communication. The disclosure also relates to a related integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and an integrated circuit. Background Art

[0002] Signal loss often becomes a serious problem in high-frequency circuit operations, such as millimeter-wavelength circuit operations. Typically, in millimeter-wavelength circuits, on-chip front-end devices are electrically connected to off-chip passive components, such as matching networks, power combiners, and antennas. On-chip front-end devices include radio frequency (RF) communication circuits, such as millimeter-wavelength communication circuits operating in the frequency range of 30 to 300 gigahertz (GHz). However, signal loss between on-chip front-end circuits and off-chip passive components becomes significant at millimeter-wavelength frequencies. To compensate for these losses, power amplifiers (PAs) and low-noise amplifiers (LNAs) use strict design specifications. Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor device, including: a substrate; a front-end module circuit, located on the substrate and configured to provide radio frequency communications; and a wafer-level chip-scale package circuit, located on the front-end module circuit and connected to the front-end module circuit, the wafer-level chip-scale package circuit being configured to provide passive components for radio frequency communications.

[0004] In some embodiments, the radio frequency communication is millimeter wavelength communication.

[0005] In some embodiments, the front-end module circuit includes a radio frequency power amplifier and a radio frequency low noise amplifier.

[0006] In some embodiments, the wafer level chip scale package circuit includes a radio frequency matching network, a radio frequency power synthesizer, and an antenna, wherein the antenna is used for phased array communication.

[0007] In some embodiments, the WLCSP circuit includes a redistribution layer that is part of at least one of a radio frequency matching network, a radio frequency power combiner, and an antenna.

[0008] Some embodiments of the present disclosure provide an integrated circuit, comprising: a substrate; a front-end module circuit, located on the substrate and comprising a radio frequency power amplifier and a radio frequency low noise amplifier; and a wafer-level chip size packaging circuit, located on the front-end module circuit and connected to the front-end module circuit, the wafer-level chip size packaging circuit comprising a radio frequency matching network and an antenna.

[0009] In some embodiments, the WLCSP circuit further includes a radio frequency power combiner.

[0010] In some embodiments, the WLCSP circuit includes a redistribution layer, which is part of a capacitor in the RF matching network or the RF power combiner.

[0011] In some embodiments, the integrated circuit further comprises a front side and a back side, wherein the WLCSP circuit is located on the front side, and a through silicon via extends through the substrate to the back side.

[0012] In some embodiments, the integrated circuit further includes a backside wafer-level chip scale package circuit connected to the through silicon via and configured to provide wiring for the wafer-level chip scale package circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The concepts of the disclosed embodiments are better understood with reference to the following detailed description and the accompanying drawings. It should be noted that, according to standard practice in the industry, the various features in the drawings are not necessarily drawn to scale. In fact, the sizes of the various features may be arbitrarily enlarged or reduced to make a clear description.

[0014] Figure 1 is a diagram schematically showing a semiconductor device including a front-end module circuit and a wafer-level chip-scale package (WLCSP) circuit according to some embodiments.

[0015] Figure 2 is a diagram schematically showing an example of a matching network according to some embodiments.

[0016] Figure 3 is a diagram schematically showing an example of a power combiner according to some embodiments.

[0017] Figure 4 is a diagram schematically showing an example of an antenna according to some embodiments.

[0018] Figure 5 is a schematic diagram showing the Figure 1 Schematic diagram of an example cross section of a semiconductor grain.

[0019] Figure 6 is a diagram schematically showing a cross section of a semiconductor die having a capacitor made of a redistribution layer (RDL) or a portion of a RDL and an under bump metal (UBM) according to some embodiments.

[0020] Figure 7 is a schematic diagram schematically showing a cross section of a semiconductor die and a printed circuit board (PCB) according to some embodiments.

[0021] Figure 8 is a schematic diagram showing the Figure 1 A cross-section of a semiconductor die and a schematic diagram of a printed circuit board, wherein the semiconductor die includes a through-silicon-via (TSV) and a backside WLCSP circuit.

[0022] Fig. 9 is a diagram schematically showing a simulated graph of self-resonant frequencies (SRFs) of four inductors according to some embodiments.

[0023] Fig.10 is a diagram schematically showing a graph of Q-factors of CMOS-based inductors L1 and L2 and Q-factors of WLCSP-based inductors L1_2 and L2_2 according to some embodiments.

[0024] Fig.11 is a diagram schematically illustrating a method of operating a device according to some embodiments.

[0025] Fig.12 is a block diagram schematically showing an example of a computer system configured to provide the semiconductor device and method of the present disclosure according to some embodiments.

[0026] Fig.13 is a block diagram of a semiconductor device manufacturing system and a semiconductor device manufacturing flow associated therewith according to some embodiments.

[0027] The reference numerals are described as follows:

[0028] 20: Semiconductor devices / semiconductor chips

[0029] 22: Front-end module circuit

[0030] 24: Wafer Level Chip Scale Package (WLCSP) Circuit

[0031] 26: Power amplifier (PA)

[0032] 28: Low Noise Amplifier (LNA)

[0033] 30: Matching Network

[0034] 32: Power combiner

[0035] 34: Antenna

[0036] 36: Inductor

[0037] 38: (First) Capacitor

[0038] 40: (Second) Capacitor

[0039] 42: First transformer winding / transformer

[0040] 44: Second transformer winding / transformer

[0041] 46: Third transformer winding / transformer

[0042] 48: Redistribution Layer

[0043] 60: Section

[0044] 62: Substrate

[0045] 64: Passivation layer

[0046] 66: First dielectric layer

[0047] 68: Aluminum pad

[0048] 70: Redistribution layer

[0049] 72: Second dielectric layer

[0050] 74: Under Bump Metal

[0051] 76: Solder ball

[0052] 80: Capacitor

[0053] 84: Section

[0054] 86: Printed Circuit Board

[0055] 88: Under Bump Metal

[0056] 90: Solder ball

[0057] 92: Solder ball electrical contact

[0058] 94: Substrate

[0059] 96: Redistribution Layer

[0060] 98: Metal layer

[0061] 100: redistribution layer

[0062] 104: Section

[0063] 106: Printed Circuit Board

[0064] 108: Through Silicon Via

[0065] 110: Backside WLCSP circuit

[0066] 112: Substrate

[0067] 114: Under Bump Metal

[0068] 116: Solder ball

[0069] 118: Solder ball electrical contact

[0070] 120: Redistribution layer

[0071] 122: Metal layer

[0072] 124: Redistribution layer

[0073] 130: Graph

[0074] 132: x-axis

[0075] 134: y-axis

[0076] 140: Graph

[0077] 142: x-axis

[0078] 144: y-axis

[0079] 150, 152, 154: Step 200: (Computer) System

[0080] 202: Processor

[0081] 204: Computer readable storage media

[0082] 206: Instructions

[0083] 208: Manufacturing tools

[0084] 210: Bus

[0085] 212: Input / output (I / O) interface

[0086] 214: Network interface

[0087] 216: Network

[0088] 218: Database

[0089] 220: User Interface (UI)

[0090] 222: (Semiconductor device manufacturing) system

[0091] 224: Design Studio

[0092] 226: Mask Studio

[0093] 228: Manufacturing Plant

[0094] 230: Design Layout

[0095] 232: Data Preparation

[0096] 234: Mask manufacturing

[0097] 236: Photomask

[0098] 238: Semiconductor wafers

[0099] 240: Wafer Manufacturing

[0100] 242: Semiconductor devices DETAILED DESCRIPTION

[0101] The following disclosure provides many different embodiments or examples to implement different features of the embodiments of the present disclosure. The following describes specific examples of components and configurations to simplify the description of the embodiments of the present disclosure. Of course, these specific examples are only for demonstration and are not intended to limit the embodiments of the present disclosure. For example, in the following description, it is mentioned that the first feature is formed on or above the second feature, which means that it may include an embodiment in which the first feature and the second feature are in direct contact, and may also include an embodiment in which an additional feature is formed between the first feature and the second feature, so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference symbols and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself limit the relationship between the various embodiments and / or configurations described.

[0102] Furthermore, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element or feature(s) depicted in the drawings. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be oriented in different orientations (rotated 90 degrees or at other orientations) and the spatially relative terms used herein should be interpreted similarly.

[0103] Embodiments disclosed herein provide a front-end module circuit operating in the millimeter-wavelength frequency range, which is integrated with a wafer-level chip-scale package (WLCSP) circuit, wherein the WLCSP circuit includes passive components or portions of passive components, such as matching networks, power combiners, and antennas for phased-array antenna operation. The front-end module circuit and the WLCSP circuit are integrated into the same semiconductor die.

[0104] The WLCSP circuits are manufactured using a far back-end package process that builds the semiconductor die from an initial complementary metal-oxide-semiconductor (CMOS) circuit. The WLCSP circuits include passive metal layers for wafer-scale package interconnections to reduce parasitic elements such as resistance, capacitance, and inductance from the semiconductor die to the printed circuit board (PCB). In the disclosed embodiments, these passive metal layers are used in the WLCSP circuits to provide passive elements for radio frequency (RF) millimeter wavelength applications.

[0105] Therefore, the disclosed embodiments can implement passive circuit design in WLCSP circuits, such as matching networks, power combiners, and antennas, and integrate WLCSP circuits with front-end module circuits (e.g., CMOS millimeter-wavelength front-end module circuits). Using WLCSP circuits, the front-end module circuits can be fully integrated with the passive components of the WLCSP circuits to reduce high-frequency signal losses.

[0106] Figure 1 2 is a schematic diagram schematically showing a semiconductor device 20 including a front-end module circuit 22 and a WLCSP circuit 24 according to some embodiments. The front-end module circuit 22 and the WLCSP circuit 24 are integrated with each other on the semiconductor device 20 and are configured to provide RD communication. In some embodiments, each of the front-end module circuit 22 and the WLCSP circuit 24 is configured to provide millimeter wavelength communication, for example, in a frequency range of 30 to 300 gigahertz (GHz).

[0107] The front-end module circuit 22 includes a power amplifier (PA) 26 and a low-noise amplifier (LNA) 28. Each of the PA 26 and the LNA 28 is electrically connected to the WLCSP circuit 24 on the semiconductor die 20 and is configured to operate within the RF signal range. The PA 26 is configured to transmit RF signals to the WLCSP circuit 24, while the LNA 28 is configured to receive RF signals from the WLCSP circuit 24. In some embodiments, each of the PA 26 and the LNA 28 is configured to operate within a millimeter wavelength frequency range (e.g., 30 to 300 GHz). In some embodiments, the front-end module circuit 22 is located on a substrate of the semiconductor die 20.

[0108] The WLCSP circuit 24 includes passive components or portions of passive components, such as a matching network 30, a power combiner 32, and an antenna 34. Each of the matching network 30 and the power combiner 32 is electrically connected to the front-end module circuit 22 and the antenna 34. The matching network 30 and the power combiner 32 are configured to operate within the RF signal range, and in some embodiments, are configured to operate within the millimeter wavelength frequency range (e.g., 30 to 300 GHz). In some embodiments, the WLCSP circuit 24 is located on or above the front-end module circuit 22. In addition, in some embodiments, the front-end module circuit 22 is integrated with the antenna 34 and associated circuits (e.g., the matching network 30 and the power combiner 32) to provide phased array operation in a phased array architecture and reduce or prevent signal loss.

[0109] Figure 2 is a diagram schematically showing an example of a matching network 30 according to some embodiments. The matching network 30 includes an inductor 36, a first capacitor 38, and a second capacitor 40. One end of the inductor 36 is connected to one end of the first capacitor 38, and the other end of the first capacitor 38 is connected to a reference point, such as ground. The other end of the inductor 36 is connected to one end of the second capacitor 40, and the other end of the second capacitor 40 is connected to a reference point, such as ground.

[0110] Matching network 30 provides impedance matching to improve power transfer between front end module circuitry 22 and antenna 34 using an interconnecting transmission line to antenna 34. If the transmission line is terminated with a matching impedance, such as that provided by matching network 30, signals on the transmission line are transmitted without reflections.

[0111] Figure 3is a schematic diagram schematically showing an example of a power combiner 32 according to some embodiments. The power combiner 32 includes a first transformer winding 42, a second transformer winding 44, and a third transformer winding 46. The first transformer winding 42, the second transformer winding 44, and the third transformer winding 46 are in-phase with each other. The second transformer winding 44 and the third transformer winding 46 transmit power to the first transformer winding 42. In some embodiments, the power combiner 32 can be used as a power divider, wherein the first transformer winding 42 transmits power to the second transformer winding 44 and the third transformer winding 46. In some embodiments, the power combiner 32 is implemented or made by a transmission line.

[0112] Figure 4 is a diagram schematically showing an example of an antenna 34 according to some embodiments. In some embodiments, WLCSP circuit 24 includes a redistribution layer (RDL), and antenna 34 includes at least a portion of redistribution layer 48. In addition, in some embodiments, matching network 30 includes at least a portion of the RDL located in WLCSP circuit 24, and in some embodiments, power combiner 32 includes at least a portion of the RDL located in WLCSP circuit 24. In some embodiments, antenna 34 is in the form of a patch antenna. In some embodiments, antenna 34 is in the form of a dipole antenna.

[0113] Figure 5 is a schematic diagram showing the Figure 1 FIG. 6 is a schematic diagram of an exemplary cross-section 60 of a semiconductor die 20. The semiconductor die 20 includes a front-end module circuit 22 and a WLCSP circuit 24 (eg, Figure 1 ).

[0114] The cross-section 60 of the semiconductor die 20 includes a substrate 62, such that the front-end module circuit 22 is formed on, over, and / or in the substrate 62 and supported by the substrate 62. In the case where the front-end module circuit 22 is located on or over the substrate 62, a passivation layer 64 is disposed or formed over the substrate 62 and the front-end module circuit 22. In some embodiments, the substrate 62 is silicon. In some embodiments, the passivation layer 64 is an oxide layer.

[0115] The semiconductor die 20 and the WLCSP circuit 24 include a first dielectric layer 66 disposed or formed on the passivation layer 64. An aluminum pad 68 is connected to the front-end module circuit 22, and a gap is formed in the passivation layer 64 and the first dielectric layer 66 above the aluminum pad 68. A redistribution layer 70 is formed on the first dielectric layer 66 and contacts the aluminum pad 68 and the front-end module circuit 22 through the gap formed in the passivation layer 64 and the first dielectric layer 66. A second dielectric layer 72 is disposed or formed on the redistribution layer 70 and the first dielectric layer 66. In addition, an under-bump metal (UBM) 74 is formed through the gap in the second dielectric layer 72 to contact the redistribution layer 70. A solder ball 76 is disposed on the under-bump metal 74 and connected to the under-bump metal 74 for contacting a circuit outside the semiconductor die 20. In some embodiments, the first dielectric layer 66 is a polybenzoxazole (PBO) layer, and in some embodiments, the second dielectric layer 72 is a PBO layer. In addition, in some embodiments, the redistribution layer 70 is made of copper (Cu), and in some embodiments, the under bump metal 74 is a thin film metal layer stack.

[0116] The passive components of the WLCSP circuit 24 include a matching network 30, a power combiner 32, and an antenna 34 (shown in FIG. Figures 2 to 4 In some embodiments, the WLCSP circuit 24 may be made of a redistribution layer 70 or a portion of a redistribution layer 70 and an under bump metallurgy 74. In some embodiments, the WLCSP circuit 24 may be made of a redistribution layer 70 or a portion of a redistribution layer 70 and an under bump metallurgy 74. The quality factor of each passive component in the WLCSP circuit 24 is fundamentally improved due to the large vertical spacing from the substrate 62. In some embodiments, at least one of the inductor 36 and / or the capacitors 38 and 40 is made of a redistribution layer 70 or a portion of a redistribution layer 70 and an under bump metallurgy 74. In some embodiments, at least one and at most all of the transformers 42, 44, and 46 are made of a redistribution layer 70 or a portion of a redistribution layer 70 and an under bump metallurgy 74.

[0117] Figure 6 is a diagram schematically showing a cross section 60 of a semiconductor die 20 having a capacitor 80 made of a redistribution layer 70 or a portion of a redistribution layer 70 and an under bump metallurgy 74 according to some embodiments. Capacitor 80 may be used in a matching network 30 or a power combiner 32. In some embodiments, capacitor 80 is one of capacitors 38 and 40 in matching network 30. In some embodiments, capacitor 80 is implemented using coupling between a redistribution layer 70 and a routing layer (e.g., an aluminum layer in or on substrate 62) in WLCSP circuit 24.

[0118] Figure 7is a diagram schematically showing a cross section 84 of a semiconductor die 20 and a printed circuit board (PCB) 86 according to some embodiments. The cross section 84 of the semiconductor die 20 includes a WLCSP circuit 24 located on and above the front end module circuit 22. The WLCSP circuit 24 includes an under bump metallization 88 electrically connected to solder balls 90, and the solder balls 90 are electrically connected to solder ball electrical contacts 92 of the printed circuit board 86 to form electrical contact between the semiconductor die 20 and the printed circuit board 86.

[0119] The cross section 84 of the semiconductor die 20 includes a substrate 94, such that the front end module circuitry 22 is formed on, over, and / or in, and supported by the substrate 94. In the case where the front end module circuitry 22 is located on the substrate 94, the WLCSP circuitry 24 is disposed or formed on or over the substrate 94 and the front end module circuitry 22. In some embodiments, the substrate 94 is silicon.

[0120] The passive components of the WLCSP circuit 24 include a matching network 30 and a power combiner 32 (shown in FIG. Figure 2 and Figure 3 In some embodiments, the antenna 34 may be made of a redistribution layer 96 or a portion of the redistribution layer 96 and the under bump metallization 88 of the WLCSP circuit 24. The antenna 34 may be made of a redistribution layer 100 or a portion of the redistribution layer 100 and the under bump metallization 88 in the WLCSP circuit 24. In other embodiments, at least a portion of at least one passive component of the WLCSP circuit 24, such as at least a portion of the matching network 30 and / or the power combiner 32, may be made of a metal layer 98 in the substrate 94.

[0121] The WLCSP circuit 24 enables area-efficient integration of the RD front-end module circuit 22 (including the millimeter-wavelength front-end module circuit 22) by allowing the use of low-loss passive structures in the WLCSP circuit 24, enabling signal shielding of one or more metal layers of the semiconductor die 20, and enabling digital and analog circuits to be built from lower-level metals in the semiconductor die 20.

[0122] Figure 8 is a schematic diagram showing the Figure 1 FIG. 1 is a schematic diagram of a cross-section 104 of a semiconductor die 20 and a printed circuit board 106, wherein the semiconductor die 20 includes a through-silicon-via (TSV) 108 and a backside WLCSP circuit 110. The cross-section 104 of the semiconductor die 20 includes a front-end module circuit 22 (shown in FIG. 1 ). Figure 1The front side WLCSP circuit 24 is disposed on and above the front side WLCSP circuit 24. The through silicon via 108 extends from the front end module circuit 22 and / or the front side WLCSP circuit 24 through the substrate 112 of the semiconductor die 20 to the back side WLCSP circuit 110. Through the through silicon via 108, the back side WLCSP circuit 110 can be a passive component (e.g., matching network 30, power combiner 32 and antenna 34 (shown in FIG. 1 ) Figures 1 to 4 Provide routing.

[0123] The front side WLCSP circuit 24 includes an under bump metallization (UBM) 114 electrically connected to solder balls 116, which are electrically connected to solder ball electrical contacts 118 of the printed circuit board 106 to form electrical contacts between the semiconductor die 20 and the printed circuit board 106. In addition, the cross section 104 of the semiconductor die 20 includes a substrate 112, such that the front end module circuit 22 is formed on, over, and / or in the substrate 112 and supported by the substrate 112. In the case where the front end module circuit 22 is located on the substrate 112, the front side WLCSP circuit 24 is disposed and / or formed on and over the substrate 112 and the front end module circuit 22.

[0124] Passive components include a matching network 30 and a power combiner 32 (shown in FIG. Figure 2 and Figure 3 ), can be made of the redistribution layer 120 or part of the redistribution layer 120 and the under bump metallization 114 of the front side WLCSP circuit 24, the metal layer 122 in the substrate 112, and / or the back side WLCSP circuit 110 through the silicon via 108. In addition, the antenna 34 can be made of the redistribution layer 124 or part of the redistribution layer 124 and the under bump metallization 114 and / or the back side WLCSP circuit 110 in the front side WLCSP circuit 24 through the silicon via 108.

[0125] Fig. 9 1 is a schematic diagram schematically showing a simulated graph 130 of self-resonant frequencies (SRF) of four inductors according to some embodiments. Two of the inductors L1 and L2 are made of complementary metal oxide semiconductor (CMOS) processes instead of being made of the redistribution layer of the WLCSP circuit. The other two inductors L1_2 and L2_2 are made of the redistribution layer of the WLCSP circuit, such as the redistribution layer 70 (shown in FIG. 1 ) of the WLCSP circuit 24. Figure 5 Graph 130 has frequency in gigahertz (GHz) plotted along an x-axis 132 and inductance in pico-Henries (p) plotted along a y-axis 134 .

[0126] The SRF of each CMOS inductor L1 and L2 is about 183 GHz, while the SRF of each WLCSP inductor L1_2 and L2_2 is about 449.6 GHz. Therefore, using the RDL of the WLCSP circuit to make the inductors L1_2 and L2_2 increases the SRF by about 2.5 times. This is due to the larger vertical spacing between the inductors L1_2 and L2_2 made of the RDL of the WLCSP circuit and the substrate.

[0127] Fig.10 1 is a diagram of a graph 140 schematically showing Q-factors of CMOS-based inductors L1 and L2 and Q-factors of WLCSP-based inductors L1_2 and L2_2 according to some embodiments. The graph on the left shows the Q-factors Q1 and Q2 of the CMOS-based inductors L1 and L2, while the graph on the right shows the Q-factors Q1 and Q2 of the WLCSP-based inductors L1_2 and L2_2. The graph 140 has a frequency in gigahertz (GHz) plotted along each x-axis 142, and an S-parameter (Q-factor) plotted along each y-axis 144.

[0128] The Q factor of CMOS inductor L1 is about 11.7 at about 122 GHz, while the Q factor of CMOS inductor L2 is about 9.85 at about 122 GHz. The Q factor of WLCSP inductor L1_2 is about 21.8 at about 270.7 GHz, while the Q factor of WLCSP inductor L2_2 is about 17.5 at about 270.7 GHz. Therefore, using the RDL of the WLCSP circuit to make WLCSP inductors L1_2 and L2_2 can increase the Q factor frequency, for example, to more than 120 GHz, and increase each Q factor by about 2 times. This is due to the larger vertical spacing between the inductors L1_2 and L2_2 made of the RDL of the WLCSP circuit and the substrate.

[0129] Fig.11 is a schematic diagram schematically illustrating a method of operating a device according to some embodiments. At step 150, the method includes transmitting a first RF signal from a front-end module circuit located on a substrate. In some embodiments, the front-end module circuit is similar to the front-end module circuit 22 (shown in FIG. Figure 1 and Figures 5 to 8 In some embodiments, the substrate may be substrate 62 (shown in Figure 5 ), substrate 94 (shown in Figure 7 ) and / or substrate 112 (shown in Figure 8 In some embodiments, the first RF signal is a millimeter wavelength signal, for example, in the frequency range of 30 to 300 GHz.

[0130] At step 152, the method includes receiving a first RF signal from the front-end module circuit at a WLCSP circuit located above and connected to the front-end module circuit. At step 154, the method includes transmitting the first RF signal from the WLCSP circuit. In some embodiments, the WLCSP circuit is such as WLCSP circuit 24 (shown in FIG. Figure 1 and Figures 5 to 8 middle).

[0131] In some embodiments, the method further includes receiving a second RF signal at the WLCSP circuit, transmitting the second RF signal from the WLCSP circuit to the front-end module circuit, and receiving the second RF signal at the front-end module circuit. In some embodiments, the second RF signal is a millimeter wavelength signal, such as in the frequency range of 30 to 300 GHz.

[0132] In some embodiments, receiving the first RF signal from the front-end module circuit at the WLCSP circuit and transmitting the first RF signal from the WLCSP circuit includes communicating the first RF signal through at least a portion of an RDL in the WLCSP circuit. In some embodiments, communicating the first RF signal through at least a portion of the RDL includes communicating the first RF signal through at least a portion of a copper RDL or a capacitor including the RDL.

[0133] Fig.12 2 is a block diagram schematically showing an example of a computer system 200 configured to provide the semiconductor devices and methods of the present disclosure according to some embodiments. Part or all of the design, layout, and fabrication of semiconductor devices (also referred to as semiconductor circuits) may be performed by or in conjunction with the computer system 200. In some embodiments, the computer system 200 includes an electronic design automation (EDA) system. In some embodiments, the semiconductor devices are integrated circuits (ICs).

[0134] In some embodiments, system 200 is a general purpose computing device including a processor 202 and a non-transitory computer readable storage medium 204. Computer readable storage medium 204 may be encoded with (e.g., store) computer program code, such as executable instructions 206. Execution of instructions 206 by processor 202 (at least in part) provides design tools that implement some or all of the functions of system 200, such as pre-layout simulation, post-layout simulation, routing, re-routing, and final layout for manufacturing. In addition, manufacturing tools 208 are included to further layout and physically implement the design and manufacture of semiconductor devices. In some embodiments, system 200 includes a commercial router. In some embodiments, in some embodiments, system 200 includes an automatic place and route (APR) system.

[0135] The processor 202 is electrically coupled to the computer readable storage medium 204 through the bus 210, and is electrically coupled to the input / output (I / O) interface 212 through the bus 210. The network interface 214 is also electrically coupled to the processor 202 through the bus 210. The network interface 214 is connected to the network 216 so that the processor 202 and the computer readable storage medium 204 can be connected to external components using the network 216. The processor 202 is configured to execute computer program code or instructions 206 encoded in the computer readable storage medium 204 to cause the system 200 to perform some or all of the functions of the system 200, such as providing the semiconductor device and method of the present disclosure and other functions of the system 200. In some embodiments, the processor 202 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0136] In some embodiments, the computer-readable storage medium 204 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 204 may include semiconductor or solid-state memory, magnetic tape, removable computer diskette, random access memory (RAM), read-only memory (ROM), rigid magnetic disk, and / or optical disk. In some embodiments using optical disks, the computer-readable storage medium 204 may include compact disk read only memory (CD-ROM), compact disk read / write (CD-R / W), and / or digital video disc (DVD).

[0137] In some embodiments, computer readable storage medium 204 stores computer program code or instructions 206 configured to cause system 200 to perform some or all of the functions of system 200. In some embodiments, computer readable storage medium 204 also stores information that facilitates the performance of some or all of the functions of system 200. In some embodiments, computer readable storage medium 204 stores database 218 that includes one or more of component libraries, digital circuit cell libraries, and databases.

[0138] System 200 includes an I / O interface 212 that is coupled to external circuits. In some embodiments, I / O interface 212 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor arrow keys for transmitting information and commands to processor 202.

[0139] The network interface 214 is coupled to the processor 202 and allows the system 200 to communicate with a network 216, wherein one or more other computer systems are connected to the network 216. The network interface 214 may include a wireless network interface, such as BLUETOOTH, WIFI, WIMAX (Worldwide Interoperability for Microwave Access), GPRS (General Packet Radio Service), or WCDMA (Wideband Code Division Multiple Access); or a wired network interface, such as ETHERNET, USB, or IEEE-1364. In some embodiments, some or all of the functions of the system 200 may be performed in two or more systems similar to the system 200.

[0140] The system 200 is configured to receive information through the I / O interface 212. The information received through the I / O interface 212 includes one or more of instructions, data, design rules, component and cell libraries, and / or other parameters processed by the processor 202. The information is transmitted to the processor 202 through the bus 210. In addition, the system 200 is configured to receive information related to a user interface (UI) through the I / O interface 212. This UI information can be stored in the computer readable storage medium 204 as a user interface (UI) 220.

[0141] In some embodiments, some or all of the functions of system 200 are implemented by a stand-alone software application executed by a processor. In some embodiments, some or all of the functions of system 200 are implemented in a software application that is part of an additional software application. In some embodiments, some or all of the functions of system 200 are implemented as a plug-in of a software application. In some embodiments, at least one function of system 200 is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the functions of system 200 are implemented as a software application used by system 200. In some embodiments, the layout diagram is generated using tools such as VIRTUOSO provided by Cadence Design Systems, Inc. or other suitable layout generation tools.

[0142] In some embodiments, the wiring, layout and other processing are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs (e.g., digital video discs or digital versatile discs (DVDs)), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM and RAM), and memory cards, etc.

[0143] As described above, embodiments of the system 200 include a fabrication tool 208 for implementing a fabrication process of the system 200. For example, a lithography mask may be generated based on the final layout, and the fabrication tool 208 may use the lithography mask to fabricate a semiconductor device.

[0144] Other aspects of device fabrication will be combined with Fig.13 illustrate, Fig.13 is a block diagram of a semiconductor device manufacturing system 222 and a semiconductor device manufacturing process associated therewith according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 222 is used to manufacture at least one element in a layer of one or more semiconductor masks and / or semiconductor devices.

[0145] exist Fig.13 In the present invention, a semiconductor device manufacturing system 222 includes multiple entities, such as a design house 224, a mask house 226, and a semiconductor device manufacturer / fabricator ("Fab") 228, which interact with each other in design, development, and manufacturing cycles and / or services related to manufacturing semiconductor devices (e.g., the semiconductor devices described herein). The entities in the system 222 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities or receives services from one or more other entities. In some embodiments, two or more of the design studio 224, the mask house 226, and the semiconductor device manufacturing plant 228 are owned by a single larger company. In some embodiments, two or more of the design studio 224 , the mask studio 226 , and the semiconductor device fabrication facility 228 are co-located in a common facility and utilize common resources.

[0146] The design studio (or design team) 224 generates a semiconductor device design layout 230. The semiconductor device design layout 230 includes various geometric patterns or semiconductor device layouts designed for the semiconductor device. The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that constitute various elements of the semiconductor structure to be manufactured. The various layers are combined to form various semiconductor device features. For example, a portion of the semiconductor device design layout 230 includes various semiconductor device features to be formed in a semiconductor substrate (e.g., a silicon wafer) and in various material layers disposed on the semiconductor substrate, such as diagonal vias, active regions or areas, gate electrodes, sources, drains, metal lines, local vias, and openings for bonding pads. The design studio 224 executes a design program to form the semiconductor device design layout 230. The semiconductor device design layout 230 is presented as one or more data files having geometric pattern information. For example, the semiconductor device design layout 230 can be represented in a graphic database system II (GDS II) file format or a DFII file format. In some embodiments, the design procedure includes one or more of analog circuit design, digital circuit design, logic circuit design, standard cell circuit design, power distribution network (PDN) design (including power via design), supply voltage track design, reference voltage track design, place and route routines, and physical layout design.

[0147] The mask studio 226 includes data preparation 232 and mask manufacturing 234. The mask studio 226 uses the semiconductor device design layout 230 to manufacture one or more masks 236 for manufacturing various layers or semiconductor structures of the semiconductor device. The mask studio 226 performs mask data preparation 232, wherein the semiconductor device design layout 230 is converted into a representative data file (RDF). The mask data preparation 232 provides the RDF to the mask manufacturing 234. The mask manufacturing 234 includes a mask writer that converts the RDF into an image on a substrate, such as a mask (reticle 236) or a semiconductor wafer 238. The design layout 230 is processed through the mask data preparation 232 to conform to the characteristics of the mask writer and / or the standards of the semiconductor device manufacturing plant 228. In Fig.132, mask data preparation 232 and mask manufacturing 234 are shown as separate elements. In some embodiments, mask data preparation 232 and mask manufacturing 234 may be collectively referred to as mask data preparation.

[0148] In some embodiments, the mask data preparation 232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. The optical proximity correction adjusts the semiconductor device design layout 230. In some embodiments, the mask data preparation 232 further includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, etc. or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0149] In some embodiments, mask data preparation 232 includes a mask rule checker (MRC) that checks the semiconductor device design layout 230 that has undergone OPC processing using a set of mask creation rules, including specific geometric and / or connection constraints to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the mask rule checker modifies the semiconductor device design layout 230 to compensate for the constraints during mask fabrication 234, and it can undo some of the modifications performed by OPC to meet the mask creation rules.

[0150] In some embodiments, the mask data preparation 232 includes a lithography process checking (LPC), which simulates a process to be performed by the semiconductor device manufacturing plant 228. The lithography process checking simulates this process based on the semiconductor device design layout 230 to create a simulated manufactured device. The processing parameters in the lithography process checking may include parameters associated with various processes of the semiconductor device manufacturing cycle, parameters associated with the tools used to manufacture the semiconductor device, and / or other aspects of the manufacturing process. The lithography process checking may consider various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc. or combinations thereof. In some embodiments, after creating a simulated manufactured device through the lithography process checking (LPC), if the simulated device is not close enough in shape to meet the design criteria, the OPC and / or MRC may be repeated to further refine the semiconductor device design layout 230.

[0151] For the sake of clarity, the above description of the mask data preparation 232 has been simplified. In some embodiments, the data preparation 232 includes additional features such as logic operations (LOP) to modify the semiconductor device design layout 230 according to manufacturing criteria. In addition, the processing applied to the semiconductor device design layout 230 during the data preparation 232 can be performed in a variety of different orders.

[0152] After the mask data preparation 232 and during the mask manufacturing 234, a mask 236 or a group of masks 236 are manufactured based on the modified semiconductor device design layout 230. In some embodiments, the mask manufacturing 234 includes performing one or more lithography exposures based on the semiconductor device design layout 230. In some embodiments, based on the modified semiconductor device design layout 230, a pattern is formed on the mask (photomask or shrink mask) 236 using an electron beam (e-beam) or a plurality of electron beams. The mask 236 can be formed using various techniques. In some embodiments, the mask 236 is formed using a binary technology. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque area and transmitted through the transparent area. In one example, a binary mask version of the mask 236 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) coated in the opaque areas of the binary mask. In another example, a phase shift technique is used to form the mask 236. In a phase shift mask (PSM) version of the mask 236, various features in the pattern formed on the phase shift mask are configured to have an appropriate phase difference to improve resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask generated by the mask manufacturing 234 is used in various processes. For example, the mask is used in an ion implantation process to form various doped regions in the semiconductor wafer 238, in an etching process to form various etched regions in the semiconductor wafer 238, and / or in other suitable processes.

[0153] Semiconductor device manufacturing plant 228 includes wafer manufacturing 240. Semiconductor device manufacturing plant 228 is a semiconductor device manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different semiconductor device products. In some embodiments, semiconductor device manufacturing plant 228 is a semiconductor foundry. For example, there may be a manufacturing facility for front end of line (FEOL) manufacturing of multiple semiconductor device products, a second manufacturing facility for back end of line (BEOL) manufacturing of interconnection and packaging of semiconductor device products, and a third manufacturing facility that provides other services to the foundry entity.

[0154] The semiconductor device manufacturing plant 228 uses the mask 236 generated by the mask studio 226 to manufacture the semiconductor structure or semiconductor device 242 of the present disclosure. Therefore, the semiconductor device manufacturing plant 228 at least indirectly uses the semiconductor device design layout 230 to manufacture the semiconductor structure or semiconductor device 242 of the present disclosure. In addition, the semiconductor wafer 238 includes a silicon substrate or other suitable substrate on which a material layer is formed, and the semiconductor wafer 238 also includes one or more of various doping regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps). In some embodiments, the semiconductor wafer 238 is manufactured by the semiconductor device manufacturing plant 228 using the mask 236 to form the semiconductor structure or semiconductor device 242 of the present disclosure. In some embodiments, semiconductor device manufacturing includes performing one or more lithography exposures based at least indirectly on the semiconductor device design layout 230.

[0155] Embodiments disclosed in the present application provide a front-end module circuit operating in an RF frequency range, which is integrated with a WLCSP circuit operating in the RF frequency range. The WLCSP circuit includes passive components or portions of passive components, such as matching networks, power synthesizers, and antennas. The front-end module circuit and the WLCSP circuit are integrated on the same semiconductor die. In some embodiments, the RF frequency range is within the millimeter wavelength frequency range. In some embodiments, the front-end module circuit and the WLCSP circuit provide phased array antenna operation.

[0156] In some embodiments, the WLCSP circuit is fabricated using a remote back-end packaging process on an original or primary CMOS circuit. The WLCSP circuit includes passive metal layers for wafer scale package interconnects to reduce parasitic elements between the semiconductor die and the printed circuit board. In the disclosed embodiments, these passive metal layers are used in the WLCSP circuit to provide passive elements for RF applications.

[0157] Therefore, the disclosed embodiments implement passive circuits, such as matching networks, power combiners, and antennas, in WLCSP circuits, and integrate the WLCSP circuits with front-end module circuits (e.g., CMOS millimeter-wavelength front-end module circuits), wherein the front-end module circuits are fully integrated with the passive components of the WLCSP circuits to reduce high-frequency signal losses.

[0158] According to some embodiments, a semiconductor device includes a substrate, a front-end module circuit, and a wafer-level chip scale package circuit. The front-end module circuit is located on the substrate and configured to provide radio frequency communication. The wafer-level chip scale package circuit is located on the front-end module circuit and connected to the wafer-level chip scale package circuit and configured to provide a passive component for radio frequency communication.

[0159] According to some other embodiments, an integrated circuit includes a substrate, a front-end module circuit, and a wafer-level chip scale package circuit. The front-end module circuit is located on the substrate and includes a radio frequency power amplifier and a radio frequency low noise amplifier. The wafer-level chip scale package circuit is located on the front-end module circuit and connected to the wafer-level chip scale package circuit, and includes a radio frequency matching network and an antenna.

[0160] According to yet other embodiments, a method of operating a device includes: transmitting a first RF signal from a front-end module circuit located on a substrate; receiving the first RF signal from the front-end module circuit at a wafer-level chip scale packaging circuit, wherein the wafer-level chip scale packaging circuit is located on the front-end module circuit and connected to the front-end module circuit; and transmitting the first RF signal from the wafer-level chip scale packaging circuit.

[0161] The features of many embodiments are summarized above so that those with ordinary knowledge in the technical field to which the present disclosure belongs can better understand the various embodiments of the present disclosure. Those with ordinary knowledge in the technical field to which the present disclosure belongs should understand that other processes and structures can be easily designed or changed based on the embodiments of the present disclosure to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those with ordinary knowledge in the technical field to which the present disclosure belongs should also understand that these equivalent structures do not deviate from the spirit and scope of the present disclosure. Various changes, substitutions and modifications may be made to the embodiments of the present disclosure without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, characterized in that: include: a substrate; a front-end module circuit located on the substrate and configured to provide radio frequency communication; as well as A wafer-level chip scale package circuit is located on the front-end module circuit and connected to the front-end module circuit. The wafer-level chip scale package circuit is configured to provide a passive component for radio frequency communication.

2. The semiconductor device according to claim 1, wherein The radio frequency communication is millimeter wavelength communication.

3. The semiconductor device according to claim 1, wherein The front-end module circuit includes a radio frequency power amplifier and a radio frequency low noise amplifier.

4. The semiconductor device according to claim 1, wherein: The wafer-level chip size package circuit includes a radio frequency matching network, a radio frequency power synthesizer and an antenna, and the antenna is used for phased array communication.

5. The semiconductor device according to claim 1, wherein: The wafer level chip scale package circuit includes a redistribution layer, which is a part of at least one of a radio frequency matching network, a radio frequency power combiner, and an antenna.

6. An integrated circuit, characterized in that: include: a substrate; A front-end module circuit is located on the substrate and includes a radio frequency power amplifier and a radio frequency low noise amplifier; as well as A wafer-level chip size package circuit is located on the front-end module circuit and connected to the front-end module circuit. The wafer-level chip size package circuit includes a radio frequency matching network and an antenna.

7. The integrated circuit according to claim 6, characterized in that The wafer level chip scale package circuit further includes a radio frequency power synthesizer.

8. The integrated circuit according to claim 7, characterized in that The wafer level chip scale package circuit includes a redistribution layer, which is a part of a capacitor in the radio frequency matching network or the radio frequency power combiner.

9. The integrated circuit according to claim 6, characterized in that The device further includes a front side and a back side, wherein the wafer level chip scale package circuit is located on the front side, and a through silicon via extends through the substrate to the back side.

10. The integrated circuit according to claim 9, characterized in that The invention further includes a backside wafer level chip scale package circuit connected to the through silicon via and configured to provide wiring for the wafer level chip scale package circuit.

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