Trench gate silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with internal current equalization

Abstract

The utility model provides an internal current-sharing trench gate silicon carbide VDMOS. The internal current-sharing trench gate silicon carbide VDMOS is characterized in that the lower side surface of a drift layer is connected to a silicon carbide substrate; the lower side of the buffer is connected to the upper side of the drift layer; the lower side surface of the well region is connected to the upper side surface of the buffer region; the lower side surface of the P-type source region is connected to the upper side surface of the well region; the lower side surface of the N-type source region is connected to the upper side surface of the well region; one side surface of the N-type source region is connected to one side surface of the P-type source region; the lower part of the gate dielectric layer is arranged in the groove, one side surface of the gate dielectric layer is connected to the other side surface of the N-type source region, and a groove is formed in the gate dielectric layer; the source metal layer is respectively connected with the P-type source region and the N-type source region; the gate metal layer is arranged in the groove; and the drain metal layer is connected to the lower side surface of the silicon carbide substrate, so that the overall on-resistance is lower, and the heat distribution is more uniform.

Description

Technical Field

[0001] The utility model relates to a trench gate silicon carbide VDMOS with internal current equalization. Background Art

[0002] Silicon carbide MOSFET is a typical representative of SiC power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. The development of device structure and preparation process has promoted the reduction of device on-resistance and the improvement of reliability. The existing silicon carbide devices have higher and higher power density, which has also led to the heat dissipation of devices becoming a technical difficulty. The heat distribution of the device is concentrated, which makes the heat dissipation of the device more difficult and limits the development of the device. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a trench gate silicon carbide VDMOS with internal current equalization, so that the overall on-resistance is lower and the heat distribution is more uniform.

[0004] The utility model is implemented as follows: an internal current-balanced trench-gate silicon carbide VDMOS, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the silicon carbide substrate;

[0007] A buffer zone, wherein the lower side of the buffer zone is connected to the upper side of the drift layer;

[0008] A well region, wherein the lower side of the well region is connected to the upper side of the buffer region, and a groove is provided on the well region;

[0009] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region;

[0010] An N-type source region, wherein a lower side of the N-type source region is connected to an upper side of the well region, and a side of the N-type source region is connected to a side of the P-type source region;

[0011] a gate dielectric layer, wherein the lower portion of the gate dielectric layer is disposed in the groove, one side of the gate dielectric layer is connected to the other side of the N-type source region, and a groove is disposed in the gate dielectric layer;

[0012] A source metal layer, the source metal layer is respectively connected to the well region, the P-type source region and the N-type source region;

[0013] A gate metal layer, wherein the gate metal layer is disposed in the groove;

[0014] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0015] The advantages of the utility model are:

[0016] 1. The device adopts a trench VDMOS structure, which makes the on-resistance of the device small;

[0017] Second, in order to solve the problem of electric field concentration at the gate corner of silicon carbide VDMOS, the P-type well region wraps the bottom of the gate to suppress the electric field concentration problem at the gate corner;

[0018] 3. When the current of the trench gate silicon carbide VDMOS flows from the n+ source region to the drain, the electron concentration is high near the gate area, forming a current direction close to the gate, making the current distribution inside the device more concentrated, and the overall on-resistance of the device is relatively large. Before the current flows through the P-type well region and reaches the drift layer, the current is redistributed through the buffer zone, making the current distribution inside the device more balanced, the overall on-resistance of the device lower, and the thermal distribution more reasonable;

[0019] Fourth, a buffer zone and a well zone are formed directly below the trench gate of the device, which can suppress the rapid diffusion of the electric field to the bottom of the trench gate when the drain is subjected to a large voltage for a short time, effectively protect the gate dielectric layer, and improve the gate reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0021] Figure 1 The utility model is a schematic diagram of a trench gate silicon carbide VDMOS with internal current equalization.

[0022] Figure 2 The utility model is a flow chart of a method for preparing a trench gate silicon carbide VDMOS with internal current equalization.

[0023] Figure 3 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 1 .

[0024] Figure 4 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 2 .

[0025] Figure 5 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 3 .

[0026] Figure 6 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 4 .

[0027] Figure 7 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 5 .

[0028] Figure 8 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 6 .

[0029] Fig. 9 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 7 .

[0030] Fig.10 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 8 .

[0031] Fig.11 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 9 .

[0032] Fig.12 This is a cross-sectional view of the process of a trench gate silicon carbide VDMOS with internal current equalization in the utility model. Figure 10 . DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0035] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0036] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0037] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] like Figure 1 As shown, the embodiment of the present application provides a trench gate silicon carbide VDMOS with internal current equalization, including:

[0039] Silicon carbide substrate 101,

[0040] A drift layer 102 , wherein the lower side of the drift layer 102 is connected to the silicon carbide substrate 101 ;

[0041] A buffer zone 103, wherein the lower side of the buffer zone 103 is connected to the upper side of the drift layer 102;

[0042] A well region 104, wherein the lower side of the well region 104 is connected to the upper side of the buffer region 103, and a groove 1041 is provided on the well region 104;

[0043] A P-type source region 105, wherein the lower side of the P-type source region 105 is connected to the upper side of the well region 104;

[0044] An N-type source region 106, wherein the lower side of the N-type source region 106 is connected to the upper side of the well region 104, and one side of the N-type source region 106 is connected to one side of the P-type source region 105;

[0045] A gate dielectric layer 107, wherein the lower portion of the gate dielectric layer 107 is disposed in the groove 1041, one side of the gate dielectric layer 107 is connected to the other side of the N-type source region 106, and a groove 1071 is disposed in the gate dielectric layer 107;

[0046] A source metal layer 108 , wherein the source metal layer 108 is respectively connected to the well region 104 , the P-type source region 105 , and the N-type source region 106 ;

[0047] A gate metal layer 109, wherein the gate metal layer 109 is disposed in the groove 1071;

[0048] and a drain metal layer 110 , wherein the drain metal layer 110 is connected to the lower side of the silicon carbide substrate 101 .

[0049] The buffer zone 103 includes a first N-type buffer layer 1031 and a second N-type buffer layer 1032. The first N-type buffer layer 1031 is arranged directly below the groove 1041. The lower side of the well region 104 is respectively connected to the upper side of the first N-type buffer layer 1031 and the upper side of the second N-type buffer layer 1032. The lower side of the first N-type buffer layer 1031 and the lower side of the second N-type buffer layer 1032 are both connected to the upper side of the drift layer 102.

[0050] like Figures 2 to 12 As shown, the method for preparing the above silicon carbide VDMOS comprises the following steps:

[0051] Step 1: depositing metal on the lower side of the silicon carbide substrate 101 to form a drain metal layer 110, and epitaxially growing on the upper side of the silicon carbide substrate 101 to form a drift layer 102, wherein the thickness of the drift layer 102 is 3-6 μm;

[0052] Step 2: forming a barrier layer a on the drift layer 102, etching the barrier layer a to form a through hole, performing ion implantation on the drift layer 102 to form a first N-type buffer layer 1031, the ion implantation energy is 400-600kev, and the depth is 1200nm-1800nm; removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a to form a through hole, performing ion implantation on the drift layer 102 to form a second N-type buffer layer 1032, the ion implantation energy is 400-600kev, and the depth is 1200nm-1800nm; the buffer zone 103 includes a first N-type buffer layer 1031 and a second N-type buffer layer 1032, the doping concentration of the first N-type buffer layer 1031 is 2e16cm -3 The doping concentration of the second N-type buffer layer 1032 is 6e16cm -3 ;

[0053] Step 3: remove the original barrier layer a, and perform ion implantation on the drift layer 102 to form a well region 104; the implantation energy is 10-400kev, and the depth is 1200nm;

[0054] Step 4: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform ion implantation on the well region 104, form an N-type source region 106, the implantation energy is 10-200kev, and the depth is 600nm;

[0055] Step 5: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, and perform ion implantation on the well region 104 to form a P-type source region 105; the implantation energy is 10-200kev, and the depth is 600nm;

[0056] Step 6: remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a, form a through hole, perform metal deposition, and form a source metal layer 108;

[0057] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching the barrier layer a, the drift layer 102 and the well region 104 to form a through hole and a groove 1041, and then performing deposition to form a gate dielectric layer 107;

[0058] Step 8, remove the original barrier layer a, re-form the barrier layer a, etch the barrier layer a and the gate dielectric layer 107 to form a through hole and a groove 1071, deposit metal on the groove 1071 to form a gate metal layer 109, remove the barrier layer a, and complete the preparation.

[0059] The silicon carbide substrate 101 and the drift layer 102 are both N-type, the well region 104 is P-type, and the distance L from the bottom of the gate dielectric layer 107 to the upper side of the buffer region 103 is 100-200 nm.

[0060] The doping concentration of the silicon carbide substrate 101 is 2e18 cm -3 , the doping concentration of the drift layer 102 is 6e16cm -3 , the doping concentration of the first N-type buffer layer 1031 is 2e16cm -3 The doping concentration of the second N-type buffer layer 1032 is 6e16cm -3 The doping concentration of the well region 104 is 1e17 cm -3 The doping concentration of the N-type source region 106 is 2e18cm -3 The doping concentration of the P-type source region 105 is 1e19cm -3 , the gate dielectric layer 107 is silicon dioxide; the doping concentration of the N-type silicon carbide substrate 101 is to ensure the formation of a low-resistance ohmic contact with the drain metal layer 110, and reduce the overall on-resistance of the device. The doping concentration of the N-type drift layer 102 is a compromise between the reverse withstand voltage and the on-resistance of the device. The first N-type buffer layer 1031 and the second N-type buffer layer 1032 have two functions. The first is to reduce the on-resistance of the device, and the second is to make the carriers from the left and right sides of the device close to the gate redistribute in the buffer zone 103 after passing through the P-type well region 104, so as to ensure that the carriers are uniformly distributed in the lateral direction and the heat distribution is more uniform. The doping concentration of the P-type well region 104 is a compromise between protecting the device gate, suppressing the device off-state current and reducing the driving loss of the device when it is fully turned on. The doping concentration of the N-type source region 106 is to form a very low-resistance ohmic contact of the source, and the doping concentration of the P-type source region 105 is to form a low-resistance ohmic contact of the source and a low-resistance body diode freewheeling.

[0061] The thickness of the silicon carbide substrate 101 of the device is 1 μm, and the thickness of the N-type drift layer 102 is 3-6 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device; the thickness of the N-type buffer region 103 is 600 nm, the thickness of the N-type source region 106 and the P-type source region 105 is 600 nm, and the distance L from the bottom of the gate dielectric layer 107 to the first N-type buffer region 103 is 100-200 nm, which is the process error of the etching depth, preferably 200 nm, the bottom thickness of the gate dielectric layer is 70 nm, and the side wall thickness is 50 nm;

[0062] The first N-type buffer layer 1031 and the P-type well region 104 below the trench gate form a protective layer from the device drain to the gate insulating dielectric layer, which can buffer the impact of transient large drain current on the device gate insulation mechanism and improve gate reliability.

[0063] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A trench gate silicon carbide VDMOS with internal current sharing, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the silicon carbide substrate; A buffer zone, wherein the lower side of the buffer zone is connected to the upper side of the drift layer; A well region, wherein the lower side of the well region is connected to the upper side of the buffer region, and a groove is provided on the well region; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the well region; An N-type source region, wherein a lower side of the N-type source region is connected to an upper side of the well region, and a side of the N-type source region is connected to a side of the P-type source region; a gate dielectric layer, wherein the lower portion of the gate dielectric layer is disposed in the groove, one side of the gate dielectric layer is connected to the other side of the N-type source region, and a groove is disposed in the gate dielectric layer; A source metal layer, the source metal layer is respectively connected to the well region, the P-type source region and the N-type source region; A gate metal layer, wherein the gate metal layer is disposed in the groove; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. The internal current-balanced trench gate silicon carbide VDMOS according to claim 1, characterized in that: The buffer zone includes a first N-type buffer layer and a second N-type buffer layer, the first N-type buffer layer is arranged directly below the groove, the lower side of the well region is respectively connected to the upper side of the first N-type buffer layer and the upper side of the second N-type buffer layer, and the lower side of the first N-type buffer layer and the lower side of the second N-type buffer layer are both connected to the upper side of the drift layer.

3. The internal current-balanced trench gate silicon carbide VDMOS according to claim 1, characterized in that: The silicon carbide substrate and the drift layer are both N-type, and the well region is P-type.

4. The internal current-balanced trench gate silicon carbide VDMOS according to claim 1, characterized in that: The distance from the bottom of the gate dielectric layer to the upper side of the buffer zone is 100-200 nm.

5. The internal current-balanced trench gate silicon carbide VDMOS according to claim 1, characterized in that: The drift layer thickness is 3-6μm.

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