Manufacturing method of super junction device

Abstract

The invention discloses a manufacturing method of a super junction device. The manufacturing method comprises the following steps: growing a first epitaxial layer; a plurality of trench gates are formed in a first epitaxial layer, gate conductive material layers outside gate trenches of the trench gates are all removed, and the top surfaces of the gate conductive material layers in the gate trenches are flat, so that the formation process of a subsequent second trench is ensured to be realized. And forming a well region and performing annealing. And performing photoetching and etching to form a plurality of second grooves, wherein the first epitaxial layer between the second grooves is used as a first conductive type column. And growing a second conductive type doped second epitaxial layer in the second groove, completely removing the second epitaxial layer outside the second groove, flattening the surface of the second epitaxial layer in the second groove, and forming a second conductive type column by the second epitaxial layer filled in the second groove. And a subsequent front process is completed, and a thermal process is set according to the requirement for controlling mutual diffusion of PN impurities of the super junction structure. And completing a back process. According to the invention, mutual diffusion of PN impurities of the super junction structure can be effectively controlled.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a superjunction (SJ) device. Background Art

[0002] Compared with the existing traditional VDMOS, the existing super junction MOSFET has been widely used in various electronic power fields due to its excellent device characteristics. Due to the special N pillar (N-type pillar) and P pillar (P-type pillar) in the super junction MOSFET structure, it can achieve a high breakdown voltage at a relatively high N-type epitaxial layer (NEPI) epitaxial concentration. Therefore, it has a low on-resistance and high breakdown voltage that exceeds the limit of Si.

[0003] There are two main manufacturing processes for existing super junction MOSFET devices. One is to accumulate mutually spaced P-type regions, namely P-type columns, and N-type regions, namely N-type columns, through multiple epitaxial deposition and photolithography. The other is to form P-type columns on a thick N epitaxial layer through deep trenches and trench filling, thereby forming mutually spaced P-type regions and N-type regions. In the existing deep trench technology, in order to implement the planarization process of deep trench P-type columns well, the P-type column formation process is usually placed before the polysilicon formation process such as the polysilicon formation process of the gate structure. At the same time, the P-type well process is sometimes placed after the P-type column is formed. In this way, the P-type column and the N-type column are formed after the P-type column of the trench is formed, and then go through the gate oxide process and other high-temperature process thermal processes, resulting in the mutual diffusion of P-type column impurities and N-type column impurities, which increases the source-drain on-resistance (Rdson) of the device and affects the chip performance. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method for manufacturing a super junction device, which can independently set the thermal process of the trench gate, the thermal process of the well region and the thermal process of the super junction structure, so that the quality of the trench gate and the well region can be guaranteed while the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost.

[0005] In order to solve the above technical problems, the present invention provides a method for manufacturing a super junction device, comprising the following steps:

[0006] A first epitaxial layer doped with a first conductivity type is grown on the surface of the semiconductor substrate.

[0007] A plurality of trench gates are formed in the first epitaxial layer, the trench gates comprising a gate oxide layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench; each of the trench gates is located in a subsequent corresponding first conductive type column; the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer in the gate trench is flat to ensure the implementation of a subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0008] A well region doped with a second conductive type is formed by photolithography and ion implantation and the well region is annealed. Each trench gate passes through the well region. The thermal process of the annealing of the well region is adjusted to push the well region to a set position and repair ion implantation damage.

[0009] Photolithography and etching are performed to form a plurality of second trenches in the first epitaxial layer, and the first epitaxial layer between the second trenches serves as a first conductive type column.

[0010] A second epitaxial layer doped with a second conductive type is grown in the second trench, the second epitaxial layer outside the second trench is completely removed and the surface of the second epitaxial layer in the second trench is flattened, a second conductive type column is formed by the second epitaxial layer filled in the second trench, and a super junction structure is formed by alternating the first conductive type columns and the second conductive type columns.

[0011] After the super junction structure is completed, a subsequent front process is performed. In the subsequent front process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement.

[0012] Complete the backside process of super junction devices.

[0013] A further improvement is that the material of the semiconductor substrate includes silicon, the material of the first epitaxial layer includes silicon, and the material of the second epitaxial layer includes silicon.

[0014] A further improvement is that the steps of forming the trench gate include:

[0015] A first dielectric layer is formed on a top surface of the first epitaxial layer.

[0016] The formation area of ​​the gate trench is defined by photolithography.

[0017] The first dielectric layer and the first epitaxial layer in the formation region of the gate trench are sequentially etched to form the gate trench.

[0018] The gate oxide layer is formed by a thermal oxidation process.

[0019] The gate conductive material layer is formed.

[0020] A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

[0021] A further improvement is that the gate conductive material layer is made of polysilicon.

[0022] A further improvement is that before or after the first chemical mechanical polishing process, the method further comprises:

[0023] A rapid thermal oxidation (RTO) or a rapid thermal annealing (RTA) is performed.

[0024] A further improvement is that the maximum annealing temperature of the well region reaches above 1100° C. and the annealing time reaches above 30 minutes.

[0025] A further improvement is that before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer.

[0026] In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

[0027] A further improvement is that the hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence.

[0028] After the etching of the second trench is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench are removed, and then the second epitaxial layer is grown.

[0029] Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

[0030] A further improvement is that the subsequent front surface process includes:

[0031] Photolithography and ion implantation are performed to form a heavily doped source region of the first conductivity type, wherein the source region and the corresponding side surface of the gate trench are self-aligned.

[0032] The source region is annealed and activated. The annealing of the source region is performed in a furnace tube at a temperature below 950° C. or in a rapid thermal annealing.

[0033] A further improvement is that the subsequent front surface process further includes:

[0034] An interlayer film is formed, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0035] A contact hole opening is formed through the interlayer film.

[0036] A second conductive type heavily doped contact region is formed at the bottom of the contact hole opening.

[0037] A metal layer is filled in the contact hole opening to form a contact hole.

[0038] A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

[0039] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0040] A dielectric protection layer is formed; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0041] The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0042] A further improvement is that it also includes performing a front passivation protection process, the front passivation protection process including:

[0043] A polyimide layer is formed.

[0044] The polyimide layer is patterned by photolithography and development to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0045] The polyimide layer is baked.

[0046] A further improvement is that the metal layer forming the contact hole comprises:

[0047] A barrier layer is formed, wherein the barrier layer is formed on the inner surface of the contact hole opening.

[0048] A tungsten layer is formed, the tungsten layer filling the contact hole opening.

[0049] The barrier layer and the tungsten layer also extend onto the surface of the interlayer film outside the contact hole opening.

[0050] The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer in the front metal layer removal area are also removed, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area.

[0051] Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed or the front metal layer is directly formed.

[0052] A further improvement is that the material of the front metal layer includes AlCu.

[0053] The material of the barrier layer includes a Ti layer and a TiN layer stacked in sequence.

[0054] The material of the second barrier layer includes a Ti layer and a TiN layer stacked in sequence.

[0055] A further improvement is that the backside process includes:

[0056] The semiconductor substrate is back-thinned.

[0057] A drain region heavily doped with the first conductivity type is formed; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is directly composed of the thinned semiconductor substrate; or, the drain region is composed of a backside injection region of the semiconductor substrate heavily doped with the second conductivity type on the backside.

[0058] A back metal layer is formed and a drain electrode is formed from the back metal layer.

[0059] A further improvement is that the back metal layer includes TiNiAg.

[0060] A further improvement is that the setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

[0061] A further improvement is that the second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant.

[0062] Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, and the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of adjacent first conductive type columns and corresponding second conductive type columns at each longitudinal position meets the requirements.

[0063] Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

[0064] A further improvement is that after the first chemical mechanical polishing process, the process further includes making the top surface of the gate conductive material layer in the gate trench below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second groove.

[0065] The present invention makes special arrangements for the process flow of the super junction device, mainly placing the trench gate and well region forming processes with high requirements on the thermal process before the super junction structure forming process, and setting the flatness of the gate conductive material layer in the gate trench, including removing all the gate conductive material layers outside the gate trench and making the top surface of the gate conductive material layer in the gate trench flat, so as to ensure that the subsequent etching and filling processes of the second trench of the super junction structure are well implemented; since the trench gate and well region forming processes are placed before the super junction structure forming process, it is possible to avoid that the trench gate and well region forming processes with high requirements on the thermal process have an adverse effect on the super junction structure, so that the trench gate and the well region can adopt a higher thermal process according to their own needs, so that the quality of the trench gate and the well region is well guaranteed; at the same time, the present invention also controls the thermal process after the super junction structure, so as to ensure that the mutual diffusion of PN impurities in the super junction structure meets the requirements, so that the on-resistance of the super junction device meets the requirements. Since the mutual diffusion of PN impurities in the super junction structure can be well controlled, the step size of the super junction structure can be further reduced, thereby further reducing the on-resistance of the super junction device and improving the performance of the super junction device.

[0066] Although the present invention places the process of forming the trench gate and the well region before the process of forming the super junction structure, the present invention controls the flatness of the gate conductive material layer in the gate trench, which can ensure that the super junction structure can still be easily formed under the condition of forming the trench gate and the well region. Therefore, the present invention also has the advantage of not increasing the process complexity and cost.

[0067] Therefore, the present invention can independently set the thermal process of the trench gate, the thermal process of the well region and the thermal process of the super junction structure, so that the quality of the trench gate and the well region can be guaranteed while the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0069] Figure 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention;

[0070] Figure 2A-2I is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention;

[0071] Figure 3 It is a schematic diagram of the device structure of a super junction device formed by the method for manufacturing a super junction device according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0072] like Figure 1 FIG. 1 is a flow chart of a method for manufacturing a super junction device according to a first embodiment of the present invention; FIG. 2A to FIG. 2I , which is a schematic diagram of the device structure in each step of the method for manufacturing a super junction device according to the first embodiment of the present invention; the method for manufacturing a super junction device according to the first embodiment of the present invention comprises the following steps:

[0073] Step S101: Figure 2A As shown, a first epitaxial layer 102 doped with a first conductivity type is grown on the surface of a semiconductor substrate 101 .

[0074] In the first embodiment of the present invention, the material of the semiconductor substrate 101 includes silicon, the material of the first epitaxial layer 102 includes silicon, and the material of the second epitaxial layer 108 formed subsequently includes silicon.

[0075] Step S102: Figure 2C As shown, a plurality of trench gates are formed in the first epitaxial layer 102, and the trench gates include a gate oxide layer 104 formed on the inner surface of the gate trench 103 and a gate conductive material layer 105 filled in the gate trench 103; each trench gate is located in a subsequent corresponding first conductive type column; the gate conductive material layer 105 outside the gate trench 103 is removed, and the top surface of the gate conductive material layer 105 in the gate trench 103 is flat to ensure the implementation of the subsequent second trench 107 formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the trench gate formation process.

[0076] In the first embodiment of the present invention, the steps of forming the trench gate include:

[0077] like Figure 2A As shown, a first dielectric layer 201 is formed on the top surface of the first epitaxial layer 102. The material of the first dielectric layer 201 is generally silicon oxide.

[0078] like Figure 2AAs shown, photolithography defines the formation area of ​​the gate trench 103. The photolithography will form a photoresist pattern 202, and the open area of ​​the photoresist pattern 202 is the formation area of ​​the gate trench 103.

[0079] like Figure 2B As shown, the first dielectric layer 201 and the first epitaxial layer 102 in the formation region of the gate trench 103 are sequentially etched to form the gate trench 103. The photoresist pattern 202 will be removed before or after etching the first epitaxial layer 102 or consumed during the etching process.

[0080] like Figure 2C As shown, a thermal oxidation process is used to form the gate oxide layer 104. The thermal oxidation process has a high temperature thermal process. Since the thermal process corresponding to the thermal oxidation process is not affected by the super junction structure formed subsequently, the parameters of the thermal oxidation process can be set according to the need to form a gate oxide layer 104 with good quality, and finally the quality of the trench gate is guaranteed.

[0081] like Figure 2C As shown, a gate conductive material layer 105 is formed.

[0082] In the first embodiment of the present invention, the material of the gate conductive material layer 105 includes polysilicon.

[0083] like Figure 2C As shown, a first chemical mechanical polishing process is performed to planarize the gate conductive material layer 105 to remove the gate conductive material layer 105 on the top surface of the first epitaxial layer 102 outside the gate trench 103 and to planarize the top surface of the gate conductive material layer 105 in the gate trench 103 .

[0084] In the first embodiment of the present invention, after the first chemical mechanical polishing process, the top surface of the gate conductive material layer 105 in the gate trench 103 is located below the top surface of the first epitaxial layer 102 outside the gate trench 103. to facilitate the subsequent formation of the second trench 107, that is, to facilitate the subsequent process of the second trench 107 to achieve its goal.

[0085] In some embodiments, before or after the first chemical mechanical polishing process, the process further includes: performing a rapid thermal oxidation or performing a rapid thermal annealing.

[0086] Step S103: Figure 2DAs shown, a well region 106 doped with a second conductivity type is formed by photolithography and ion implantation and the well region 106 is annealed, each trench gate passes through the well region 106, and the well region 106 is pushed to a set position and ion implantation damage is repaired by adjusting the thermal process of annealing the well region 106. Photolithography and ion implantation means that the ion implantation area is first defined by photolithography process, and then ion implantation is performed.

[0087] In the first embodiment of the present invention, the maximum annealing temperature of the well region 106 is above 1100° C., and the annealing time is above 30 minutes.

[0088] Step S104: Figure 2E As shown, photolithography and etching are performed to form a plurality of second trenches 107 in the first epitaxial layer 102, and the first epitaxial layer 102 between the second trenches 107 serves as a first conductive type column. The depth of the second trench 107 is much greater than the depth of the gate trench 103. Photolithography and etching means that the etching area is first defined by photolithography, and then etching is performed.

[0089] In the first embodiment of the present invention, before performing the photolithography process of the second trench 107, the method further includes: forming a hard mask layer. The hard mask layer includes a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence.

[0090] In the etching process of the second trench 107 , the hard mask layer is etched first, and then the first epitaxial layer 102 is etched.

[0091] After the etching of the second trench 107 is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench 107 are removed, and then the subsequent growth of the second epitaxial layer 108 is performed.

[0092] Step S105: Figure 2E As shown, a second epitaxial layer 108 doped with a second conductive type is grown in the second trench 107, the second epitaxial layer 108 outside the second trench 107 is completely removed and the surface of the second epitaxial layer 108 in the second trench 107 is flattened, the second epitaxial layer 108 filled in the second trench 107 forms a second conductive type column, and the first conductive type columns and the second conductive type columns are alternately arranged to form a super junction structure.

[0093] The process then includes: planarizing the second epitaxial layer 108 by a second chemical mechanical polishing process, so as to completely remove the second epitaxial layer 108 outside the second trench 107 and make the surface of the second epitaxial layer 108 in the second trench 107 flat.

[0094] The first conductivity type pillar and the second conductivity type pillar of the super junction structure achieve charge matching at each longitudinal position.

[0095] In some embodiments, the second trench 107 has a side vertical structure, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is constant.

[0096] In some embodiments, the second trench 107 may have a side inclined structure that is wide at the top and narrow at the bottom, the doping concentration of the second epitaxial layer 108 is constant, and the doping concentration of the first epitaxial layer 102 is set according to the side inclination angle and the depth of the second trench 107. From the bottom to the top of the second trench 107, the doping concentration of the first epitaxial layer 102 at the corresponding depth gradually increases, so that the charge balance of adjacent first conductive type columns and corresponding second conductive type columns at each longitudinal position meets the requirements.

[0097] In some embodiments, the second trench 107 may have a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer 102 is constant, and the doping concentration of the second epitaxial layer 108 is set according to the side inclination angle and the depth of the second trench 107, and the doping concentration of the second epitaxial layer 108 at the corresponding depth gradually decreases from the bottom to the top of the second trench 107.

[0098] Step S106, after the super junction structure is completed, a subsequent front process is performed. In the subsequent front process, a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement.

[0099] In the first embodiment of the present invention, the setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

[0100] In the first embodiment of the present invention, the subsequent front surface process includes:

[0101] like Figure 2F As shown, photolithography and ion implantation are performed to form a source region 109 heavily doped with the first conductivity type, and the source region 109 and the side surface of the corresponding gate trench 103 are self-aligned.

[0102] The source region 109 is annealed and activated. The annealing of the source region 109 is performed in a furnace at a temperature below 950° C. or in a rapid thermal annealing.

[0103] like Figure 2G As shown, an interlayer film 110 is formed, and the interlayer film 110 is formed by stacking an undoped silicon dioxide layer and a BPSG layer.

[0104] like Figure 2G As shown, a contact hole opening 111 is formed through the interlayer film 110 . The contact hole opening 111 also penetrates into the first epitaxial layer 102 and passes through the surface source region 109 and contacts the well region 106 .

[0105] like Figure 2G As shown, a second conductive type heavily doped contact region 111 a , ie, a contact hole implantation (CT IMP) is formed at the bottom of the contact hole opening 111 .

[0106] like Figure 2H As shown, a metal layer is filled in the contact hole opening 111 to form a contact hole.

[0107] The metal layers forming the contact holes include:

[0108] A barrier layer 112 is formed. The barrier layer 112 is formed on the inner surface of the contact hole opening 111 .

[0109] In some embodiments, the material of the barrier layer 112 includes a Ti layer and a TiN layer stacked in sequence.

[0110] like Fig.2I As shown, a tungsten layer 113 is formed, and the tungsten layer 113 fills the contact hole opening 111 .

[0111] The barrier layer 112 and the tungsten layer 113 also extend onto the surface of the interlayer film 110 outside the contact hole opening 111 .

[0112] like Fig.2I As shown, a front metal layer 114 is formed. The front metal layer 114 is patterned and etched to form a source and a gate. The source region 109 and the well region 106 are connected to the source through corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer 105 at the trench gate lead-out end. In some embodiments, the material of the front metal layer 114 includes AlCu.

[0113] In the first embodiment of the present invention, the front metal layer 114 is formed on the surface of the tungsten layer 113. When the front metal layer 114 is patterned, the tungsten layer 113 and the barrier layer 112 are also removed in the removal area of ​​the front metal layer 114, and the tungsten layer 113 and the barrier layer 112 are also retained in the retention area of ​​the front metal layer 114. Fig.2I Only the source formation region is shown, so Fig.2I In the embodiment, the front metal layer 114 and the bottom tungsten layer 113 and barrier layer 112 are all retained.

[0114] Step S107: Fig.2I As shown, the back side process of the super junction device is completed.

[0115] In the first embodiment of the present invention, the back surface process includes:

[0116] The semiconductor substrate 101 is backside thinned.

[0117] A drain region heavily doped with the first conductivity type is formed. In the first embodiment of the present invention, the semiconductor substrate 101 is heavily doped with the first conductivity type, and the drain region is directly composed of the thinned semiconductor substrate 101. In this case, the drain region does not need to be further activated. In other embodiments, the drain region may be composed of a backside injection region heavily doped with the second conductivity type on the backside of the semiconductor substrate 101, and the drain region needs to be activated later.

[0118] A back metal layer 115 is formed and a drain electrode is formed by the back metal layer 115. In some embodiments, the back metal layer 115 includes TiNiAg.

[0119] In some embodiments, the process further includes performing a front passivation protection process, wherein the front passivation protection process further includes:

[0120] A dielectric protection layer (not shown) is formed; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer.

[0121] Photolithography and dry etching are performed to pattern the dielectric protection layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

[0122] In some embodiments, the front side passivation protection process further includes:

[0123] A polyimide layer (not shown) is formed.

[0124] Photolithography and development are performed to pattern the polyimide layer to open a lead-out region of the source electrode and a lead-out region of the gate electrode.

[0125] The polyimide layer is baked.

[0126] In some embodiments, the dielectric protection layer and the polyimide layer are stacked simultaneously.

[0127] In some embodiments, only the dielectric protection layer can be formed, and the polyimide layer can be omitted.

[0128] In some embodiments, the dielectric protection layer can be omitted and only the polyimide layer can be formed.

[0129] In the first embodiment of the present invention, the super junction device is an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the super junction device can also be a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0130] The first embodiment of the present invention makes a special arrangement for the process flow of the super junction device, mainly placing the formation process of the trench gate and the well region 106, which have high requirements on the thermal process, before the formation process of the super junction structure, and setting the flatness of the gate conductive material layer 105 in the gate trench 103, including removing all the gate conductive material layer 105 outside the gate trench 103 and making the top surface of the gate conductive material layer 105 in the gate trench 103 flat, so as to ensure that the subsequent etching and filling process of the second trench 107 of the super junction structure is well implemented; because the trench gate The formation process of the well region 106 is placed before the formation process of the super junction structure, so that the formation process of the trench gate and the well region 106 with high requirements for the thermal process can be avoided from having an adverse effect on the super junction structure. In this way, the trench gate and the well region 106 can adopt a high thermal process according to their own needs, so that the quality of the trench gate and the well region 106 is well guaranteed; at the same time, the first embodiment of the present invention also controls the thermal process after the super junction structure, which can ensure that the PN impurities of the super junction structure diffuse mutually to meet the requirements, so that the on-resistance of the super junction device can meet the requirements. Since the PN impurities of the super junction structure diffuse mutually to be well controlled, the stepping of the super junction structure can be further reduced, so that the on-resistance of the super junction device can be further reduced and the performance of the super junction device can be improved.

[0131] Although the first embodiment of the present invention places the process of forming the trench gate and the well region 106 before the process of forming the super junction structure, the first embodiment of the present invention controls the flatness of the gate conductive material layer 105 in the gate trench 103, which can ensure that the super junction structure can still be easily formed under the condition of forming the trench gate and the well region 106. Therefore, the first embodiment of the present invention also has the advantage of not increasing the process complexity and cost.

[0132] Therefore, the first embodiment of the present invention can independently set the thermal process of the trench gate, the thermal process of the well region 106 and the thermal process of the super junction structure, so that the quality of the trench gate and the well region 106 can be guaranteed while the mutual diffusion of PN impurities in the super junction structure can be effectively controlled, which is conducive to realizing a super junction structure with a smaller step and reducing the on-resistance of the super junction device, while not increasing the process complexity and cost.

[0133] like Figure 3 , which is a schematic diagram of the device structure of a super junction device formed by the manufacturing method of a super junction device according to the second embodiment of the present invention; the difference from the manufacturing method of a super junction device according to the first embodiment of the present invention is that in the manufacturing method of a super junction device according to the second embodiment of the present invention,

[0134] Before forming the front metal layer 114, the barrier layer 112 and the tungsten layer 113 outside the contact hole opening 111 are removed, and then the second barrier layer 112a and the front metal layer 114 are formed. In some embodiments, the material of the second barrier layer 112a includes a Ti layer and a TiN layer stacked in sequence.

[0135] In other embodiments, the second barrier layer 112 a may not be formed, and the front metal layer 114 may be directly formed.

[0136] In the first embodiment of the present invention, taking N-type MOSFET as an example, the thermal process after the formation of the P-type column can be greatly reduced, thereby further reducing the on-resistance of the device. The following takes a 600V trench gate super junction N-type MOSFET as an example, and further describes the first embodiment of the present invention in combination with corresponding parameters:

[0137] In step S101 , the semiconductor substrate 101 is a low-resistivity N-type substrate. For example, the resistivity of the semiconductor substrate 101 is less than 0.003 ohm.cm.

[0138] The thickness of the first epitaxial layer 102 is between 45 microns and 50 microns. The design of the resistivity of the first epitaxial layer 102 is related to the stepping of the subsequent P-type column, i.e., the second conductive type column, and the N-type column, i.e., the first conductive type column, and can be designed by simulation using computer-aided software. For example, the stepping of the PN column is set to 5 microns, and the resistivity is set to 0.5 ohm.cm.

[0139] In step S102 , the thickness of the first dielectric layer 201 is 0.5-2 microns.

[0140] The width and depth of the gate trench 103 can be set according to device performance. For example, the width of the gate trench 103 is set at 0.8-1.5 microns, and the depth is set at 2.5-4 microns.

[0141] The thickness of the gate oxide layer 104 is set to be 500 angstroms to 1500 angstroms;

[0142] The resistivity of the polysilicon of the gate conductive material layer 105 is generally set at about 10 ohm.cm to 30 ohm.cm. Before or after the polysilicon planarization of the gate conductive material layer 105 is completed, a high temperature RTO or high temperature RTA can be performed to improve the leakage between the gate and the drain of the product.

[0143] In step S103, the impurity of ion implantation in the well region 106 is generally B, the implantation energy is 100 KeV, and the implantation dose is designed according to the requirement of the device threshold voltage, for example, the implantation dose is 1E13 atoms / cm 2The ion implantation of the well region 106 can also be achieved by using two B implantations with different energies, so that different P-type wells, namely the well region 106, can be constructed, and the performance parameters of the device including the threshold voltage and EAS can be adjusted. After the ion implantation of the well region 106 is formed, a high-temperature annealing can be performed, such as annealing at 1100°C for 30 minutes or at a higher temperature. 1100°C for 30 minutes means a thermal annealing at a temperature of 1100°C for 30 minutes. This can push the P-type well to the set position on the one hand, and can also repair some damage caused during the ion implantation process.

[0144] In step S104, the thickness of the bottom silicon dioxide layer is The thickness of the middle silicon nitride layer is The thickness of the top silicon dioxide layer is 2 to 5 microns.

[0145] The width of the deep trench, namely the second trench 107, is 2.5 microns, the size of the N region between adjacent trenches, namely the spacing between the second trenches 107, is 2.5 microns, and the depth of the second trench 107 is 40-42 microns, which can be set according to the BVdss requirement of the device.

[0146] After etching the second trench 107, the top SIO2 and SIN of the hard mask, i.e., the top silicon dioxide layer and the middle silicon nitride layer, are completely removed, and the bottom SIO2, i.e., the bottom silicon dioxide layer, is kept as a protective layer on the Si surface. The second trench 107 is then completely filled by P-type epitaxial deposition, and then all the Si on the surface is removed by chemical mechanical polishing.

[0147] In step S106, Figure 2F As shown, the surface oxide film, that is, the bottom silicon dioxide layer, is partially removed, leaving about A thick film is used as a protective film for the subsequent N+ implantation, i.e., the implantation of the source region 109, or the surface oxide film is completely removed first and then RTO is used to deposit about The oxide film can be deposited by using a lower temperature process such as a thermal oxidation process at 800℃ to 950℃. The thermal oxide film is formed by the use of a high temperature or long-term thermal process to reduce the mutual diffusion of impurities between the P-type column and the N-type column. Then, the N+ region, i.e., the source region 109, is formed by photolithography and ion implantation. Here, N+ can be phosphorus implanted or arsenic As implanted, for example, As 60keV1~5E15 atoms / cm 2 ,As 60Kev 1~5E15 atoms / cm 2 Indicates that the implanted impurity is As, the implantation energy is 60keV, and the implantation dose is 1 atom / cm 2 ~5E15 atoms / cm 2After the ion implantation of the source region 109, an activation process at a temperature below 950°C, for example, 900°C for 30 min, may be performed, or RTA activation may be used.

[0148] In the step of forming the interlayer film 110, a 2000 angstrom undoped silicon dioxide layer is first deposited, and then a 8000-10000 angstrom BPSG layer is deposited.

[0149] In the step of forming the contact hole, the contact hole opening 111 can penetrate into the Si middle of the first epitaxial layer 102. arrive

[0150] The bottom of the contact hole opening 111 can be formed into a P-type region, namely the contact region 111a, by injecting B or BF2. For example, when the contact region 111a is injected with B, the injection energy can be 30-60 KeV, and the injection dose can be 5E14-1E15 / cm 2 This better ensures the ohmic contact between the metal in the subsequent contact hole opening 111 and the Si at the bottom of the contact hole opening 111 and reduces the contact resistance.

[0151] In the step of forming the barrier layer 112, the thickness of the Ti layer is The thickness of the TiN layer is

[0152] In the step of forming the tungsten layer 113, the process of metal tungsten filling the contact hole opening 111 is to grow along the sidewalls of the contact hole opening 111 and contact the central area of ​​the contact hole opening 111. The contacted portion may have some gaps or no gaps. The tungsten may completely fill the contact hole opening 111, or may not completely fill it, as long as the subsequent metal can cover the hole well.

[0153] In the step of forming the front metal layer 114, the deposition temperature of AlCu can be set to 250-450°C, and the thickness can be set to 2-6 microns. Then, by metal photolithography and dry etching, the metal AL-CU, i.e. AlCu, the W, i.e. tungsten layer 113, and the barrier layer 112 are all removed.

[0154] In addition, as an alternative, in the second embodiment of the present invention, it can be replaced by:

[0155] Before forming the front metal layer 114, the W on the silicon surface is completely removed by dry etching, and then the barrier layer 112 film under the W is also completely etched away, and then Ti / TiN / Alcu, i.e., the second barrier layer 112a and the front metal layer 114, are deposited. The thickness of the film can be set as follows: 5 microns, other settings are also possible, including 5 microns means the thickness of the Ti layer is The thickness of the TiN layer is The thickness of AlCu is 5 microns. Alternatively, after the W on the surface is completely etched, only AlCu is deposited, for example, 5 microns of AlCu is deposited. After the AlCu deposition is completed, metal photolithography and dry etching are performed.

[0156] In step S107 , the back side is thinned to reduce the thickness of the entire silicon wafer, ie, the overall thickness of the semiconductor substrate 101 and the first epitaxial layer 102 , to 60 to 200 microns.

[0157] The thickness of the TiNiAg of the back metal layer 115 can be Ti layer Ni layer Ag layer

[0158] The above process can realize the manufacture of a super junction MOSFET, which can form the separation of the active area, the transition area and the terminal area that bears the lateral voltage. The electrode in the source area is Fig.2I The gate is connected to the front metal layer 114. Fig.2I The trench gate is designed through layout, and the contact holes at the ends of the trench gate are connected and led out through metal. The drain is the back metal layer 115.

[0159] The MOSFET obtained based on the above manufacturing process can be further added with the following process, namely the front passivation protection process, to improve the performance and reliability of the product. The front passivation protection process includes:

[0160] A 1-2 micron dielectric protection layer can be deposited. The dielectric protection layer can be SiON, SiO2, SiN, a Si-rich silicon oxide film, or a combination of them. Then, through photolithography and dry etching, the gate electrode lead-out area and the source lead-out area are opened, while other areas including the terminal area that bears the lateral voltage are protected, which can improve the reliability of the product.

[0161] The front passivation protection process also includes:

[0162] A polyimide film can be deposited on the surface of the silicon wafer. The polyimide film can be formed on the surface of the dielectric protection layer, or the dielectric protection layer can be omitted. Then, through photolithography and development, the electrode lead-out area of ​​the gate is opened, the lead-out area of ​​the source is opened, and other areas including the terminal area that bears the lateral voltage are protected, which can improve the reliability of the product. After the photolithography and development are completed, it can be baked at 300-400°C (30-90 minutes). After baking, the thickness of the polyimide is 4-15 microns.

[0163] In the first embodiment of the present invention, in order to reduce the mutual diffusion of PN impurities after the formation of the P-type column, the temperature is limited to not exceed 950C during the thermal process after the formation of the P-type column for more than 10 minutes.

[0164] In the first embodiment of the present invention, the following further optimizations can be performed:

[0165] In step S101, the setting of the first epitaxial layer 102 can be set according to the inclination angle and depth of the trench, i.e., the second trench 107, in step S104. For example, if the trench is vertical, the resistivity of the first epitaxial layer 102 can be set to be constant, i.e., consistent from top to bottom. If the trench is an inclined trench with a large top and a small bottom, then the concentration of the N epitaxial layer, i.e., the first epitaxial layer 102, can be set to be high at the top and low at the bottom according to the degree of inclination, and the concentration in the middle can be linearly changed, that is, at each position perpendicular to the trench, when the impurity concentration of the p-type column, i.e., the second conductive type column, is a single concentration, the PN balance can be achieved, so that the source-drain breakdown voltage (BVdss) and Rdson of the device can be better balanced.

[0166] It can also be: the filling of the groove in step S105, that is, filling the second epitaxial layer 108 in the second groove 107, can be set in combination with the setting of the first epitaxial layer 102 and the inclination angle of the groove. For example, if the groove is vertical, then the resistivity of the first epitaxial layer 102 can be set to be constant, that is, it is consistent from top to bottom, then the impurity concentration of the P-type column can also be constant. If the resistivity of the first epitaxial layer 102 can be set to be constant, and the groove is an inclined groove with a large top and a small bottom, then according to the degree of inclination, in the P-type epitaxial deposition process, a high P-type impurity concentration can be set first for deposition, and the deposition concentration can be gradually reduced. Afterwards, the specific process conditions are determined by evaluating the window relationship between the BVdss of the device and the P-type impurity setting, with the goal of expanding the process window of the P-type epitaxial process.

[0167] Compared with the prior art, the first embodiment of the present invention adopts a new process flow without increasing the process complexity and cost. Before the formation of the trench of the P-type column, i.e., the second trench 107, the gate oxide process of the high-temperature process, i.e., the formation process of the gate oxide layer 104, and the push-well process for forming the P-type well are placed before the P-type column trench. After the P-type column is formed, the stability of the thermal process is set to below 950C, or only an extremely short-time activation process such as RTA is used.

[0168] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. A method for manufacturing a super junction device, characterized in that: The steps include: growing a first epitaxial layer doped with a first conductivity type on a surface of the semiconductor substrate; forming a plurality of trench gates in the first epitaxial layer, wherein the trench gates include a gate oxide layer formed on the inner surface of a gate trench and a gate conductive material layer filled in the gate trench; Each of the trench gates is located in a subsequent corresponding first conductive type column; the gate conductive material layer outside the gate trench is removed, and the top surface of the gate conductive material layer in the gate trench is flat, so as to ensure the implementation of the subsequent second trench formation process, and the quality of the trench gate is adjusted by adjusting the thermal process in the formation process of the trench gate; A well region doped with a second conductive type is formed by photolithography and ion implantation and the well region is annealed, each trench gate passes through the well region, and the well region is pushed to a set position and ion implantation damage is repaired by adjusting the thermal process of the annealing of the well region; Performing photolithography and etching to form a plurality of second trenches in the first epitaxial layer, wherein the first epitaxial layer between the second trenches serves as a first conductive type column; Growing a second epitaxial layer doped with a second conductivity type in the second trench, removing all of the second epitaxial layer outside the second trench and making the surface of the second epitaxial layer in the second trench flat, forming a second conductivity type column by the second epitaxial layer filled in the second trench, and forming a super junction structure by alternatingly arranging the first conductivity type columns and the second conductivity type columns; A subsequent front process after the super junction structure is completed, wherein a thermal process is set according to the requirement of controlling the mutual diffusion of PN impurities of the super junction structure so that the on-resistance of the super junction device meets the requirement; Complete the backside process of super junction devices.

2. The method for manufacturing a super junction device according to claim 1, wherein: A material of the semiconductor substrate includes silicon, a material of the first epitaxial layer includes silicon, and a material of the second epitaxial layer includes silicon.

3. The method for manufacturing a super junction device according to claim 1, wherein: The steps of forming the trench gate include: forming a first dielectric layer on a top surface of the first epitaxial layer; Photolithography defines a formation region of the gate trench; Sequentially etching the first dielectric layer and the first epitaxial layer in the formation region of the gate trench to form the gate trench; Forming the gate oxide layer by a thermal oxidation process; forming the gate conductive material layer; A first chemical mechanical polishing process is performed to planarize the gate conductive material layer to remove the gate conductive material layer above the top surface of the first epitaxial layer outside the gate trench and to planarize the top surface of the gate conductive material layer within the gate trench.

4. The method for manufacturing a super junction device according to claim 3, characterized in that: The gate conductive material layer is made of polysilicon.

5. The method for manufacturing a super junction device according to claim 3, characterized in that: Before or after the first chemical mechanical polishing process, the method further includes: Perform a rapid thermal oxidation or a rapid thermal annealing.

6. The method for manufacturing a super junction device according to claim 1, wherein: The maximum annealing temperature of the well region is above 1100° C. and the annealing time is above 30 minutes.

7. The method for manufacturing a super junction device according to claim 1, wherein: Before performing the photolithography process of the second trench, the method further includes: forming a hard mask layer; In the etching process of the second trench, the hard mask layer is etched first, and then the first epitaxial layer is etched.

8. The method for manufacturing a super junction device according to claim 7, characterized in that: The hard mask layer comprises a bottom silicon dioxide layer, a middle silicon nitride layer and a top silicon dioxide layer stacked in sequence; After the etching of the second trench is completed, the top silicon dioxide layer and the middle silicon nitride layer outside the second trench are removed, and then the second epitaxial layer is grown; Afterwards, a second chemical mechanical polishing process is used to planarize the second epitaxial layer, so as to completely remove the second epitaxial layer outside the second trench and make the surface of the second epitaxial layer in the second trench flat.

9. The method for manufacturing a super junction device according to claim 1, wherein: The subsequent front surface process includes: Performing photolithography and ion implantation to form a heavily doped source region of the first conductivity type, wherein the source region and the corresponding side of the gate trench are self-aligned; The source region is annealed and activated. The annealing of the source region is performed in a furnace tube at a temperature below 950° C. or in a rapid thermal annealing.

10. The method for manufacturing a super junction device according to claim 9, characterized in that: The subsequent front surface process also includes: forming an interlayer film, wherein the interlayer film is formed by stacking an undoped silicon dioxide layer and a BPSG layer; forming a contact hole opening through the interlayer film; forming a second conductive type heavily doped contact region at the bottom of the contact hole opening; Filling a metal layer in the contact hole opening to form a contact hole; A front metal layer is formed and the front metal layer is patterned and etched to form a source and a gate. The source region and the well region are connected to the source through the corresponding contact holes at the top, and the gate is connected to the contact hole at the top of the gate conductive material layer at the trench gate lead-out end.

11. The method for manufacturing a super junction device according to claim 10, characterized in that: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: Forming a dielectric protection layer; the dielectric protection layer is a combination of one or more of a SiON layer, a SiO2 layer, a SiN layer and a Si-rich silicon oxide layer; The dielectric protection layer is patterned by photolithography and dry etching to open the lead-out region of the source electrode and the lead-out region of the gate electrode.

12. The method for manufacturing a super junction device according to claim 10 or 11, characterized in that: The process also includes performing a front passivation protection process, wherein the front passivation protection process includes: forming a polyimide layer; Performing photolithography and development to pattern the polyimide layer to open the lead-out region of the source electrode and the lead-out region of the gate electrode; The polyimide layer is baked.

13. The method for manufacturing a super junction device according to claim 10, characterized in that: The metal layer forming the contact hole comprises: forming a barrier layer, wherein the barrier layer is formed on the inner surface of the contact hole opening; forming a tungsten layer, wherein the tungsten layer fills the contact hole opening; The barrier layer and the tungsten layer also extend onto the surface of the interlayer film outside the contact hole opening; The front metal layer is formed on the surface of the tungsten layer. When the front metal layer is patterned, the tungsten layer and the barrier layer are also removed in the front metal layer removal area, and the tungsten layer and the barrier layer are also retained in the front metal layer retention area. Alternatively, the barrier layer and the tungsten layer outside the contact hole opening are removed before forming the front metal layer, and then a second barrier layer and the front metal layer are formed or the front metal layer is directly formed.

14. The method for manufacturing a super junction device according to claim 1, characterized in that: The back side process includes: Performing backside thinning on the semiconductor substrate; A drain region heavily doped with a first conductivity type is formed; the semiconductor substrate is heavily doped with the first conductivity type, and the drain region is directly composed of the thinned semiconductor substrate; or, the drain region is composed of a backside injection region of the semiconductor substrate heavily doped with a second conductivity type on the backside; A back metal layer is formed and a drain electrode is formed from the back metal layer.

15. The method for manufacturing a super junction device according to claim 14, characterized in that: The setting of the thermal process corresponding to the subsequent front process includes: when the time of the thermal process exceeds 10 minutes, the corresponding temperature is limited to not more than 950°C.

16. The method for manufacturing a super junction device according to claim 1, characterized in that: The second trench has a side vertical structure, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is constant; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the second epitaxial layer is constant, the doping concentration of the first epitaxial layer is set according to the side inclination angle and the depth of the second trench, and the doping concentration of the first epitaxial layer at the corresponding depth gradually increases from the bottom to the top of the second trench, so that the charge balance of each adjacent first conductive type column and the corresponding second conductive type column at each longitudinal position meets the requirement; Alternatively, the second trench has a side inclined structure with a wide top and a narrow bottom, the doping concentration of the first epitaxial layer is constant, and the doping concentration of the second epitaxial layer is set according to the side inclination angle and depth of the second trench, and the doping concentration of the second epitaxial layer at the corresponding depth gradually decreases from the bottom to the top of the second trench.

17. The method for manufacturing a super junction device according to claim 3, characterized in that: After the first chemical mechanical polishing process, the process further includes making the top surface of the gate conductive material layer in the gate trench below the top surface of the first epitaxial layer outside the gate trench. to facilitate the subsequent formation of the second groove.

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