Passivation contact structure and passivation contact battery
By adding a metal thin film layer to the TOPCon solar cell, the energy loss problem caused by high light absorption and high doping concentration of the doped polysilicon layer is solved, and the photoelectric conversion efficiency and filling factor of the battery are improved.
Patent Information
- Application Number
- CN202420157794.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-23
- Publication Date
- 2025-01-10
- Estimated Expiration
- 2034-01-23
AI Technical Summary
In existing TOPCon solar cells, the high light absorption and high doping concentration of doped polysilicon thin films lead to energy loss and increase in Auger recombination, affecting battery performance.
Adding a metal thin film layer to the phosphorus-doped polysilicon layer will enhance the conductivity, thinning the doped polysilicon layer, reducing infrared light absorption, and improving the reflectivity of infrared light through the metal thin film layer.
It effectively reduces the absorption of infrared light by the doped polysilicon layer, reduces the risk of doped atoms diffusing to the substrate, and improves the photoelectric conversion efficiency and filling factor of the battery.
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Figure CN222339915U_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to solar cells, and more particularly to passivation contact technology. Background Art
[0002] The production of tunneling oxide passivated contact solar cells, commonly known as TOPCon cells, is mainly to combine an ultra-thin tunneling oxide layer with a heavily doped polysilicon layer and deposit it on the surface of a silicon substrate. The interface recombination between the silicon substrate and the polysilicon layer can be reduced by the chemical passivation of silicon oxide. In this passivation contact structure, the majority carriers are transported by tunneling, while the minority carriers cannot pass through due to the potential barrier and the field effect of polysilicon, so this structure is called a passivation contact structure. The traditional passivation contact structure of TOPCon cells is generally to grow an ultra-thin SiO2 layer with a thickness of about 1-5nm on an n-type silicon substrate to passivate the surface of the silicon substrate; and then grow a phosphorus-doped polysilicon layer on the ultra-thin oxide layer to achieve selective carrier transmission.
[0003] During the operation of the TOPCon cell, most of the visible light is absorbed after the incident light passes through the PN junction, and the remaining infrared light will be reflected by the anti-reflection layer and return to the PN junction after passing through the doped polysilicon film. However, the doped polysilicon film has a higher light absorption, resulting in energy loss of long-wave infrared light; in addition, the conductivity of the polysilicon film depends on the doping concentration. A relatively high doping concentration is required for better conductivity. At a high doping concentration, the diffusion capacity of the doped atoms is stronger, and they are easily pushed to the substrate during the high-temperature annealing step, resulting in an increase in Auger recombination and thus reducing the performance of the cell. This in turn forces the thickness of the doped polysilicon layer to be very thick, further leading to energy loss. Utility Model Content
[0004] The embodiments of the present application provide a passivation contact structure and a preparation method, and a passivation contact cell to solve the technical problem that doped polysilicon thin films have high light absorption and cause energy loss.
[0005] In a first aspect, an embodiment of the present application provides a passivation contact structure, the passivation contact structure comprising:
[0006] An n-type silicon wafer, one side of which is a polished surface;
[0007] A tunneling oxide layer, a phosphorus-doped polysilicon layer, and a metal film layer are sequentially stacked on the polishing surface.
[0008] In some embodiments of the present application, the thickness of the tunnel oxide layer is 1 to 10 nm.
[0009] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer is 10 to 120 nm; and / or,
[0010] The phosphorus atom doping concentration of the phosphorus-doped polysilicon layer is not higher than 2e20.
[0011] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer is 90-100 nm.
[0012] In some embodiments of the present application, the material of the metal film layer is one of silver, copper and aluminum; and / or,
[0013] The thickness of the metal film layer is 10-100 nm.
[0014] In a second aspect, an embodiment of the present application provides a method for preparing a passivation contact structure, the method for preparing a passivation contact structure comprising the following steps:
[0015] Providing an n-type silicon wafer having a polished surface;
[0016] A tunneling oxide layer, a phosphorus-doped polysilicon layer and a metal film layer are sequentially prepared on the polishing surface.
[0017] In some embodiments of the present application, the material of the metal film layer is one of silver, copper and aluminum; and / or,
[0018] The thickness of the tunnel oxide layer is 1 to 10 nm; and / or,
[0019] The thickness of the phosphorus-doped polysilicon layer is 10 to 120 nm; and / or,
[0020] The thickness of the metal film layer is 10-100 nm.
[0021] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer is 90-100 nm.
[0022] In some embodiments of the present application, the metal film layer is prepared by an evaporation process or an atomic deposition process.
[0023] In a third aspect, an embodiment of the present application provides a passivated contact battery, the passivated contact battery comprising:
[0024] The passivation contact structure described in any embodiment of the first aspect, or the passivation contact structure prepared by the method described in any embodiment of the second aspect, wherein the other side of the n-type silicon wafer is a velvet surface;
[0025] A first anti-reflection layer disposed on the metal thin film layer;
[0026] A first electrode embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer;
[0027] A boron-doped oxide layer, a passivation layer and a second anti-reflection layer are sequentially arranged on the suede surface;
[0028] A second electrode is embedded in the second anti-reflection layer, the passivation layer and the boron-doped oxide layer and forms an electrical contact with the boron-doped oxide layer and the n-type silicon wafer.
[0029] The above technical solution provided by the embodiment of the present application has the following advantages compared with the prior art:
[0030] The passivation contact structure provided in the embodiment of the present application adds a metal film layer on the phosphorus-doped polysilicon layer. The metal film layer can enhance the conductivity of the phosphorus-doped polysilicon layer on the one hand, so that the phosphorus-doped polysilicon layer does not need to maintain a high doping concentration, thereby reducing the risk of doped atoms being pushed into the n-type silicon wafer, which allows the thickness of the doped polysilicon layer to be correspondingly thinned, thereby reducing its absorption of infrared light; at the same time, the metal film layer has a high reflectivity to infrared light, which further increases the absorption and utilization of infrared light. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0033] Figure 1 A schematic structural diagram of a passivation contact structure provided in an embodiment of the present application;
[0034] Figure 2 A schematic diagram of the structure of a passivated contact battery provided in an embodiment of the present application. DETAILED DESCRIPTION
[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.
[0036] Unless otherwise specified, the terms used herein should be understood as commonly used in the art. Therefore, unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art to which this application belongs. In the event of a conflict, this specification takes precedence.
[0037] Unless otherwise specified, various raw materials, reagents, instruments and equipment used in this application can be purchased from the market or prepared by existing methods.
[0038] The English abbreviations used in this application have the following meanings:
[0039] TOPCon: Tunnel Oxide Passivated Contact solar cell (TOPcon)
[0040] PECVD: Plasma Enhanced Chemical Vapor Deposition
[0041] LPCVD: Low Pressure Chemical Vapor Deposition
[0042] ALD: atomic layer deposition
[0043] The existing TOPCon cells have technical problems such as high light absorption of doped polysilicon thin film and high doping concentration which easily leads to increased Auger recombination.
[0044] The technical solution provided by the embodiments of the present application is to solve the above technical problems, and the overall idea is as follows:
[0045] In a first aspect, an embodiment of the present application provides a passivation contact structure, the passivation contact structure comprising:
[0046] An n-type silicon wafer 1, one side of the n-type silicon wafer 1 being a polished surface;
[0047] A tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, and a metal film layer 4 are sequentially stacked on the polishing surface.
[0048] Those skilled in the art will appreciate that the tunneling oxide layer 2 is a conventional structure in the art. The function of the tunneling oxide layer 2 is to reduce the interface state density between the n-type silicon wafer 1 substrate and the doped polysilicon layer through chemical passivation. The majority carrier concentration is much higher than the minority carrier concentration, which reduces the probability of electron-hole recombination while increasing the resistivity to form selective contact for majority carriers. In the tunneling oxide layer 2, electrons pass through the oxide layer from the metal surface to the metal surface on the other side. This phenomenon only occurs in very thin oxide layers, usually less than a few nanometers. In this case, the wavelength of the electrons is comparable to the thickness of the tunneling oxide layer 2, so the electrons can pass through the tunneling oxide layer 2.
[0049] Those skilled in the art can understand that the phosphorus-doped polysilicon layer 3 is a conventional structure in the art. The phosphorus-doped polysilicon layer 3 functions to form a passivation contact together with the tunneling oxide layer 2.
[0050] Doped polysilicon films have higher light absorption, resulting in energy loss of long-wave infrared light; at the same time, the conductivity of polysilicon films depends on the doping concentration. Better conductivity requires a relatively high doping concentration, and high doping concentrations easily push doped ions into the substrate during the high-temperature annealing step, causing an increase in Auger recombination and thus reducing battery performance.
[0051] The present application adds a metal film layer 4 on the phosphorus-doped polysilicon layer 3. The metal film layer 4 can enhance the conductivity of the phosphorus-doped polysilicon layer 3, so that the phosphorus-doped polysilicon layer 3 does not need to maintain a high doping concentration, thereby reducing the risk of doped atoms being pushed into the n-type silicon wafer 1. This allows the thickness of the doped polysilicon layer to be correspondingly thinned, thereby reducing its absorption of infrared light. At the same time, the metal film layer 4 has a high reflectivity to infrared light, which further increases the absorption and utilization of infrared light.
[0052] In some embodiments of the present application, the thickness of the tunnel oxide layer 2 is 1-10 nm.
[0053] It is easy to understand that the thickness of the tunnel oxide layer 2 is a conventional parameter in the art. As an example, the thickness of the tunnel oxide layer 2 can be 1 nm, 3 nm, 5 nm, 8 nm, or 10 nm.
[0054] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer 3 is 10 to 120 nm; and / or,
[0055] The phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is not higher than 2e20.
[0056] It is easy to understand that in the art, the thickness of the phosphorus-doped polysilicon layer 3 is not less than 150 nm in most cases, and is usually about 200 nm. The present application can reduce the thickness of the phosphorus-doped polysilicon layer 3, and the thickness of the phosphorus-doped polysilicon layer 3 can be, for example, 10 nm, 30 nm, 50 nm, 80 nm, 100 nm, or 120 nm.
[0057] The phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 may be, for example, 2e20, 2e15, 8e10, 5e10, or 2e10.
[0058] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer 3 is 90-100 nm.
[0059] The beneficial effect of the thickness of the phosphorus-doped polysilicon layer 3 being 90-100 nm is that it is easy to realize in terms of process, has good carrier transport capability, and is relatively thin. As an example, the thickness of the phosphorus-doped polysilicon layer 3 can be 90 nm, 92 nm, 95 nm, 97 nm, or 100 nm.
[0060] In some embodiments of the present application, the material of the metal film layer 4 is one of silver, copper and aluminum; and / or,
[0061] The thickness of the metal film layer 4 is 10-100 nm.
[0062] It is easy to understand that silver, copper and aluminum all have good electrical conductivity and high thermal reflectivity to infrared light.
[0063] The thickness of the metal thin film layer 4 can be, for example, 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, or 100 nm.
[0064] In a second aspect, an embodiment of the present application provides a method for preparing a passivation contact structure, the method for preparing a passivation contact structure comprising the following steps:
[0065] S1: providing an n-type silicon wafer 1 having a polished surface;
[0066] S2: preparing a tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, and a metal film layer 4 in sequence on the polished surface.
[0067] Those skilled in the art can understand that the polished surface is generally obtained by performing a polishing process on the n-type silicon wafer 1 , and the polishing process is a conventional process in the art.
[0068] Those skilled in the art will appreciate that it is a conventional technical solution in the art to prepare the tunnel oxide layer 2. As an example, the tunnel oxide layer 2 can be prepared by PECVD, LPCVD, etc., and the deposition atmosphere can include N2O, SiH4, oxygen, etc.
[0069] Those skilled in the art can understand that preparing the phosphorus-doped polysilicon layer 3 is a conventional technical solution in the art, and is usually obtained by depositing a polysilicon layer and then performing a phosphorus-doping treatment.
[0070] In some embodiments of the present application, the material of the metal film layer 4 is one of silver, copper and aluminum; and / or,
[0071] The thickness of the tunnel oxide layer 2 is 1-10 nm; and / or,
[0072] The thickness of the phosphorus-doped polysilicon layer 3 is 10 to 120 nm; and / or,
[0073] The thickness of the metal film layer 4 is 10-100 nm.
[0074] In some embodiments of the present application, the thickness of the phosphorus-doped polysilicon layer 3 is 90-100 nm.
[0075] In some embodiments of the present application, the metal film layer 4 is prepared by an evaporation process or an atomic deposition process.
[0076] In a third aspect, an embodiment of the present application provides a passivated contact battery, the passivated contact battery comprising:
[0077] The passivation contact structure described in any embodiment of the first aspect, or the passivation contact structure prepared by the method described in any embodiment of the second aspect, wherein the other side of the n-type silicon wafer 1 is a velvet surface;
[0078] A first anti-reflection layer 5 disposed on the metal thin film layer 4;
[0079] A first electrode 6 embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer 3;
[0080] A boron-doped oxide layer 7, a passivation layer 8 and a second anti-reflection layer 9 are sequentially arranged on the suede surface;
[0081] A second electrode 10 is embedded in the second anti-reflection layer 9 , the passivation layer 8 and the boron-doped oxide layer 7 and forms an electrical contact between the boron-doped oxide layer 7 and the n-type silicon wafer 1 .
[0082] Those skilled in the art can understand that the velvet surface is formed by texturing, which is a conventional technical means in the art and can form special morphologies on the surface of silicon wafers. For example, a pyramid-like morphology can be obtained by alkali texturing, and a wormhole-like morphology can be obtained by acid texturing. Texturing can improve the light trapping effect of silicon wafers. In the field of Topcon batteries, alkali texturing is generally used.
[0083] The boron-doped oxide layer 7 is a conventional structure in the art, and is usually obtained by subjecting a silicon wafer to a high-temperature boron diffusion process, which is usually carried out in an oxygen atmosphere containing at least one of BCl3 and BBr3.
[0084] Those skilled in the art will appreciate that the passivation layer 8 is a conventional structure in the art. The passivation layer 8 may also be referred to as an insulating layer, and may be made of silicon nitride, aluminum oxide, titanium oxide, or silicon oxide, or any combination thereof. The passivation film may be deposited by vapor deposition, sputtering, ALD, or other methods.
[0085] Those skilled in the art can understand that, for the first anti-reflection layer 5 and the second anti-reflection layer 9 of the present application, the anti-reflection layer is a conventional structure in the art. The anti-reflection layer can be made of silicon nitride, aluminum oxide, titanium oxide or silicon oxide, or any combination thereof. As an example, the anti-reflection film can be prepared by a PECVD method.
[0086] The first electrode 6 and the second electrode 10 described in the present application are both metal electrodes in solar cells, also known as grid lines. Those skilled in the art will appreciate that metal electrodes are conventional structures in the art, and the material of the metal electrode is generally formed by a conductive electrode slurry, and the electrode slurry can, for example, use a metallized silver paste applied to p-type crystalline silicon cells on the market, such as a silver paste containing Pb-Te-O glass powder. As an exemplary preparation method, the electrode slurry can be applied to the silicon wafer by screen printing in the desired patterned form, and after drying, sintering and other post-processing can be performed. The conductive layer formed by the electrode slurry forms an electrical contact with the silicon wafer to form an electrode.
[0087] The present application will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are intended only to illustrate the present application and are not intended to limit the scope of the present application. The experimental methods for which specific conditions are not specified in the following examples are usually measured according to industry standards. If there is no corresponding industry standard, then the conditions recommended by the manufacturer are followed.
[0088] Example 1
[0089] This embodiment provides a passivation contact battery, the passivation contact battery comprising:
[0090] An n-type silicon wafer 1, wherein one side of the n-type silicon wafer 1 is a polished side and the other side is a velvet side;
[0091] A tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, and a metal film layer 4 are sequentially stacked on the polishing surface;
[0092] A first anti-reflection layer 5 disposed on the metal thin film layer 4;
[0093] A first electrode 6 embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer 3;
[0094] A boron-doped oxide layer 7, a passivation layer 8 and a second anti-reflection layer 9 are sequentially arranged on the suede surface;
[0095] A second electrode 10 is embedded in the second anti-reflection layer 9 , the passivation layer 8 and the boron-doped oxide layer 7 and forms an electrical contact between the boron-doped oxide layer 7 and the n-type silicon wafer 1 .
[0096] Among them, the thickness of the tunneling oxide layer 2 is 10nm, the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is 2e20, the thickness of the phosphorus-doped polysilicon layer 3 is 90nm, the material of the metal film layer 4 is aluminum, and the thickness of the metal film layer 4 is 20nm.
[0097] Example 2
[0098] The difference between this embodiment and embodiment 1 is that the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is 2e10, and the thickness of the phosphorus-doped polysilicon layer 3 is 95 nm. The details are as follows:
[0099] This embodiment provides a passivation contact battery, the passivation contact battery comprising:
[0100] An n-type silicon wafer 1, wherein one side of the n-type silicon wafer 1 is a polished side and the other side is a velvet side;
[0101] A tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, and a metal film layer 4 are sequentially stacked on the polishing surface;
[0102] A first anti-reflection layer 5 disposed on the metal thin film layer 4;
[0103] A first electrode 6 embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer 3;
[0104] A boron-doped oxide layer 7, a passivation layer 8 and a second anti-reflection layer 9 are sequentially arranged on the suede surface;
[0105] A second electrode 10 is embedded in the second anti-reflection layer 9 , the passivation layer 8 and the boron-doped oxide layer 7 and forms an electrical contact between the boron-doped oxide layer 7 and the n-type silicon wafer 1 .
[0106] Among them, the thickness of the tunneling oxide layer 2 is 10nm, the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is 2e10, the thickness of the phosphorus-doped polysilicon layer 3 is 95nm, the material of the metal film layer 4 is aluminum, and the thickness of the metal film layer 4 is 20nm.
[0107] Example 3
[0108] The difference between this embodiment and embodiment 1 is that the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is 2e12, and the thickness of the phosphorus-doped polysilicon layer 3 is 100 nm. The details are as follows:
[0109] This embodiment provides a passivation contact battery, the passivation contact battery comprising:
[0110] An n-type silicon wafer 1, wherein one side of the n-type silicon wafer 1 is a polished side and the other side is a velvet side;
[0111] A tunneling oxide layer 2, a phosphorus-doped polysilicon layer 3, and a metal film layer 4 are sequentially stacked on the polishing surface;
[0112] A first anti-reflection layer 5 disposed on the metal thin film layer 4;
[0113] A first electrode 6 embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer 3;
[0114] A boron-doped oxide layer 7, a passivation layer 8 and a second anti-reflection layer 9 are sequentially arranged on the suede surface;
[0115] A second electrode 10 is embedded in the second anti-reflection layer 9 , the passivation layer 8 and the boron-doped oxide layer 7 and forms an electrical contact between the boron-doped oxide layer 7 and the n-type silicon wafer 1 .
[0116] Among them, the thickness of the tunneling oxide layer 2 is 10nm, the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer 3 is 2e12, the thickness of the phosphorus-doped polysilicon layer 3 is 100nm, the material of the metal film layer 4 is aluminum, and the thickness of the metal film layer 4 is 20nm.
[0117] Comparative Example
[0118] The only difference between this comparative example and Example 1 is that this comparative example does not include a metal thin film layer, and the thickness of the phosphorus-doped polysilicon layer is 200 nm.
[0119] This comparative example provides a passivated contact cell, the passivated contact cell comprising:
[0120] An n-type silicon wafer, wherein one side of the n-type silicon wafer is a polished surface and the other side is a velvet surface;
[0121] A tunneling oxide layer, a phosphorus-doped polysilicon layer, and a metal film layer are sequentially stacked on the polishing surface;
[0122] A first anti-reflection layer disposed on the metal thin film layer;
[0123] A first electrode embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer;
[0124] A boron-doped oxide layer, a passivation layer and a second anti-reflection layer are sequentially arranged on the suede surface;
[0125] A second electrode is embedded in the second anti-reflection layer, the passivation layer and the boron-doped oxide layer and forms an electrical contact between the boron-doped oxide layer 7 and the n-type silicon wafer.
[0126] The thickness of the tunnel oxide layer is 10 nm, the phosphorus atom doping concentration of the phosphorus-doped polysilicon layer is 2e20, and the thickness of the phosphorus-doped polysilicon layer is 90 nm.
[0127] Related experiments and effect data:
[0128] After testing with an IV tester, the photoelectric conversion efficiency and FF (Fill Factor) of the passivated contact cells provided in Examples 1 to 3 and the comparative example are shown in Table 1:
[0129] Example 1 Example 2 Example 3 Comparative Example Photoelectric conversion efficiency (%) 25.8 25.7 25.7 25.5 FF(%) 85.6 85.5 85.5 85
[0130] Table 1
[0131] As can be seen from Table 1, the photoelectric conversion efficiency and FF of Examples 1 to 3 are improved compared with the comparative example, which shows that the performance of the solar cell can be effectively improved by thinning the phosphorus-doped polysilicon layer and adding a metal film layer in the examples.
[0132] Various embodiments of the present application may be presented in the form of a range; it should be understood that the description in the form of a range is only for convenience and brevity, and should not be understood as a rigid limitation on the scope of the present application; therefore, the range description should be considered to have specifically disclosed all possible sub-ranges and single numerical values within the range. For example, the range description from 1 to 6 should be considered to have specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., as well as single numbers within the range, such as 1, 2, 3, 4, 5 and 6, which apply regardless of the range. In addition, whenever a numerical range is indicated herein, it is meant to include any cited number (fractional or integer) within the indicated range.
[0133] In the present application, in the absence of any contrary description, the directional words used, such as "upper" and "lower", are specifically the directions of the drawings in the accompanying drawings. In addition, in the description of the present application specification, the terms "including", "comprising", etc. refer to "including but not limited to". Moreover, the terms "including", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of further restrictions, the elements defined by the sentence "including..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. In this article, "and / or" describes the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B, which can represent: A exists alone, A and B exist at the same time, and B exists alone. For the association relationship of more than three associated objects described by "and / or", it means that any one of these three associated objects can exist alone, or any at least two of them exist at the same time. For example, for A, and / or B, and / or C, it can be represented that any one of A, B, and C exists alone, or any two of them exist at the same time, or three of them exist at the same time. In this article, "at least one" refers to one or more, and "multiple" refers to two or more. "At least one", "the following at least one (individual)" or similar expressions refer to any combination of these items, including any combination of single (individual) or plural (individual). For example, "at least one (individual) of a, b, or c", or "at least one (individual) of a, b, and c", can all represent: a, b, c, ab (i.e. a and b), ac, bc, or abc, wherein a, b, and c can be single or multiple, respectively.
[0134] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.
Claims
1. A passivation contact structure, characterized in that: The passivation contact structure comprises: An n-type silicon wafer, one side of which is a polished surface; A tunneling oxide layer, a phosphorus-doped polysilicon layer, and a metal film layer are sequentially stacked on the polishing surface.
2. The passivation contact structure according to claim 1, characterized in that: The thickness of the tunnel oxide layer is 1-10 nm.
3. The passivation contact structure according to claim 1, characterized in that: The thickness of the phosphorus-doped polysilicon layer is 10 to 120 nm; and / or, The phosphorus atom doping concentration of the phosphorus-doped polysilicon layer is not higher than 2e20.
4. The passivation contact structure according to claim 3, characterized in that: The thickness of the phosphorus-doped polysilicon layer is 90-100 nm.
5. The passivation contact structure according to claim 1, characterized in that: The material of the metal film layer is one of silver, copper and aluminum; and / or, The thickness of the metal film layer is 10-100 nm.
6. A passivated contact battery, characterized in that: The passivated contact cell comprises: The passivation contact structure according to any one of claims 1 to 5, wherein the other side of the n-type silicon wafer is a velvet surface; A first anti-reflection layer disposed on the metal thin film layer; A first electrode embedded in the passivation contact structure and forming an electrical contact with the phosphorus-doped polysilicon layer; A boron-doped oxide layer, a passivation layer and a second anti-reflection layer are sequentially arranged on the suede surface; A second electrode is embedded in the second anti-reflection layer, the passivation layer and the boron-doped oxide layer and forms an electrical contact with the boron-doped oxide layer and the n-type silicon wafer.