Battery management system and electronic equipment

Abstract

The utility model discloses a battery management system and electronic equipment, and the system comprises a main control module; a selection module; each slave control module comprises an input unit, an output unit and a communication unit, and the input unit of the first slave control module in the N slave control modules is connected with the master control module so as to receive an addressing enable signal sent by the master control module; the input unit of the mth slave control module is connected with the output unit of the (m-1) th slave control module and the master control module through a selection module so as to receive an addressing enable signal sent by the (m-1) th slave control module or the master control module through the selection module, and the communication units of the N slave control modules are connected with the master control module; wherein N and m are integers, N > = 2, and 2 < = m < = N. In this way, the addressing efficiency of the slave control module can be improved.

Description

Technical Field

[0001] The present application relates to the field of energy storage technology, and in particular to a battery management system and an electronic device. Background Art

[0002] The battery management system (BMS) is mainly used to monitor the parameter information (temperature, voltage, current, state of charge, etc.) of the energy storage equipment, and to manage and control the status of the energy storage equipment.

[0003] Since energy storage equipment generally includes multiple battery clusters, and each battery cluster includes multiple battery cells, multiple slave controllers are generally used to monitor multiple battery clusters separately to realize the voltage and temperature collection and balancing control functions of the cluster battery cells. Then a master controller is used for overall control, which is responsible for collecting and processing the signals collected by each slave controller, estimating the battery status based on the collected signals, and realizing charging and discharging control and logical operations for each battery cluster.

[0004] When there are many slave controls, the master control needs to address the slave controls for the convenience of managing them. How to address them efficiently has become a problem that needs to be solved urgently. Utility Model Content

[0005] To solve the above problems, the present application provides a battery management system and an electronic device, which can improve the addressing efficiency of the slave control module.

[0006] On the one hand, the present application provides a battery management system, which includes: a master control module; a selection module; N slave control modules, the slave control modules include an input unit, an output unit and a communication unit, the input unit of the first slave control module among the N slave control modules is connected to the master control module to receive an addressing enable signal sent by the master control module, the input unit of the mth slave control module is connected to the output unit of the m-1th slave control module and the master control module through a selection module to receive the addressing enable signal sent by the m-1th slave control module or the master control module through the selection module, and the communication units of the N slave control modules are connected to the master control module; wherein N and m are integers, N≥2, 2≤m≤N.

[0007] In one embodiment, the first input end of the selection module is connected to the output unit of the m-1th slave control module, the second input end of the selection module is connected to the master control module, the output end of the selection module is connected to the input unit of the mth slave control module, and the control end of the selection module is connected to the master control module to receive an addressing mode signal sent by the master control module; wherein the selection module is configured to, according to the addressing mode signal, turn on the output unit of the m-1th slave control module and the input unit of the mth slave control module for automatic addressing, or turn on the input unit of the master control module and the mth slave control module for manual addressing.

[0008] In one embodiment, the selection module includes: a first AND logic gate, wherein the first input end of the first AND logic gate serves as the first input end of the selection module; a second AND logic gate, wherein the first input end of the second AND logic gate serves as the second input end of the selection module, and the second input end of the second AND logic gate serves as the control end of the selection module; a non-logic gate, wherein the input end of the non-logic gate is connected to the second input end of the second AND logic gate, and the output end of the non-logic gate is connected to the second input end of the first AND logic gate; and an OR logic gate, wherein the first input end of the OR logic gate is connected to the output end of the first AND logic gate, and the second input end of the OR logic gate is connected to the output end of the second AND logic gate, and the output end of the OR logic gate serves as the output end of the selection module.

[0009] In one embodiment, the slave control module also includes a control unit connected to the input unit, the output unit and the communication unit, and the control unit is configured to receive an addressing enable signal through the input unit, receive addressing data through the communication unit, and send an addressing enable signal through the output unit.

[0010] In one embodiment, the output unit includes: a first switch tube, a first end of the first switch tube is configured to input a driving signal, and a second end of the first switch tube is connected to a selection module to output an addressing enable signal; a second switch tube, a first end of the second switch tube is connected to a control end of the first switch tube, a second end of the second switch tube is grounded, and the control end of the second switch tube is connected to a control unit and receives an enable control signal.

[0011] In one embodiment, the output unit also includes: a first resistor, a first end of the first resistor is configured to input a driving signal, and a second end of the first resistor is connected to a first end of the first switch tube; a second resistor, a first end of the second resistor is connected to the first end of the first resistor, and a second end of the second resistor is connected to a control end of the first switch tube; a third resistor, a first end of the third resistor is connected to the control end of the first switch tube, and a second end of the third resistor is connected to the first end of the second switch tube; a fourth resistor, a first end of the fourth resistor is connected to the control unit and receives an enable control signal, and a second end of the fourth resistor is connected to the control end of the second switch tube; a fifth resistor, a first end of the fifth resistor is connected to the control end of the second switch tube, and a second end of the fifth resistor is grounded.

[0012] In one embodiment, the output unit further includes: a sixth resistor, a first end of the sixth resistor is connected to the second end of the first switch tube, and a second end of the sixth resistor is grounded; a first capacitor, a first end of the first capacitor is connected to the second end of the first switch tube, and a second end of the first capacitor is grounded.

[0013] In one embodiment, the input unit includes: a seventh resistor, a first end of the seventh resistor is configured to input a power supply voltage signal; a third switch tube, a first end of the third switch tube is connected to the second end of the seventh resistor and the control unit to output an addressing trigger signal, a second end of the third switch tube is grounded, and a control end of the third switch tube is connected to the selection module to receive an addressing enable signal.

[0014] In one embodiment, the input unit also includes: an eighth resistor, a first end of the eighth resistor is connected to the control end of the third switch tube, and a second end of the eighth resistor is connected to the selection module to receive an addressing enable signal; a ninth resistor, a first end of the ninth resistor is connected to the control end of the third switch tube, and a second end of the ninth resistor is grounded; a second capacitor, a first end of the second capacitor is connected to the second end of the eighth resistor, and a second end of the second capacitor is grounded; a third capacitor, a first end of the third capacitor is connected to the first end of the third switch tube, and a second end of the third capacitor is grounded.

[0015] Another aspect of the present application provides an electronic device, which includes the battery management system as described above.

[0016] The battery management system provided by the present application includes: a master control module; a selection module; N slave control modules, the slave control modules include an input unit, an output unit and a communication unit, the input unit of the first slave control module among the N slave control modules is connected to the master control module to receive the addressing enable signal sent by the master control module, the input unit of the mth slave control module is connected to the output unit of the m-1th slave control module and the master control module through a selection module to receive the addressing enable signal sent by the m-1th slave control module or the master control module through the selection module, and the communication units of the N slave control modules are connected to the master control module; wherein N and m are integers, N≥2, 2≤m≤N. In the above manner, by setting a selection module between multiple slave control modules, different addressing modes can be freely switched, that is, automatic addressing or manual addressing can be realized. On the one hand, the diversification of addressing modes provided is conducive to the operability of the battery management system, and on the other hand, it can be selected according to different application scenarios. When a slave control module fails, the slave control module is addressed separately without addressing all slave control modules in sequence, thereby improving the addressing efficiency of the slave control module. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 It is a structural schematic diagram of an embodiment of a battery management system provided by the present application;

[0019] Figure 2 is a schematic structural diagram of a slave control module 20 in one embodiment;

[0020] Figure 3 is a schematic diagram of the structure of the selection module 30 in one embodiment;

[0021] Figure 4 It is a flowchart of an embodiment of an addressing method for a battery management system provided by the present application;

[0022] Figure 5 is a schematic diagram of the structure of the input unit 21 in one embodiment;

[0023] Figure 6 is a schematic diagram of the structure of the output unit 22 in one embodiment;

[0024] Figure 7 It is a structural schematic diagram of an embodiment of an electronic device provided by the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0026] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0027] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0028] The use of "suitable for" or "configured to" in this application is meant to be open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is meant to be open and inclusive, because the process, step, calculation or other action "based on" one or more stated conditions or values ​​can be based on additional conditions or values ​​beyond the stated values ​​in practice.

[0029] In this application, the word "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described in this application as "exemplary" is not necessarily to be construed as being preferred or advantageous over other embodiments. The following description is given to enable any technician in the field to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes will not be elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in the present application.

[0030] See also Figure 1 and Figure 2 , Figure 1 1 is a schematic diagram of a battery management system according to an embodiment of the present application. The battery management system 100 includes a master control module 10, a plurality of slave control modules 20 and a plurality of selection modules 30. Figure 2 2 is a schematic diagram of the structure of the slave control module 20 in one embodiment.

[0031] The master control module 10 may be a Second Battery Management Unit (SBMU), and the slave control module 20 may be a Voltage Slave Control Module (VCMU).

[0032] The slave control module 20 includes an input unit 21, an output unit 22 and a communication unit 23. The input unit 21 of the first slave control module 20 among the N slave control modules 20 is connected to the master control module 10. The input unit 21 of the mth slave control module 20 is connected to the output unit 22 of the m-1th slave control module 20 and the master control module 10 through a selection module 30. The communication units 23 of the N slave control modules 20 are connected to the master control module 10. It can be understood that the N slave control modules 20 are connected in sequence, and the first slave control module 20 is the first one of the N slave control modules 20 in the connection order. Wherein, N and m are integers, N≥2, 2≤m≤N.

[0033] The input unit 21 of the first slave control module 20 is used to receive the addressing enable signal sent by the master control module 10. The input unit of the mth slave control module 20 is used to receive the addressing enable signal sent by the output unit of the m-1th slave control module 20 through the selection module 30, or to receive the addressing enable signal sent by the master control module 10 through the selection module 30. The selection module 30 is used to select the connection between the mth slave control module 20 and the m-1th slave control module 20, or to select the connection between the mth slave control module 20 and the master control module 10.

[0034] In the embodiment of the present application, the addressing mode includes two types, namely, the automatic addressing mode and the manual addressing mode. The selection of automatic addressing and manual addressing is determined by the master control module 10 controlling the selection module 30 to select different paths. Specifically, when the master control module 10 controls the selection module 30 to select the connection between the m-1th slave control module 20 and the mth slave control module 20, the N slave control modules 20 are connected in sequence, thereby realizing the automatic addressing of the N slave control modules 20 in sequence. When the master control module 10 controls the selection module 30 to select the connection between the master control module 10 and the slave control module 20, the manual addressing of the slave control module 20 is realized.

[0035] Specifically, in the automatic addressing mode, the master control module 10 sends an addressing enable signal to the first slave control module 20, and the first slave control module 20 enters the addressing state after receiving the addressing enable signal through the input unit 21. In the addressing state, the communication unit 23 receives the addressing data (such as the addressing message) sent by the master control module. After completing the addressing according to the addressing data, the first slave control module 20 sends the addressing enable signal to the input unit 21 of the second slave control module 20 through the output unit 22. The subsequent addressing method of each slave control module 20 is consistent with the addressing method of the first slave control module 20, which will not be repeated here.

[0036] Optionally, the selection module 30 can be implemented by a selection switch with a "2-to-1" function, which can be specifically a switch circuit formed by a MUX circuit, a MOS tube combination, etc. Specifically, the first input end of the selection module 30 is connected to the output unit 22 of the m-1th slave control module 20, the second input end of the selection module 30 is connected to the master control module 10, the output end of the selection module 30 is connected to the input unit 21 of the mth slave control module 20, and the control end of the selection module 30 is connected to the master control module 10 to receive the addressing mode signal sent by the master control module. The selection module 30 is configured to conduct the output unit 22 of the m-1th slave control module 20 and the input unit 21 of the mth slave control module 20 according to the addressing mode signal for automatic addressing, or conduct the master control module 10 and the input unit 21 of the mth slave control module 20 for manual addressing. Specifically, the selection module 30 is configured to, when the addressing mode signal is at a first level, turn on the output unit 22 of the m-1th slave control module 20 and the input unit 21 of the mth slave control module 20 for automatic addressing, and when the addressing mode signal is at a second level, turn on the input unit 21 of the master control module 10 and the mth slave control module 20 for manual addressing. For example, the first level is a high level, the second level is a low level, or the first level is a low level, and the second level is a high level.

[0037] like Figure 3 As shown, Figure 3 : is a schematic diagram of the structure of the selection module 30 in an embodiment, and the selection module 30 includes a first AND logic gate AND1, a second AND logic gate AND2, a NOT logic gate NO and an OR logic gate OR. Among them, the first input end of the first AND logic gate AND1 serves as the first input end of the selection module 30; the first input end of the second AND logic gate AND2 serves as the second input end of the selection module 30, and the second input end of the second AND logic gate AND serves as the control end of the selection module 30; the input end of the NOT logic gate NO is connected to the second input end of the second AND logic gate AND2, and the output end of the NOT logic gate NO is connected to the second input end of the first AND logic gate AND1; the first input end of the OR logic gate OR is connected to the output end of the first AND logic gate AND1, the second input end of the OR logic gate OR is connected to the output end of the second AND logic gate AND2, and the output end of the OR logic gate OR serves as the output end of the selection module 30.

[0038] The following is the truth table of the selection module 30:

[0039] The first input terminal X The second input terminal Y Control terminal SEL Output EN 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1

[0040] According to the above Figure 3 The logic circuit and the above truth table can be used to obtain the following formula:

[0041]

[0042] That is, when the addressing mode signal of the control end is the first level (low level "0"), the addressing enable signal of the output end is the addressing enable signal received by the first input end; when the addressing mode signal of the control end is the second level (high level "1"), the addressing enable signal of the output end is the addressing enable signal received by the second input end.

[0043] The following is combined with the above Figure 1-Figure 3 , and see Figure 4 , the addressing process of the slave control module 20 is introduced, Figure 4 It is a flow chart of an embodiment of an addressing method for a battery management system provided in the present application.

[0044] (1) After the battery management system is powered on, the output signals of the output units 22 of the master control module 10 and the slave control module 20 are initialized to a low level "0", and each slave control module 20 enters a silent state by default. After power-on initialization, the master control module 10 sends a verification broadcast frame (for example, FlowControlReq=0xAA in 0x0801FF00) to each slave control module 20 at a set period (for example, 50ms). The slave control modules 20 each read internal parameters (for example, the existing address of the slave control module 20) and perform verification calculations (for example, CRC8 calculations). The CRC8 standard generation polynomial used is x^8+x^5+x^4+1, that is, the polynomial is used to perform correlation calculations with the internal parameters to obtain the verification result (such as the CRC result).

[0045] (2) After each slave control module 20 calculates its own check result, it returns a frame check result (e.g., CRC check result: CfgResp_Type=1, CfgResp_Crc=CRC8 in 0x1827FExx) to the master control module 10 at a set period (e.g., 50ms). The master control module 10 sequentially checks the check result returned by each slave control module 20 with the check result calculated internally. In one embodiment, the master control module 10 and the slave control module 20 use the same check algorithm, for example, both use the CRC8 check algorithm.

[0046] (3) After the master control module 10 verifies that all slave control modules 20 have passed the verification, the master control module 10 periodically sends a running broadcast (for example, FlowControlReq=0x55 in 0x0801FF00, and stops sending the frame after 2s of continuous sending), and the system enters normal operation. If the master control module 10 determines that any slave control module 20 has failed the verification, it is considered that the slave control module 20 needs to be re-addressed, enters the addressing process, and stops the verification request (for example, stops sending the 0x0801FF00 message).

[0047] When automatic addressing is required, the master control module 10 controls the addressing mode signal sent to the control end of each selection module 30 to be at the first level. The selection module 30 conducts the connection path between the output unit 22 of the m-1th slave control module 20 and the input unit 21 of the mth slave control module 20, and enters the automatic addressing process described in the following (4)-(7).

[0048] (4) After the master control module 10 enters the self-addressing process, it outputs a high-level addressing enable signal to the input unit 21 of the first slave control module 20 connected thereto, and sends the addressing data (such as the configuration message) to the communication unit 23 of the first slave control module 20 through the communication link. After the input unit 21 of the first slave control module 20 connected to the master control module 10 detects the high-level addressing enable signal, it enters the waiting state. If the configuration message sent by the master control module 10 is received, the parameters are stored in the internal memory (such as the EE memory), and the configuration completion mark (CfgResp_Type=2) is returned to the master control module 10 through the communication unit 23, and at the same time, the high-level addressing enable signal is output to the second slave control module 20 through the output unit 22. The configuration of the first slave control module 20 is completed, that is, the addressing is completed.

[0049] (5) After receiving the configuration completion mark of the first slave control module 20, the master control module 10 sends the addressing data (such as the configuration message) to the communication unit 23 of the second slave control module 20. Similar to the configuration process of the first slave control module 20, the second slave control module 20 receives the configuration parameters and stores them in the internal memory, and returns the configuration completion mark (CfgResp_Type=2) to the master control module 10, and outputs a high-level addressing enable signal to the third slave control module 20 through the output unit 22.

[0050] (6) The subsequent configuration of the slave control module 20 is carried out in sequence according to the above configuration process.

[0051] (7) After the master control module 10 receives the configuration completion mark (CfgResp_Type=2) status of the last slave control module 20, the master control module 10 sends a system operation request broadcast frame (FlowControlReq=0x55), stops sending the message for a preset time (e.g., 2s), and turns off the high-level addressing enable signal output by the master control module 10. All slave control modules 20 receive the system operation broadcast frame of the master control module 10, turn off the high-level addressing enable signal output by the output unit 22 of the slave control module 20, switch from the silent state to the running state, and send normal communication messages.

[0052] When manual addressing is required, the addressing mode signal sent by the master control module 10 to the control end of the selection module 30 corresponding to the slave control module 20 that needs to be manually addressed is at the second level. The selection module 30 conducts the connection path between the master control module 10 and the input unit 21 of the slave control module 20, and enters the following manual addressing process:

[0053] The slave control module 20 receives the configuration message sent by the master control module 10, stores the parameters in the internal memory (such as EE memory), and returns a configuration completion mark (CfgResp_Type=2) to the master control module 10 through the communication unit 23, and the configuration of the slave control module 20 is completed.

[0054] In some embodiments, the above addressing process can also be processed for different system exceptions, as follows:

[0055] (1) The master control module 10 sends a verification broadcast frame to each slave control module 20, and waits for each slave control module 20 to return its calculated CRC result. If the CRC value of all slave control modules 20 is not received after waiting for 5 seconds or the returned CRC verification fails, the automatic addressing process is directly entered.

[0056] (2) After entering the automatic addressing process, after the master control module 10 sends a configuration message (0x0823FF00, 0x0824FF00) to a slave control module 20, it waits for the slave control module 20 to return a configuration completion mark. If it times out (for example, 500ms), the number of configuration failures is recorded as 1, and the corresponding configuration message is sent to the slave control module 20 again. If the number of configuration failures is greater than 5 times, the automatic addressing process ends, the configuration fails, and the addressing failure of the slave control module 20 is reported to the master control module 20, and the internal fault code is stored.

[0057] (3) The slave control module 20 is powered on and initialized. If the slave control module 20 still does not receive the verification broadcast frame from the master control module 10 after a preset period of time (for example, 2 seconds), the slave control module 20 addressing fault is reported to the master control module 20, and the internal fault code is stored. The slave control module 20 automatically enters the operating state, starts running, and sends the initial operating data.

[0058] (4) The slave control module 20 enters the waiting state. If it has not received all the configuration messages sent by the master control module 10 after a preset time (for example, 2 seconds), or has received the configuration message but cannot be correctly stored in the EE memory, the slave control module 20 addressing fault is reported to the master control module 20, and the internal fault code is stored. The slave control module 20 automatically enters the running state, starts running, and sends the initial running data.

[0059] (5) After the slave control module 20 completes writing the parameter configuration sent by the master control module 10, if it still does not receive the operation broadcast frame (0x55) sent by the master control module 10 after a preset time (for example, 5s), the slave control module 20 addressing fault is reported to the master control module 20 and the internal fault code is stored. The slave control module 20 automatically enters the operation state, starts running, and sends the initial data of the operation after the configuration is completed.

[0060] (6) When the system enters the running state, if it receives a forced automatic addressing command from the upper computer, it first determines whether the charging and discharging current is less than the preset value (for example, 0.1C) and the charging connection is not connected. If so, the system returns to the parameter automatic addressing process. The master control module 10 first returns to the automatic configuration stage and sends a return to waiting for configuration command to each slave control module 20. After receiving the command, the slave control module 20 enters the waiting for configuration state, and the system performs automatic addressing again.

[0061] The input unit 21 and the output unit 22 are introduced below.

[0062] like Figure 5 As shown, Figure 5 2 is a schematic diagram of the structure of an input unit 21 in an embodiment. The input unit 21 includes a first switch tube Q1 and a second switch tube Q2.

[0063] Among them, the first end of the first switch tube Q1 is configured to input a driving signal, and the second end of the first switch tube Q1 is connected to the selection module 30 to output an addressing enable signal; the first end of the second switch tube Q2 is connected to the control end of the first switch tube Q1, the second end of the second switch tube Q2 is grounded GND, and the control end of the second switch tube Q2 is connected to the control unit 24 and receives an enable control signal.

[0064] Optionally, in one embodiment, the input unit 21 further includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6 and a first capacitor C1.

[0065] Among them, the first end of the first resistor R1 is configured to input a driving signal, and the second end of the first resistor R1 is connected to the first end of the first switch tube Q1; the first end of the second resistor R2 is connected to the first end of the first resistor R1, and the second end of the second resistor R2 is connected to the control end of the first switch tube Q1; the first end of the third resistor R3 is connected to the control end of the first switch tube Q1, and the second end of the third resistor R3 is connected to the first end of the second switch tube Q2; the first end of the fourth resistor R4 is connected to the control unit 24 and receives an enable control signal, and the second end of the fourth resistor R4 is connected to the control end of the second switch tube Q4; the first end of the fifth resistor R5 is connected to the control end of the second switch tube Q2, and the second end of the fifth resistor R5 is grounded GND; the first end of the sixth resistor R6 is connected to the second end of the first switch tube Q1, and the second end of the sixth resistor R6 is grounded GND; the first end of the first capacitor C1 is connected to the second end of the first switch tube Q1, and the second end of the first capacitor C1 is grounded GND.

[0066] In one embodiment, the first switch tube Q1 is a PNP transistor, the first end of the first switch tube Q1 is the emitter, the second end is the collector, and the control end is the base; the second switch tube Q2 is an NPN transistor, the first end of the second switch tube Q2 is the collector, the second end is the emitter, and the control end is the base.

[0067] Specifically, when a slave control module 20 completes addressing, the control unit 24 sends a high-level enable control signal, the second switch tube Q2 is turned on, and the base level of the first switch tube Q1 is pulled down to a low level. The first switch tube Q1 is turned on, and the drive signal is output as a high-level addressing enable signal to the next slave control module 20.

[0068] It can be understood that in other embodiments, the first switch tube Q1 and the second switch tube Q2 may also be replaced by other switches with similar functions, such as MOS tubes of corresponding models.

[0069] like Figure 6 As shown, Figure 6 2 is a schematic diagram of the structure of an output unit 22 in an embodiment. The output unit 22 includes a seventh resistor R7 and a third switch tube Q3.

[0070] Among them, the first end of the seventh resistor R7 is configured to input a power supply voltage signal; the first end of the third switch tube Q3 is connected to the second end of the seventh resistor R7 and the control unit 24 to output an addressing trigger signal, the second end of the third switch tube Q3 is grounded GND, and the control end of the third switch tube Q3 is connected to the selection module 30 to receive an addressing enable signal.

[0071] Optionally, in one embodiment, the output unit 22 further includes an eighth resistor R8, a ninth resistor R9, a second capacitor C2 and a third capacitor C3.

[0072] Among them, the first end of the eighth resistor R8 is connected to the control end of the third switch tube Q3, and the second end of the eighth resistor R8 is connected to the selection module 30 to receive the addressing enable signal; the first end of the ninth resistor R9 is connected to the control end of the third switch tube Q3, and the second end of the ninth resistor R9 is grounded GND; the first end of the second capacitor C2 is connected to the second end of the eighth resistor R8, and the second end of the second capacitor C2 is grounded GND; the first end of the third capacitor C3 is connected to the first end of the third switch tube Q3, and the second end of the third capacitor C3 is grounded GND.

[0073] In one embodiment, the third switch tube Q3 is an NPN transistor, the first end of the third switch tube Q3 is a collector, the second end is an emitter, and the control end is a base.

[0074] Specifically, when a slave control module 20 receives a high-level addressing enable signal from the previous slave control module 20 or the master control module, the third switch tube Q3 is turned on, and the addressing trigger signal is pulled down to a low level, triggering the control unit 24 to enter the waiting state.

[0075] It can be understood that in other embodiments, the third switch tube Q3 can also be replaced by other switches with similar functions, such as a MOS tube of a corresponding model.

[0076] The battery management system provided in this embodiment includes: a master control module; a selection module; N slave control modules, the slave control modules include an input unit, an output unit and a communication unit, the input unit of the first slave control module among the N slave control modules is connected to the master control module to receive the addressing enable signal sent by the master control module, the input unit of the mth slave control module is connected to the output unit of the m-1th slave control module and the master control module through a selection module to receive the addressing enable signal sent by the m-1th slave control module or the master control module through the selection module, and the communication units of the N slave control modules are connected to the master control module; wherein N and m are integers, N≥2, 2≤m≤N. In the above manner, by setting a selection module between multiple slave control modules, different addressing modes can be freely switched, that is, automatic addressing or manual addressing can be realized. On the one hand, the diversification of addressing modes provided is conducive to the operability of the BMS system, and on the other hand, it can be selected according to different application scenarios. For example, after a slave control module fails, the slave control module is addressed separately without the need for all slave control modules to be addressed in sequence, thereby improving the addressing efficiency of the slave control module.

[0077] See also Figure 7 , Figure 7 1 is a schematic diagram of the structure of an electronic device according to an embodiment of the present application. The electronic device 700 includes the battery management system 100 as described in the above embodiment.

[0078] It is understandable that the electronic device 700 may be a new energy vehicle or a hybrid vehicle, or other electronic devices.

[0079] The display screen provided in the embodiment of the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A battery management system, characterized in that: The battery management system comprises: Main control module; Select the module; N slave control modules, the slave control modules include an input unit, an output unit and a communication unit, the input unit of the first slave control module among the N slave control modules is connected to the master control module to receive an addressing enable signal sent by the master control module, the input unit of the mth slave control module is connected to the output unit of the m-1th slave control module and the master control module through a selection module to receive an addressing enable signal sent by the m-1th slave control module or the master control module through the selection module, and the communication units of the N slave control modules are connected to the master control module; Wherein, N and m are integers, N≥2, 2≤m≤N.

2. The battery management system according to claim 1, characterized in that: The first input end of the selection module is connected to the output unit of the m-1th slave control module, the second input end of the selection module is connected to the master control module, the output end of the selection module is connected to the input unit of the mth slave control module, and the control end of the selection module is connected to the master control module to receive the addressing mode signal sent by the master control module; Wherein, the selection module is configured to, according to the addressing mode signal, turn on the output unit of the m-1th slave control module and the input unit of the mth slave control module for automatic addressing, or turn on the input unit of the master control module and the mth slave control module for manual addressing.

3. The battery management system according to claim 2, characterized in that: The selection module comprises: A first AND logic gate, wherein a first input terminal of the first AND logic gate serves as a first input terminal of the selection module; a second AND logic gate, wherein a first input terminal of the second AND logic gate serves as a second input terminal of the selection module, and a second input terminal of the second AND logic gate serves as a control terminal of the selection module; a NOT logic gate, wherein an input end of the NOT logic gate is connected to a second input end of the second AND logic gate, and an output end of the NOT logic gate is connected to a second input end of the first AND logic gate; An OR logic gate, wherein the first input end of the OR logic gate is connected to the output end of the first AND logic gate, the second input end of the OR logic gate is connected to the output end of the second AND logic gate, and the output end of the OR logic gate serves as the output end of the selection module.

4. The battery management system according to claim 1, characterized in that: The slave control module also includes a control unit connected to the input unit, the output unit and the communication unit, and the control unit is configured to receive an addressing enable signal through the input unit, receive addressing data through the communication unit, and send an addressing enable signal through the output unit.

5. The battery management system according to claim 4, characterized in that: The output unit comprises: A first switch tube, wherein a first end of the first switch tube is configured to input a driving signal, and a second end of the first switch tube is connected to the selection module to output the addressing enable signal; A second switch tube, wherein a first end of the second switch tube is connected to a control end of the first switch tube, a second end of the second switch tube is grounded, and the control end of the second switch tube is connected to the control unit and receives an enable control signal.

6. The battery management system according to claim 5, characterized in that: The output unit also includes: a first resistor, wherein a first end of the first resistor is configured to input the driving signal, and a second end of the first resistor is connected to a first end of the first switch tube; a second resistor, wherein a first end of the second resistor is connected to a first end of the first resistor, and a second end of the second resistor is connected to a control end of the first switch tube; a third resistor, wherein a first end of the third resistor is connected to the control end of the first switch tube, and a second end of the third resistor is connected to the first end of the second switch tube; a fourth resistor, a first end of the fourth resistor being connected to the control unit and receiving an enable control signal, and a second end of the fourth resistor being connected to a control end of the second switch tube; A fifth resistor, wherein a first end of the fifth resistor is connected to the control end of the second switch tube, and a second end of the fifth resistor is grounded.

7. The battery management system according to claim 5, characterized in that: The output unit also includes: a sixth resistor, wherein a first end of the sixth resistor is connected to the second end of the first switch tube, and a second end of the sixth resistor is grounded; A first capacitor, wherein a first end of the first capacitor is connected to a second end of the first switch tube, and a second end of the first capacitor is grounded.

8. The battery management system according to claim 4, characterized in that: The input unit comprises: a seventh resistor, wherein a first end of the seventh resistor is configured to input a power supply voltage signal; A third switch tube, wherein the first end of the third switch tube is connected to the second end of the seventh resistor and the control unit to output an addressing trigger signal, the second end of the third switch tube is grounded, and the control end of the third switch tube is connected to the selection module to receive the addressing enable signal.

9. The battery management system according to claim 8, characterized in that: The input unit also includes: an eighth resistor, a first end of the eighth resistor being connected to the control end of the third switch tube, and a second end of the eighth resistor being connected to the selection module to receive the addressing enable signal; a ninth resistor, wherein a first end of the ninth resistor is connected to the control end of the third switch tube, and a second end of the ninth resistor is grounded; a second capacitor, wherein a first end of the second capacitor is connected to the second end of the eighth resistor, and a second end of the second capacitor is grounded; A third capacitor, wherein a first end of the third capacitor is connected to a first end of the third switch tube, and a second end of the third capacitor is grounded.

10. An electronic device, characterized in that: The electronic device comprises a battery management system as claimed in any one of claims 1 to 9.

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