Semiconductor module, charger, and vehicle

Abstract

The utility model discloses a semiconductor module, a charger and a vehicle, the semiconductor module comprises a first substrate area, a second substrate area and a third substrate area, the first substrate area comprises a first conductive area and a second conductive area, and the second substrate area comprises a third conductive area and a fourth conductive area. A switching circuit of the power factor correction circuit is located in the first conductive region; the switching circuit of the resonant conversion primary side circuit is located in the second conductive region, and the switching circuit of the resonant conversion secondary side circuit is located in the third conductive region; a switching circuit of the direct-current conversion primary side circuit is located in the fourth conductive area, and a switching circuit of the direct-current conversion secondary side circuit is located on the third substrate area; a first insulating part extending in the second direction perpendicular to the first direction is arranged between the first substrate area and the second substrate area, and a second insulating part extending in the second direction is arranged between the second substrate area and the third substrate area. The semiconductor module integrated circuit has more topological functions, the module layout is more compact, and the high-low voltage electrical insulating property is good.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to a semiconductor module, and a charger and a vehicle using the semiconductor module. Background Art

[0002] In the related art, the on-board charger designs the OBC and DC / DC circuits as two independent functional structures, which occupies more space in the vehicle, and each component requires a separate housing, and also needs to be separately assembled with a fixing bracket and connecting harness, which is costly. Utility Model Content

[0003] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the first purpose of the utility model is to propose a semiconductor module, which can ensure charging efficiency, high integration, and improve high and low voltage insulation.

[0004] The second objective of the present invention is to provide a charger.

[0005] The third objective of the present invention is to provide a vehicle.

[0006] In order to achieve the above-mentioned purpose, a semiconductor module of an embodiment of the first aspect of the utility model comprises: a first substrate area, a second substrate area and a third substrate area, wherein the first substrate area, the second substrate area and the third substrate area extend along the same plane, the first substrate area comprises a first conductive area and a second conductive area, the second substrate area comprises a third conductive area and a fourth conductive area, the third conductive area is adjacent to the second conductive area, and the fourth conductive area is adjacent to the third substrate area; a switching circuit of a power factor correction circuit, wherein the switching circuit of the power factor correction circuit is located in the first conductive area; a switching circuit of a resonant conversion circuit, wherein the switching circuit of the resonant conversion circuit comprises a switch of a resonant conversion main side circuit. a switching circuit of a DC conversion circuit and a switching circuit of a resonant conversion secondary circuit, the switching circuit of the resonant conversion primary circuit is located in the second conductive area, and the switching circuit of the resonant conversion secondary circuit is located in the third conductive area; a switching circuit of a DC conversion circuit, the switching circuit of the DC conversion circuit includes a switching circuit of a DC conversion primary circuit and a switching circuit of a DC conversion secondary circuit, the switching circuit of the DC conversion primary circuit is located in the fourth conductive area, and the switching circuit of the DC conversion secondary circuit is located on the third substrate area; a first insulating member and a second insulating member, the first insulating member is located between the first substrate area and the second substrate area, and the second insulating member is located between the second substrate area and the third substrate area.

[0007] The semiconductor module of the embodiment of the utility model integrates the switching circuit of the power factor correction circuit, the switching circuit of the resonant conversion circuit and the switching circuit of the DC conversion circuit. The integrated circuit topology has more functions and higher integration, which improves the charging efficiency. The substrate areas are close to each other, which makes the layout of the module more compact while ensuring electrical isolation, provides convenience for the external connection of the transformer, and an insulating member is provided between adjacent substrate areas to enhance the electrical insulation between the substrate areas.

[0008] In some embodiments, the first substrate region, the second substrate region and the third substrate region are arranged in sequence along a first direction, the first conductive region and the second conductive region are arranged along the first direction, and the third conductive region and the fourth conductive region are arranged along the first direction.

[0009] In some embodiments, the semiconductor module also includes: a base plate, on which the first substrate area, the second substrate area and the third substrate area are all located; an insulating frame, which is located on the base plate, and surrounds the first substrate area, the second substrate area and the third substrate area; the insulating frame is constructed with a first spacing beam extending along a second direction perpendicular to the first direction between the first substrate area and the second substrate area as the first insulating member; the insulating frame is also constructed with a second spacing beam extending along the second direction between the second substrate area and the third substrate area as the second insulating member.

[0010] In some embodiments, a first fixed connection portion is provided on the first spacing beam, and the first fixed connection portion is used to fix the insulating frame and the plastic shell together; a second fixed connection portion is provided on the second spacing beam, and the second fixed connection portion is used to fix the insulating frame and the plastic shell together.

[0011] In some embodiments, the first conductive region includes a plurality of first sub-conductive regions arranged at intervals along a first direction and extending along a second direction perpendicular to the first direction, the plurality of first sub-conductive regions include at least one first DC conductive region, at least one first AC conductive region and at least one second DC conductive region; the switching circuit of the power factor correction circuit includes a plurality of first upper bridge power chips and a plurality of first lower bridge power chips, the plurality of first upper bridge power chips are located in the at least one first DC conductive region, the source electrodes of the plurality of first upper bridge power chips are electrically connected to the at least one second DC conductive region, the plurality of first lower bridge power chips are located in the at least one first AC conductive region, and the source electrodes of the plurality of first lower bridge power chips are electrically connected to the at least one second DC conductive region.

[0012] In some embodiments, the plurality of first sub-conductive regions include one first DC conductive region, two AC conductive regions and two second DC conductive regions, the two first AC conductive regions are located on both sides of the first DC conductive region along the first direction, and the two second DC conductive regions are respectively located on the side of the two first AC conductive regions away from the first DC conductive region along the first direction; the switching circuit of the power factor correction circuit includes two first upper bridge power chips and two first lower bridge power chips, the two first upper bridge power chips are located in the first DC conductive region, the source electrodes of the two first upper bridge power chips are respectively electrically connected to the two first AC conductive regions, the two first lower bridge power chips are respectively located in the two first AC conductive regions, and the source electrodes of the two first lower bridge power chips are respectively electrically connected to the two second DC conductive regions.

[0013] In some embodiments, one of the two first upper bridge power chips and one of the two first lower bridge power chips are MOS chips, the other of the two first upper bridge power chips and the other of the two first lower bridge power chips are IGBT chips; one of the MOS chip and one of the IGBT chips are located in the first DC conductive zone, and the other of the MOS chip and the other of the IGBT chips are located in the two first AC conductive zones respectively; two FRD chips are also provided corresponding to the two IGBT chips, one of the FRD chips is located in the first DC conductive zone, and the other of the FRD chips is located in the first AC conductive zone where the other of the IGBT chips is located, one end of one of the FRD chips is electrically connected to the first AC conductive zone where the other of the FRD chips is located, and the other of the FRD chips is electrically connected to the second DC conductive zone to which the other of the IGBT chips is connected.

[0014] In some embodiments, the second conductive region includes a plurality of second sub-conductive regions arranged at intervals along the first direction and extending along the second direction, and the plurality of second sub-conductive regions include at least one third DC conductive region, at least one second AC conductive region and at least one fourth DC conductive region; the switching circuit of the resonant conversion main side circuit includes a plurality of second upper bridge power chips and a plurality of second lower bridge power chips, the plurality of second upper bridge power chips are located on the at least one third DC conductive region, the source electrodes of the plurality of second upper bridge power chips are respectively electrically connected to the at least one second AC conductive region, the plurality of second lower bridge power chips are located on the at least one second AC conductive region, and the source electrodes of the plurality of second lower bridge power chips are respectively electrically connected to the at least one fourth DC conductive region.

[0015] In some embodiments, the plurality of second sub-conductive regions include two third DC conductive regions, two second AC conductive regions and two fourth DC conductive regions, the two second AC conductive regions are located on both sides of the two fourth DC conduction band regions along the first direction, the two third DC conductive regions are located on the side of the two second AC conductive regions away from the fourth DC conductive region along the first direction, and one end of the two third DC conductive regions close to the edge of the first substrate region extends along the first direction and surrounds the second AC conductive region and the fourth DC conductive region; the switch circuit of the resonant conversion main side circuit includes two second upper bridge power chips and two second lower bridge power chips, the two second upper bridge power chips are respectively located on the two third DC conductive regions, the source electrodes of the two second upper bridge power chips are respectively electrically connected to the adjacent second AC conductive regions, the two second lower bridge power chips are respectively located in the two second AC conductive regions, and the source electrodes of the two second lower bridge power chips are respectively electrically connected to the adjacent fourth DC conductive regions.

[0016] In some embodiments, the first substrate area includes a first side and a second side opposite to each other in the second direction; one end of the first sub-conductive area and the second sub-conductive area is close to the first side of the first substrate area; a plurality of first source signal detection conductive areas are also formed in the first conductive area and the second conductive area, and the plurality of first source signal detection conductive areas are located along the second direction on one side of the plurality of first sub-conductive areas and the plurality of second sub-conductive areas close to the second side of the first substrate area, and the plurality of first source signal detection conductive areas are arranged in sequence along the first direction; the source electrodes of the plurality of first upper bridge power chips, the source electrodes of the plurality of first lower bridge power chips, the source electrodes of the plurality of second upper bridge power chips, and the source electrodes of the plurality of second lower bridge power chips are electrically connected to the corresponding first source signal detection conductive areas, respectively.

[0017] In some embodiments, the first conductive region and the second conductive region further form a plurality of first gate signal detection conductive regions, the plurality of first gate signal detection conductive regions are located along the second direction on a side of the plurality of first source signal detection conductive regions away from the first sub-conductive region and the second sub-conductive region, the plurality of first gate signal detection conductive regions are arranged in sequence along the first direction, the plurality of first gate signal detection conductive regions are arranged one-to-one with the plurality of first source signal detection conductive regions, a portion of the first gate signal detection conductive region extends along the second direction to the side of the corresponding first source signal detection conductive region; the gates of the plurality of first upper bridge power chips, the gates of the plurality of first lower bridge power chips, the gates of the plurality of second upper bridge power chips and the gates of the plurality of second lower bridge power chips are electrically connected to the corresponding first gate signal detection conductive regions, respectively.

[0018] In some embodiments, the first substrate area also includes a third side and a fourth side opposite to each other along the first direction; the first conductive area is close to the third side of the first substrate area, and the second conductive area is close to the fourth side of the first substrate area; the second conductive area also includes a first thermal detection area, the first thermal detection area is close to the fourth side of the first substrate area along the first direction, the first thermal detection area is close to the second side of the first substrate area along the second direction, the first thermal detection area and a plurality of the first gate signal detection conductive areas are arranged along the first direction, and the first thermal detection area is also arranged along the first direction with a plurality of the first source signal detection conductive areas.

[0019] In some embodiments, each of the first DC conductive areas and each of the third DC conductive areas is provided with a first DC transmission terminal perpendicular to the first substrate area, each of the first AC conductive areas is provided with a first AC transmission terminal perpendicular to the first substrate area, each of the second AC conductive areas is provided with a second AC transmission terminal perpendicular to the first substrate area, each of the second DC conductive areas and the fourth DC conductive areas is provided with a second DC transmission terminal perpendicular to the first substrate area, and the first DC transmission terminal, the first AC transmission terminal, the second AC transmission terminal and the second DC transmission terminal are arranged along the first direction; each of the first source signal detection conductive areas is provided with a first source signal detection terminal perpendicular to the first substrate area to transmit a source signal; each of the first gate signal detection conductive areas is provided with a first gate signal detection terminal perpendicular to the first substrate area to transmit a gate signal; the first thermal detection area is provided with two first thermal detection terminals to transmit a thermal detection signal; wherein, a plurality of the first source signal detection terminals and one of the first thermal detection terminals are arranged along the first direction, and a plurality of the first gate signal detection terminals and another of the first thermal detection terminals are arranged along the first direction.

[0020] In some embodiments, the third conductive region includes a plurality of third sub-conductive regions arranged at intervals along a first direction and extending along a second direction perpendicular to the first direction, and the plurality of third sub-conductive regions include at least one fifth DC conductive region, at least one third AC conductive region and at least one sixth DC conductive region; the switching circuit of the resonant conversion secondary circuit includes a plurality of third upper bridge power chips and a plurality of third lower bridge power chips, the plurality of third upper bridge power chips are located on the at least one fifth DC conductive region, the source electrodes of the plurality of third upper bridge power chips are respectively electrically connected to the at least one third AC conductive region, the plurality of third lower bridge power chips are located in the at least one third AC conductive region, and the source electrodes of the plurality of third lower bridge power chips are respectively electrically connected to the at least one sixth DC conductive region.

[0021] In some embodiments, the switch circuit of the resonant conversion secondary circuit includes two fifth DC conductive areas, two third AC conductive areas and two sixth DC conductive areas, the two third AC conductive areas are located on both sides of the two sixth DC conductive areas along the first direction, the two fifth DC conductive areas are located on the side of the two third AC conductive areas away from the sixth DC conductive area along the first direction, and one end of the two fifth DC conductive areas close to the edge of the second substrate area extends along the first direction and surrounds the third AC conductive area and the sixth DC conductive area; the switch circuit of the resonant conversion secondary circuit includes two third upper bridge power chips and two third lower bridge power chips, the two third upper bridge power chips are respectively located on the two fifth DC conductive areas, the source electrodes of the two third upper bridge power chips are respectively electrically connected to the adjacent third AC conductive areas, the two third lower bridge power chips are respectively located on the two third AC conductive areas, and the source electrodes of the two third lower bridge power chips are respectively electrically connected to the two sixth DC conductive areas.

[0022] In some embodiments, the second substrate area includes a first side and a second side opposite to each other along the second direction; the plurality of third sub-conductive areas are close to the first side of the second substrate area; the third conductive area also includes a plurality of second source signal detection conductive areas, the plurality of second source signal detection conductive areas are located along the second direction on one side of the plurality of third sub-conductive areas close to the second side of the second substrate area, and the plurality of second source signal detection conductive areas are arranged along the first direction; the source electrodes of the plurality of third upper bridge power chips and the source electrodes of the plurality of third lower bridge power chips are respectively electrically connected to the corresponding second source signal detection conductive areas.

[0023] In some embodiments, the third conductive region also includes multiple second gate signal detection conductive regions, multiple second gate signal detection conductive regions are located along the second direction on the side of the multiple second source signal detection conductive regions away from the third sub-conductive region, multiple second gate signal detection conductive regions are arranged in sequence along the first direction, multiple second gate signal detection conductive regions are arranged one-to-one with multiple second source signal detection conductive regions, and a part of the second gate signal detection conductive region extends along the second direction to a side of the corresponding second source signal detection conductive region; the gates of the multiple third upper bridge power chips and the gates of the multiple third lower bridge power chips are respectively electrically connected to the corresponding second gate signal detection conductive regions.

[0024] In some embodiments, the fourth conductive region includes a plurality of fourth sub-conductive regions arranged at intervals along the first direction and extending along the second direction, and the plurality of fourth sub-conductive regions include at least one seventh DC conductive region, at least one fourth AC conductive region and at least one eighth DC conductive region; the switching circuit of the DC conversion main side circuit includes a plurality of fourth upper bridge power chips and a plurality of fourth lower bridge power chips, the plurality of fourth upper bridge power chips are located in the at least one seventh DC conductive region, the source electrodes of the plurality of fourth upper bridge power chips are respectively electrically connected to the at least one fourth AC conductive region, the plurality of fourth lower bridge power chips are located in the at least one fourth AC conductive region, and the source electrodes of the plurality of fourth lower bridge power chips are respectively electrically connected to the at least one eighth DC conductive region.

[0025] In some embodiments, the plurality of fourth sub-conductive regions include two seventh DC conductive regions, two fourth AC conductive regions, and two eighth DC conductive regions, the two fourth AC conductive regions are located on both sides of the two eighth DC conductive regions along the first direction, the two seventh DC conductive regions are located on a side of the two fourth AC conductive regions away from the eighth DC conductive region along the first direction, and one end of the two seventh DC conductive regions close to the first side of the second substrate region extends along the first direction and surrounds the fourth AC conductive region and the eighth DC conductive region; the switch circuit of the DC conversion main side circuit includes two fourth upper bridge power chips and two fourth lower bridge power chips, the two fourth upper bridge power chips are respectively located in the two seventh DC conductive regions, the source electrodes of the two fourth upper bridge power chips are respectively electrically connected to the adjacent fourth AC conductive regions, the two fourth lower bridge power chips are respectively located in the two fourth AC conductive regions, and the source electrodes of the two fourth lower bridge power chips are respectively electrically connected to the two eighth DC conductive regions.

[0026] In some embodiments, the fourth conductive region further includes a plurality of third source signal detection conductive regions and a plurality of third gate signal detection conductive regions, and the plurality of third source signal detection conductive regions are arranged in one-to-one correspondence with the plurality of third gate signal detection conductive regions; wherein the plurality of third source signal detection conductive regions are located along the second direction on a side of the plurality of fourth sub-conductive regions close to the second side of the second substrate region, the plurality of third source signal detection conductive regions are arranged along the first direction, and the sources of the plurality of fourth upper bridge power chips and the sources of the plurality of fourth lower bridge power chips are respectively electrically connected to the corresponding third source signal detection conductive regions; the plurality of third gate signal detection conductive regions are located along the second direction on a side of the plurality of third source signal detection conductive regions away from the fourth sub-conductive regions, the plurality of third gate signal detection conductive regions are arranged in sequence along the first direction, a portion of the third gate signal detection conductive region extends along the second direction to a side of the corresponding third source signal detection conductive region, and the gates of the plurality of fourth upper bridge power chips and the gates of the plurality of fourth lower bridge power chips are respectively electrically connected to the corresponding third gate signal detection conductive regions.

[0027] In some embodiments, the second substrate area also includes a third side and a fourth side opposite to each other along the first direction; the third conductive area is close to the third side of the second substrate area, and the fourth conductive area is close to the fourth side of the second substrate area; the third conductive area also includes a second thermal detection area, the second thermal detection area is close to the third side of the second substrate area along the first direction, and the second thermal detection area is close to the second side of the second substrate area along the second direction.

[0028] In some embodiments, each of the fifth DC conductive regions and each of the seventh DC conductive regions is provided with a third DC transmission terminal perpendicular to the second substrate region, each of the third AC conductive regions is provided with a third AC transmission terminal perpendicular to the second substrate region, each of the fourth AC conductive regions is provided with a fourth AC transmission terminal perpendicular to the second substrate region, each of the sixth DC conductive regions and each of the eighth DC conductive regions is provided with a fourth DC transmission terminal perpendicular to the second substrate region, and the third DC transmission terminal, the third AC transmission terminal, the fourth AC transmission terminal and the fourth DC transmission terminal are arranged along the first direction; each of the second source signal detection conductive regions is provided with a second source signal perpendicular to the second substrate region. Each of the third source signal detection conductive areas is provided with a third source signal detection terminal perpendicular to the second substrate area, each of the second gate signal detection conductive areas is provided with a second gate signal detection terminal perpendicular to the second substrate area, each of the third gate signal detection conductive areas is provided with a third gate signal detection terminal perpendicular to the second substrate area, and the second thermal detection area is provided with two second thermal detection terminals perpendicular to the second substrate area; one of the second thermal detection terminals, the second source signal detection terminal and the third source signal detection terminal is arranged in sequence along the first direction, and the other of the second thermal detection terminal, the second gate signal detection terminal and the third gate signal detection terminal is arranged in sequence along the first direction.

[0029] In some embodiments, a fifth sub-conductive region, a sixth sub-conductive region, and a seventh sub-conductive region are formed on the third substrate region, which are arranged in sequence along a first direction and extend along a second direction perpendicular to the first direction; the switching circuit of the secondary circuit of the DC conversion circuit includes a plurality of fifth power chips connected in parallel and a plurality of sixth power chips connected in parallel; a plurality of the fifth power chips are located in the fifth sub-conductive region, and a plurality of source electrodes of the fifth power chips are electrically connected to the sixth sub-conductive region; a plurality of the sixth power chips are located in the seventh sub-conductive region, and a plurality of source electrodes of the sixth power chips are electrically connected to the sixth sub-conductive region.

[0030] In some embodiments, the third substrate area includes a first edge and a second edge along the second direction; the third substrate area also includes: a first DC pin terminal, the first DC pin terminal is connected to the fifth sub-conductive area and extends along the second direction from the first edge of the third substrate area, for transmitting a DC signal; a second DC pin terminal, the second DC pin terminal is connected to the sixth sub-conductive area and extends along the second direction from the first edge of the third substrate area, for transmitting a DC signal; a third DC pin terminal, the third DC pin terminal is connected to the seventh sub-conductive area and extends along the second direction from the first edge of the third substrate area, for transmitting a DC signal; the first DC pin terminal, the second DC pin terminal and the third DC pin terminal are arranged along the first direction.

[0031] In some embodiments, the third substrate area further includes a fourth source signal detection conductive area and a fifth source signal detection conductive area; the fourth source signal detection conductive area and the fifth source signal detection conductive area both extend along the second direction, the fourth source signal detection conductive area is located along the first direction on a side of the fifth sub-conductive area away from the sixth sub-conductive area, one end of the fourth source signal detection conductive area close to the second side of the third substrate area is bent along the first direction to a side of the fifth sub-conductive area close to the second side of the third substrate area, the fifth source signal detection conductive area is located along the first direction on a side of the seventh sub-conductive area away from the sixth sub-conductive area, one end of the fifth source signal detection conductive area close to the second side of the third substrate area is bent along the first direction to a side of the seventh sub-conductive area close to the second side of the third substrate area; the sources of the plurality of fifth power chips are electrically connected to the fourth source signal detection conductive area, and the sources of the plurality of sixth power chips are electrically connected to the fifth source signal detection conductive area.

[0032] In some embodiments, a fourth gate signal detection conductive area and a fifth gate signal detection conductive area extending along the second direction are also formed on the third substrate area; the fourth gate signal detection conductive area is located along the first direction on a side of the fourth source signal detection conductive area away from the fifth sub-conductive area, and one end of the fourth gate signal detection conductive area close to the second side of the third substrate area is bent along the first direction to a side of the fourth source signal detection conductive area close to the second side of the third substrate area; the fifth gate signal detection conductive area is located along the first direction on a side of the fifth source signal detection conductive area away from the seventh sub-conductive area; a plurality of first gate resistors and a plurality of second gate resistors are also arranged on the third substrate area; a plurality of the first gate resistors are located in the fourth gate signal detection conductive area, and a plurality of the first gate resistors are correspondingly connected to the gates of a plurality of the fifth power chips, and a plurality of the second gate resistors are located in the fifth gate signal detection conductive area, and a plurality of the second gate resistors are correspondingly connected to the gates of a plurality of the sixth power chips.

[0033] In some embodiments, a third thermal detection area is also formed on the third substrate area, and the third thermal detection area is close to the second edge of the third substrate area along the second direction. The third thermal detection area is located between the bending portion of the fourth source signal detection conductive area and the bending portion of the fifth source signal detection conductive area along the first direction.

[0034] In some embodiments, a fourth source signal detection terminal perpendicular to the third substrate area is provided on the fourth source signal detection conductive area to provide a source signal of the fifth power chip; a fifth source signal detection terminal perpendicular to the third substrate area is provided on the fifth source signal detection conductive area to provide a source signal of the sixth power chip; a fourth gate signal detection terminal perpendicular to the third substrate area is provided on the fourth gate signal detection conductive area to provide a gate signal of the fifth power chip; a fifth gate signal detection terminal perpendicular to the third substrate area is provided on the fifth gate signal detection conductive area to provide a gate signal of the sixth power chip; a third thermal detection terminal perpendicular to the third substrate area is provided on the third thermal detection area to transmit a thermal detection signal of the third substrate area; the fourth gate signal detection terminal, the fourth source signal detection terminal, the third thermal detection terminal, the fifth source signal detection terminal and the fifth gate signal detection terminal are arranged along the first direction.

[0035] In order to achieve the above-mentioned purpose, the second aspect embodiment of the utility model also proposes a charger, including: the semiconductor module described above; a first transformer circuit, the primary end of the first transformer circuit is connected to the switching circuit of the resonant conversion primary circuit of the semiconductor module, and the secondary end of the first transformer circuit is connected to the switching circuit of the resonant conversion secondary circuit of the semiconductor module; a second transformer circuit, the primary end of the second transformer circuit is connected to the switching circuit of the DC conversion primary circuit of the semiconductor module, and the secondary end of the second transformer circuit is connected to the switching circuit of the DC conversion secondary circuit of the semiconductor module.

[0036] According to the charger of the embodiment of the utility model, by adopting the semiconductor module of the above embodiment, the semiconductor module has a higher degree of integration, and while ensuring the charging efficiency, the space occupied in the vehicle can be reduced. In addition, the high and low voltage insulation inside the semiconductor module is high, thereby improving the charging performance.

[0037] In some embodiments, a second AC transmission terminal connected to the switch circuit of the resonant conversion primary circuit is provided on the first substrate area of ​​the semiconductor module, and a third AC transmission terminal connected to the switch circuit of the resonant conversion secondary circuit is provided on the second substrate area of ​​the semiconductor module; the primary end of the first transformer circuit is connected to the second AC transmission terminal, and the secondary end of the first transformer circuit is connected to the third AC transmission terminal; a fourth AC transmission terminal connected to the switch circuit of the DC conversion primary circuit is provided on the second substrate area of ​​the semiconductor module, and three DC pin terminals connected to the switch circuit of the DC conversion secondary circuit are provided on the third substrate area of ​​the semiconductor module; the primary end of the second transformer circuit is connected to the fourth AC transmission terminal, and the secondary end of the second transformer circuit is connected to the three DC pin terminals.

[0038] In order to achieve the above-mentioned purpose, the third aspect of the present invention further provides a vehicle, including a power battery and the charger, wherein the charger is connected to the power battery.

[0039] According to the vehicle of the embodiment of the utility model, by adopting the charger of the above embodiment, the charging efficiency is high and the charger occupies little space in the vehicle.

[0040] Additional aspects and advantages of the present invention will be given in part in the following description, and in part will become apparent from the following description, or will be learned through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0042] Figure 1 is a schematic diagram of a semiconductor module according to an embodiment of the utility model;

[0043] Figure 2 is a plan view of a semiconductor module according to an embodiment of the utility model;

[0044] Figure 3 is a schematic diagram of the overall circuit of a charger according to an embodiment of the utility model;

[0045] Figure 4 is a schematic diagram of a charging process of a charger according to an embodiment of the utility model;

[0046] Figure 5 is a schematic diagram of a switch circuit of a semiconductor module according to the utility model;

[0047] Figure 6 It is a schematic diagram of a semiconductor module connected to an external transformer circuit according to an embodiment of the utility model;

[0048] Figure 7 (1) and (2) are a schematic diagram and a top view of a layout of a power chip in a first substrate region according to an embodiment of the present invention;

[0049] Figure 8 (1) and (2) are a schematic diagram and a top view of a layout of a power chip in a second substrate region according to an embodiment of the present invention;

[0050] Fig. 9 (1) and (2) are a schematic diagram and a top view of a layout of a power chip in a third substrate region according to an embodiment of the present invention.

[0051] Reference numerals:

[0052] Semiconductor module 100;

[0053] A first substrate region 101, a second substrate region 102 and a third substrate region 103;

[0054] A first conductive region 1.1, a second conductive region 1.2, a third conductive region 2.1 and a fourth conductive region 2.2;

[0055] The insulating frame 40, the first insulating member 41, the second insulating member 51, the first gate resistor 601 and the second gate resistor 602, the first fixed connection portion 411 and the second fixed connection portion 511;

[0056] a first DC conductive region 1-4, a first AC conductive region 1-3, a second DC conductive region 1-5, a third DC conductive region 2-4, a second AC conductive region 2-3, a fourth DC conductive region 2-5, a fifth DC conductive region 3-4, a third AC conductive region 3-3, a sixth DC conductive region 3-5, a seventh DC conductive region 4-4, a fourth AC conductive region 4-3, an eighth DC conductive region 4-5, a fifth sub-conductive region 7-4, a sixth sub-conductive region 7-5 and a seventh sub-conductive region 7-6;

[0057] first source signal detection conductive areas 1-2 and 2-2, first gate signal detection conductive areas 1-1 and 2-1, first heat detection area 401, second source signal detection conductive area 3-2, second gate signal detection conductive area 3-1, third source signal detection conductive area 4-2, third gate signal detection conductive area 4-1, second heat detection area 402, fourth source signal detection conductive area 5-2 and fifth source signal detection conductive area 5-3, fourth gate signal detection conductive area 5-1 and fifth gate signal detection conductive area 5-4, third heat detection area 403;

[0058] The first upper bridge power chip Q1 and Q3, the first lower bridge power chip Q2 and Q4, the second upper bridge power chip Q5 and Q7, the second lower bridge power chip Q6 and Q8, the third upper bridge power chip Q9 and Q11, the third lower bridge power chip Q10 and Q12, the fourth upper bridge power chip Q13 and Q15, the fourth lower bridge power chip Q14 and Q16, the fifth power chip Q17, and the sixth power chip Q18;

[0059] A first DC pin terminal 701 , a second DC pin terminal 702 and a third DC pin terminal 703 , a power terminal 511 , and a signal terminal 611 ;

[0060] The first side L1 and the second side L2 , the third side L3 and the fourth side L4 of the first substrate region 101 , the first side L5 and the second side L6 , the third side L7 and the fourth side L8 of the second substrate region 102 , and the first side L9 and the second side L10 of the third substrate region 103 . DETAILED DESCRIPTION

[0061] The embodiments of the present utility model are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present utility model are described in detail below.

[0062] Figure 1 is a schematic diagram of a semiconductor module according to an embodiment of the present invention. Figure 2 FIG. 1 is a plan view of a semiconductor module according to an embodiment of the present invention.

[0063] like Figure 1As shown, the semiconductor module 100 of the embodiment of the utility model includes a first substrate area 101, a second substrate area 102 and a third substrate area 103. The first substrate area 101, the second substrate area 102 and the third substrate area 103 extend along the same plane. Optionally, the first substrate area 101, the second substrate area 102 and the third substrate area 103 can be different areas of the same substrate; or optionally, the first substrate area 101, the second substrate area 102 and the third substrate area 103 can be defined on different substrates. For example, in either of these two optional situations, the substrate can be a ceramic copper-clad substrate, which can be single-sided copper-clad or double-sided copper-clad, but is not limited thereto.

[0064] like Figure 2 As shown, the first substrate area 101 includes a first conductive area 1.1 and a second conductive area 1.2. The second substrate area 102 includes a third conductive area 2.1 and a fourth conductive area 2.2. The third conductive area 2.1 is adjacent to the second conductive area 1.2, and the fourth conductive area 2.2 is adjacent to the third substrate area 103. This arrangement makes the layout more compact and the distribution more reasonable.

[0065] Figure 3 It is a total circuit of a charger according to an embodiment of the utility model, and the total circuit includes a power factor correction circuit (PFC, Power Factor Correction), a resonant conversion circuit (LLC converter) and a direct current conversion circuit (DC / DC). Among them, the power factor correction circuit is used to reduce grid interference, convert the single-phase alternating current input from the grid into direct current and play a role in correcting the power factor; the input end of the resonant conversion circuit is connected to the output end of the PFC switch circuit, and the voltage of the input current can be increased or decreased according to the battery working condition. Its switch circuit has a resonant characteristic, which can reduce the switching loss and improve the efficiency of the switch circuit on and off. Its LLC output end outputs direct current to the power battery; the power battery is connected to the input end of the direct current conversion circuit (DC / DC) conversion switch circuit, and the stable direct current outputs low-voltage direct current to the low-voltage battery through the DC / DC conversion switch circuit.

[0066] Figure 4 It is a schematic diagram of the charging sequence of a charger according to an embodiment of the utility model.

[0067] Reference Figure 3 and Figure 4 As shown, the power factor correction circuit is connected to the input terminal of the national grid, for example Figure 3 The AC-IN in the circuit realizes power factor correction through a power factor correction circuit. The AC power after power factor correction is converted into DC power through a resonant conversion circuit, which can be provided to the power battery to charge the power battery. The DC conversion circuit can also be used to convert the DC power into a low-voltage battery charging voltage to charge the low-voltage battery.

[0068] Each circuit includes a plurality of power switch tubes, and power factor correction, resonant conversion and DC conversion are realized by switching on and off the plurality of power switch tubes. In an embodiment of the utility model, the switch circuits of each circuit are integrated into the same semiconductor module.

[0069] That is, the semiconductor module 100 of the embodiment of the utility model includes a switch circuit of a power factor correction circuit, a switch circuit of a resonant conversion circuit, and a switch circuit of a DC conversion circuit. The schematic diagram of the switch circuit of the semiconductor module of the embodiment of the utility model is shown in FIG. Figure 5 As shown, the internal structure of the module is formed by connecting power chips. The semiconductor module 100 of the embodiment of the utility model does not include a transformer circuit. For example, the capacitor, inductor and transformer in the charging circuit do not appear in this semiconductor module. The overall circuit of the charger can be realized by connecting the semiconductor module 100 and a PCB (Printed Circuit Board), such as Figure 6 As shown, the semiconductor module 100 is connected to an external transformer circuit via electrical conductors.

[0070] The switch circuit of the power factor correction circuit is located in the first conductive area 1.1; the switch circuit of the resonant conversion circuit includes the switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit, the switch circuit of the resonant conversion primary circuit is located in the second conductive area 1.2, and the switch circuit of the resonant conversion secondary circuit is located in the third conductive area 2.1; the switch circuit of the DC conversion circuit includes the switch circuit of the DC conversion primary circuit and the switch circuit of the DC conversion secondary circuit, the switch circuit of the DC conversion primary circuit is located in the fourth conductive area 2.2, and the switch circuit of the DC conversion secondary circuit is located on the third substrate area 103. The third conductive area 2.1 is adjacent to the second conductive area 1.2, and the fourth conductive area 2.2 is adjacent to the third substrate area 103, so that the switch circuit of the resonant conversion secondary circuit and the switch circuit of the resonant conversion primary circuit, the switch circuit of the DC conversion primary circuit and the switch circuit of the DC conversion secondary circuit are located in different conductive areas, so that the layout can be compact while ensuring electrical isolation.

[0071] Furthermore, a first insulating member 41 is disposed between the first substrate area 101 and the second substrate area 102, and a second insulating member 51 is disposed between the second substrate area 101 and the third substrate area 103. The first insulating member 41 and the second insulating member 51 can reduce the problem of high and low voltage insulation between adjacent substrate areas in the module. In an embodiment, the first insulating member 41 and the second insulating member 51 can be insulating members disposed separately between adjacent substrate areas, or can be part of the module plastic package frame.

[0072] As described above, the semiconductor module 100 of the embodiment of the utility model integrates multifunctional switching circuits such as the switching circuit of the power factor correction circuit, the switching circuit of the resonant conversion circuit and the switching circuit of the DC conversion circuit into one module. The switching circuit has a high degree of integration, and each circuit part does not require a separate housing, which reduces the cost. In addition, combined with the compact module layout, the implementation of all circuits occupies less space in the vehicle compartment, has a higher power density output, higher charging efficiency, and lower switching loss.

[0073] Furthermore, the switch circuit of the power factor correction circuit and the switch circuit of the resonant conversion primary circuit, the switch circuit of the resonant conversion secondary circuit and the switch circuit of the DC conversion primary circuit, and the switch circuit of the DC conversion secondary circuit are each divided into a substrate area, so that the electrical isolation between the switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit, and between the switch circuit of the DC conversion primary circuit and the switch circuit of the DC conversion secondary circuit can be ensured. Insulating members are provided between adjacent substrate areas to further enhance the electrical insulation between the substrate areas.

[0074] In addition, the switching circuit of the power factor correction circuit and the switching circuit of the resonant conversion main side circuit, as well as the switching circuit of the resonant conversion secondary side circuit and the switching circuit of the DC conversion main side circuit belong to the same substrate area, and the substrate areas are close to each other, which makes the internal layout of the module more compact and provides convenience for the external connection of the transformer.

[0075] Furthermore, in some embodiments, Figure 2 As shown, the first substrate area 101, the second substrate area 102 and the third substrate area 103 are arranged in sequence along the first direction, the first conductive area 1.1 and the second conductive area 1.2 are arranged along the first direction, and the third conductive area 2.1 and the fourth conductive area 2.2 are arranged along the first direction. The substrate areas are arranged along the first direction with a spacing between them, so that the chip layout in the substrate is more symmetrical and the structural strength is better.

[0076] In an embodiment, Figure 1 As shown, the semiconductor module 100 further includes a base plate (not shown) and an insulating frame 40 .

[0077] The first substrate area 101, the second substrate area 102 and the third substrate area 103 are all located on the base plate. Furthermore, the substrate and the base plate can be directly welded, and the base plate can be connected to a heat dissipation structure such as a heat dissipation channel to achieve heat dissipation of the semiconductor module 100 and ensure the working performance of the power chip inside the semiconductor module 100.

[0078] like Figure 1As shown, the insulating frame 40 is located on the bottom plate, and the insulating frame 40 surrounds the first substrate area 101, the second substrate area 102 and the third substrate area 103; the insulating frame 40 is configured with a first spacing beam extending along a second direction perpendicular to the first direction between the first substrate area 101 and the second substrate area 102 as a first insulating member 41; the insulating frame 40 is also configured with a second spacing beam extending along the second direction between the second substrate area 102 and the third substrate area 103 as a second insulating member 51. The insulating frame 40 is used to insulate between the substrate areas, and the overall structural strength of the semiconductor module 100 can be improved while ensuring high and low voltage insulation.

[0079] Furthermore, if Figure 1 As shown, the first spacing beam 41 is provided with a first fixed connection portion 411, which is used to fix the insulating frame 40 to the plastic package shell. The second spacing beam 51 is provided with a second fixed connection portion 511, which is used to fix the insulating frame 40 to the plastic package shell.

[0080] In the embodiment, the first fixed connection portion 411 and the second fixed connection portion 511 may be in the form of snap-fits, which have a simple structure and are easy to install.

[0081] Specifically, after the power chip inside the semiconductor module 100 is installed and the various transmission and detection terminals are installed, the plastic package shell can be covered on the insulating frame 40 and fixedly connected through the first fixed connection part 411 and the second fixed connection part 511, so as to protect the internal power chip and isolate the power chip in the module from interference by external factors.

[0082] Referring to the above description, considering the need for electrical isolation and the need for an external transformer, the arrangement of the first substrate area 101, the second substrate area 102 and the third substrate area 103 on the bottom plate of the semiconductor module of the present application can meet the following requirements: Figure 2 As shown, the long edge of the semiconductor module 100 Figure 2 The first substrate area 101 is arranged in the horizontal direction, that is, the first direction, from left to right (in this embodiment, left to right is Figure 2 The three parts of the circuit board (as shown in the figure) are the fast tube functional area of ​​the power factor correction circuit, the slow tube functional area of ​​the power factor correction circuit, and the switching circuit of the resonant conversion main side circuit, wherein the fast tube functional area of ​​the power factor correction circuit and the slow tube functional area of ​​the power factor correction circuit do not need to be electrically isolated, while the switching circuit of the resonant conversion secondary side circuit needs to be electrically isolated from the switching circuit of the resonant conversion main side circuit and needs to be close to the switching circuit of the resonant conversion main side circuit in space. Therefore, the long edge of the second substrate area composed of the switching circuit of the resonant conversion secondary side circuit and the switching circuit of the DC conversion main side circuit Figure 2The layout is in the middle horizontal direction, i.e., the first direction, and the switch circuit of the resonant conversion secondary circuit is the left part, and the right part close to the first substrate area 101 is the switch circuit of the resonant conversion primary circuit, so that the switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit are divided into two different substrate areas to achieve electrical isolation and keep them close in space; similarly, the switch circuit of the DC conversion secondary circuit needs to be electrically isolated from the switch circuit of the DC conversion primary circuit, and needs to be close in space to the switch circuit of the DC conversion primary circuit, so the long edge of the third substrate area 103 containing the switch circuit of the DC conversion secondary circuit Figure 2 The arrangement in the horizontal direction, i.e., the first direction, enables the switch circuit of the DC conversion primary circuit and the switch circuit of the DC conversion secondary circuit to be respectively divided into two different substrates for electrical isolation, while being close in space. On this basis, insulating members such as spacer beams of the insulating frame 40 are arranged between the substrate areas and between the substrate areas, which can further enhance the electrical insulation between the substrates and the reliability of the module.

[0083] The specific layout of the power chips in each conductive area of ​​the semiconductor module 100 according to the embodiment of the present invention will be described below with reference to the accompanying drawings.

[0084] Figure 7 (1) is a schematic diagram of a power chip in the first conductive region according to an embodiment of the utility model. Figure 7 (2) corresponds to Figure 7 Layout diagram of the power chip in the schematic diagram in (1).

[0085] in, Figure 7 As shown in (2), the first conductive region 1.1 realizes the switch circuit function of the power factor correction circuit, and the second conductive region 1.2 realizes the switch circuit function of the resonant conversion main side circuit.

[0086] like Figure 7 As shown, the first conductive area 1.1 includes a plurality of first sub-conductive areas arranged at intervals along a first direction and extending along a second direction perpendicular to the first direction, and the plurality of first sub-conductive areas include at least one first DC conductive area 1-4, at least one first AC conductive area 1-3 and at least one second DC conductive area 1-5.

[0087] The switch circuit of the power factor correction circuit includes a plurality of first upper bridge power chips (e.g., Q1 and Q3) and a plurality of first lower bridge power chips (e.g., Q2 and Q4), wherein the plurality of first upper bridge power chips are located in at least one first DC conductive area 1-4, and the source electrodes of the plurality of first upper bridge power chips are electrically connected to at least one second DC conductive area 1-5, for example, by a binding wire or a conductive tape. The plurality of first lower bridge power chips are located in at least one first AC conductive area 1-3, and the source electrodes of the plurality of first lower bridge power chips are electrically connected to at least one second DC conductive area 1-5, for example, by a binding wire or a conductive tape.

[0088] Take two first upper bridge power chips and two first lower bridge power chips as an example. Figure 7 As shown, the multiple first sub-conductive regions include a first DC conductive region 1-4, two AC conductive regions 1-3 and two second DC conductive regions 1-5. The two first AC conductive regions 1-3 are located on both sides of the first DC conductive region 1-4 along the first direction, and the two second DC conductive regions 1-5 are located on the side of the two first AC conductive regions 1-3 away from the first DC conductive region 1-4 along the first direction.

[0089] The switch circuit of the power factor correction circuit includes two first upper bridge power chips (Q1 and Q3) and two first lower bridge power chips (Q2 and Q4), the two first upper bridge power chips are located in the first DC conductive area 1-4, that is, the two first upper bridge power chips, such as Q1 and Q3, share the first DC conductive area and the DC transmission terminal thereon, the source electrodes of the two first upper bridge power chips are respectively electrically connected to the two first AC conductive areas 1-3, for example, by binding wires, the two first lower bridge power chips are respectively located in the two first AC conductive areas 1-3, and the source electrodes of the two first lower bridge power chips are respectively connected to the two second DC conductive areas 1-5. The connection of the switch circuit of the implemented power factor correction circuit is as follows: Figure 7 As shown in (1).

[0090] Furthermore, in the embodiment, the switch circuit of the power factor correction circuit includes a fast tube function and a slow tube function. Specifically, the PFC fast tube function area can use a MOS chip such as a SiC MOS chip, and the corresponding module switch circuit Figure 7 (1) Q1, Q2 transistors; PFC slow tube functional area can use IGBT / FRD chip such as Figure 7 Q3 and Q4 in (1).

[0091] For example, one of the two first upper bridge power chips and one of the two first lower bridge power chips are MOS chips such as Q1 and Q2, and the other of the two first upper bridge power chips and the other of the two first lower bridge power chips are IGBT chips such as Q3 and Q4.

[0092] Among them, a MOS chip and an IGBT chip are located in the first DC conductive area 1-4, and another MOS chip and another IGBT chip are respectively located in the two first AC conductive areas 1-3. Two FRD chips are also provided corresponding to the two IGBT chips, one FRD chip is located in the first DC conductive area 1-4, and the other FRD chip is located in the first AC conductive area 1-3 where the other IGBT chip is located, one end of one FRD chip is electrically connected to the first AC conductive area 1-3 where the other FRD chip is located, and the other FRD chip is electrically connected to the second DC conductive area 1-5 connected to the other IGBT chip.

[0093] like Figure 7 As shown, the second conductive area 1.2 includes a plurality of second sub-conductive areas arranged at intervals along the first direction and extending along the second direction, and the plurality of second sub-conductive areas include at least one third DC conductive area 2-4, at least one second AC conductive area 2-3 and at least one fourth DC conductive area 2-5.

[0094] The switching circuit of the resonant conversion main side circuit includes multiple second upper bridge power chips (for example, Q5 and Q7) and multiple second lower bridge power chips (for example, Q6 and Q8), the multiple second upper bridge power chips are located on at least one third DC conductive area 2-4, the source electrodes of the multiple second upper bridge power chips are respectively electrically connected to at least one second AC conductive area 2-3, for example, by binding wires or conductive tapes, the multiple second lower bridge power chips are located on at least one second AC conductive area 2-3, and the source electrodes of the multiple second lower bridge power chips are respectively electrically connected to at least one fourth DC conductive area 2-5.

[0095] Take two second upper bridge power chips and two second lower bridge power chips as an example. Figure 7 As shown, the multiple second sub-conductive regions include two third DC conductive regions 2-4, two second AC conductive regions 2-3 and two fourth DC conductive regions 2-5, the two second AC conductive regions 2-3 are located on both sides of the two fourth DC conduction band regions 2-5 along the first direction, the two third DC conductive regions 2-4 are located on the side of the two second AC conductive regions 2-3 away from the fourth DC conductive region 2-5 along the first direction, and one end of the two third DC conductive regions 2-4 close to the edge of the first substrate region 101 extends along the first direction and surrounds the second AC conductive region 2-3 and the fourth DC conductive region 2-5.

[0096] Among them, the switching circuit of the resonant conversion main side circuit includes two second upper bridge power chips (Q5 and Q7) and two second lower bridge power chips (Q6 and Q8), the two second upper bridge power chips are respectively located on the two third DC conductive areas 2-4, and the source electrodes of the two second upper bridge power chips are respectively electrically connected to the adjacent second AC conductive areas 2-3, the two second lower bridge power chips are respectively located on the two second AC conductive areas 2-3, and the source electrodes of the two second lower bridge power chips are respectively electrically connected to the adjacent fourth DC conductive areas 2-5.

[0097] Further, each first DC conductive area 1-4 and each third DC conductive area 2-4 is provided with a first DC transmission terminal perpendicular to the first substrate area 101, each first AC conductive area 1-3 is provided with a first AC transmission terminal perpendicular to the first substrate area 101, each second AC conductive area 2-3 is provided with a second AC transmission terminal perpendicular to the first substrate area 101, and each second DC conductive area 1-5 and fourth DC conductive area 2-5 is provided with a second DC transmission terminal perpendicular to the first substrate area 101. Figure 7 As shown, the first DC transmission terminal, the first AC transmission terminal, the second AC transmission terminal and the second DC transmission terminal are arranged along the first direction.

[0098] In an embodiment, the first DC transmission terminal, the first AC transmission terminal, the second AC transmission terminal, and the second DC transmission terminal may be pin terminals, such as Figure 1 As shown, the first DC transmission terminal, the first AC transmission terminal, the second AC transmission terminal and the second DC transmission terminal correspond to the power terminal 511, and the power terminal 511 can be in a pin manner or other manners.

[0099] Furthermore, if Figure 7 As shown, the first substrate area 101 includes a first side L1 and a second side L2 opposite to each other in the second direction; one end of the first sub-conductive area and the second sub-conductive area is close to the first side L1 of the first substrate area 101; a plurality of first source signal detection conductive areas 1-2 and 2-2 are also formed in the first conductive area and the second conductive area, and the plurality of first source signal detection conductive areas 1-2 and 2-2 are located along the second direction on one side of the plurality of first sub-conductive areas and the plurality of second sub-conductive areas close to the second side L2 of the first substrate area 101, and the plurality of first source signal detection conductive areas 1-2 and 2-2 are arranged sequentially along the first direction.

[0100] Sources of the first upper bridge power chips, the first lower bridge power chips, the second upper bridge power chips and the second lower bridge power chips are electrically connected to the corresponding first source signal detection conductive areas 1 - 2 and 2 - 2 , respectively.

[0101] Each of the first source signal detection conductive areas 1-2 and 2-2 is provided with a first source signal detection terminal perpendicular to the first substrate area 101 to transmit a source signal. Figure 1 As shown, the first source signal detection terminal corresponds to the signal terminal 611 in the figure, and the signal terminal 611 can be in the form of a pin.

[0102] Similarly, the first conductive area and the second conductive area also form a plurality of first gate signal detection conductive areas 1-1 and 2-1, and the plurality of first gate signal detection conductive areas 1-1 and 2-1 are located along the second direction on a side of the plurality of first source signal detection conductive areas (1-2 and 2-2) away from the first sub-conductive area and the second sub-conductive area, and the plurality of first gate signal detection conductive areas (1-1 and 2-1) are arranged in sequence along the first direction, and the plurality of first gate signal detection conductive areas (1-1 and 2-1) are arranged one-to-one with the plurality of first source signal detection conductive areas (1-2 and 2-2), and a portion of the first gate signal detection conductive area (1-1 and 2-1) extends along the second direction to the side of the corresponding first source signal detection conductive area (1-2 and 2-2).

[0103] The gates of multiple first upper bridge power chips, the gates of multiple first lower bridge power chips, the gates of multiple second upper bridge power chips and the gates of multiple second lower bridge power chips are respectively electrically connected to the corresponding first gate signal detection conductive areas (1-1 and 2-1), for example, by binding wires or conductive tapes.

[0104] Each of the first gate signal detection conductive areas (1-1 and 2-1) is provided with a first gate signal detection terminal perpendicular to the first substrate area 101 to transmit a gate signal. Figure 1 In the figure, the first gate signal detection terminal may correspond to the signal terminal in the figure, and the signal terminal may be in the form of a pin or other applicable signal terminal.

[0105] like Figure 7 As shown, the first substrate region 101 further includes a third side L3 and a fourth side L4 opposite to each other along the first direction.

[0106] The first conductive area is close to the third side L3 of the first substrate area 101, and the second conductive area is close to the fourth side L4 of the first substrate area L4; the second conductive area also includes a first thermal detection area 401, the first thermal detection area 401 is close to the fourth side L4 of the first substrate area 101 along the first direction, the first thermal detection area 401 is close to the second side L2 of the first substrate area 101 along the second direction, the first thermal detection area 401 and the first gate signal detection conductive area (1-1 and 2-1) are arranged along the first direction, and the first thermal detection area 401 is also arranged along the first direction with the first source signal detection conductive areas 1-2 and 2-2.

[0107] For example, the first thermal detection area 401 may be an area where a thermistor is placed, and the temperature of the first substrate area is sensed by the thermistor.

[0108] The first thermal detection area 401 is provided with two first thermal detection terminals to transmit thermal detection signals; Figure 1 In the figure, the first heat detection terminal may correspond to the signal terminal, and the signal terminal may be in the form of a pin or other applicable forms. The pin terminal may be connected to an external circuit or circuit board through the plastic package housing of the semiconductor module 100.

[0109] like Figure 1 As shown in FIG. 7 , a plurality of first source signal detection terminals and a first heat detection terminal are arranged along the first direction, and a plurality of first gate signal detection terminals and another first heat detection terminal are arranged along the first direction. Such a design can simplify the process and facilitate installation.

[0110] It should be noted that if Figure 7 As shown, the first AC transmission terminals of the two first AC conductive areas 1-3 correspond to the connection ports 1 and 2 in the schematic diagram to connect to the AC input terminal of the power grid, and the second AC transmission terminals of the second AC conductive areas 2-3 correspond to the connection ports 5 and 6 in the schematic diagram to connect to the transformer circuit in the resonant conversion circuit.

[0111] Please refer to the attached Figure 8 The chip layout in the third conductive area and the fourth conductive area of ​​the second substrate area is described. Figure 8 (1) is a schematic diagram of the switching circuit of the secondary circuit of the resonant conversion and the switching circuit of the primary circuit of the DC conversion. Figure 8 (2) corresponds to Figure 8 Schematic diagram of the chip layout in (1).

[0112] The third conductive area 2.1 includes a plurality of third sub-conductive areas arranged at intervals along a first direction and extending along a second direction perpendicular to the first direction, and the plurality of third sub-conductive areas include at least one fifth DC conductive area 3-4, at least one third AC conductive area 3-3 and at least one sixth DC conductive area 3-5.

[0113] The switching circuit of the resonant conversion secondary circuit includes multiple third upper bridge power chips (for example, Q9 and Q11) and multiple third lower bridge power chips (for example, Q10 and Q12), the multiple third upper bridge power chips are located on at least one fifth DC conductive area 3-4, and the source electrodes of the multiple third upper bridge power chips are respectively electrically connected to at least one third AC conductive area 3-3, for example, by binding wires or conductive strips; the multiple third lower bridge power chips are located in at least one third AC conductive area 3-3, and the source electrodes of the multiple third lower bridge power chips are respectively electrically connected to at least one sixth DC conductive area 3-6, for example, by binding wires or conductive strips.

[0114] Take the switching circuit of the resonant conversion secondary circuit including two third upper bridge power chips and two third lower bridge power chips as an example.

[0115] like Figure 8 As shown, the switch circuit of the resonant conversion secondary circuit includes two fifth DC conductive areas 3-4, two third AC conductive areas 3-3 and two sixth DC conductive areas 3-6, the two third AC conductive areas 3-3 are located on both sides of the two sixth DC conductive areas 3-5 along the first direction, the two fifth DC conductive areas 3-4 are located on the side of the two third AC conductive areas 3-3 away from the sixth DC conductive area 3-5 along the first direction, and one end of the two fifth DC conductive areas 3-4 close to the edge of the second substrate area extends along the first direction and surrounds the third AC conductive area 3-3 and the sixth DC conductive area 3-5.

[0116] The switching circuit of the resonant conversion secondary circuit includes two third upper bridge power chips (Q9 and Q11) and two third lower bridge power chips (Q10 and Q12). The two third upper bridge power chips are respectively located on the two fifth DC conductive areas 3-4, and the sources of the two third upper bridge power chips are respectively electrically connected to the adjacent third AC conductive areas 3-3. The two third lower bridge power chips are respectively located on the two third AC conductive areas 3-3, and the sources of the two third lower bridge power chips are respectively electrically connected to the two sixth DC conductive areas 3-5.

[0117] Furthermore, if Figure 8 As shown, the second substrate region 102 includes a first side L5 and a second side L6 that are opposite to each other along the second direction; and the plurality of third sub-conductive regions are close to the first side L5 of the second substrate region 102 .

[0118] The third conductive area 2.1 also includes a plurality of second source signal detection conductive areas 3-2, which are located along the second direction on one side of the plurality of third sub-conductive areas 2.1 close to the second side L6 of the second substrate area 102, and are arranged along the first direction. The sources of the plurality of third upper bridge power chips and the sources of the plurality of third lower bridge power chips are electrically connected to the corresponding second source signal detection conductive areas 3-2, respectively, to provide source signals.

[0119] like Figure 8As shown, the third conductive area also includes a plurality of second gate signal detection conductive areas 3-1, the plurality of second gate signal detection conductive areas 3-1 are located along the second direction on a side of the plurality of second source signal detection conductive areas 3-2 away from the third sub-conductive area, the plurality of second gate signal detection conductive areas 3-1 are arranged in sequence along the first direction, the plurality of second gate signal detection conductive areas 3-1 are arranged one-to-one with the plurality of second source signal detection conductive areas 3-2, and a portion of the second gate signal detection conductive area 3-1 extends along the second direction to a side of the corresponding second source signal detection conductive area 3-2. The gates of the plurality of third upper bridge power chips and the gates of the plurality of third lower bridge power chips are respectively connected to the corresponding second gate signal detection conductive areas 3-1 to provide gate signals for the power chips.

[0120] like Figure 8 As shown, the fourth conductive region 2.2 includes a plurality of fourth sub-conductive regions spaced apart along the first direction and extending along the second direction, and the plurality of fourth sub-conductive regions include at least one seventh DC conductive region 4-4, at least one fourth AC conductive region 4-3 and at least one eighth DC conductive region 4-5.

[0121] The switching circuit of the DC conversion main side circuit includes multiple fourth upper bridge power chips (for example, Q13 and Q15) and multiple fourth lower bridge power chips (for example, Q14 and Q16), the multiple fourth upper bridge power chips are located in at least one seventh DC conductive zone 4-4, the source electrodes of the multiple fourth upper bridge power chips are respectively electrically connected to at least one fourth AC conductive zone 4-3, the multiple fourth lower bridge power chips are located in at least one fourth AC conductive zone 4-3, and the source electrodes of the multiple fourth lower bridge power chips are respectively connected to at least one eighth DC conductive zone 4-5.

[0122] Take the case where the switch circuit of the DC conversion main side circuit includes two fourth upper bridge power chips and two fourth lower bridge power chips as an example.

[0123] like Figure 8 As shown, the multiple fourth sub-conductive regions include two seventh DC conductive regions 4-4, two fourth AC conductive regions 4-3 and two eighth DC conductive regions 4-5. The two fourth AC conductive regions 4-3 are located on both sides of the two eighth DC conductive regions 4-5 along the first direction, the two seventh DC conductive regions 4-4 are located on the side of the two fourth AC conductive regions 4-3 away from the eighth DC conductive region 4-5 along the first direction, and one end of the two seventh DC conductive regions 4-4 close to the first side of the second substrate region 102 extends along the first direction and surrounds the fourth AC conductive region 4-3 and the eighth DC conductive region 4-5.

[0124] The switching circuit of the DC conversion main side circuit includes two fourth upper bridge power chips and two fourth lower bridge power chips. The two fourth upper bridge power chips are respectively located in the two seventh DC conductive areas 4-4, and the sources of the two fourth upper bridge power chips are respectively electrically connected to the adjacent fourth AC conductive areas 4-3. The two fourth lower bridge power chips are respectively located in the two fourth AC conductive areas 4-3, and the sources of the two fourth lower bridge power chips are respectively electrically connected to the two eighth DC conductive areas 4-5.

[0125] Furthermore, if Figure 8 As shown, the fourth conductive region 2.2 further includes a plurality of third source signal detection conductive regions 4-2 and a plurality of third gate signal detection conductive regions 4-1, and the plurality of third source signal detection conductive regions 4-2 and the plurality of third gate signal detection conductive regions 4-1 are arranged in one-to-one correspondence.

[0126] Among them, multiple third source signal detection conductive areas 4-2 are located along the second direction on one side of the second side L6 of multiple fourth sub-conductive areas close to the second substrate area 102, and multiple third source signal detection conductive areas 4-2 are arranged along the first direction. The sources of multiple fourth upper bridge power chips and the sources of multiple fourth lower bridge power chips are respectively electrically connected to the corresponding third source signal detection conductive areas 4-2, for example, by binding wires or conductive tapes, to provide source signals for the power chips.

[0127] A plurality of third gate signal detection conductive areas 4-1 are located along the second direction on a side of a plurality of third source signal detection conductive areas 4-2 away from the fourth sub-conductive area, a plurality of third gate signal detection conductive areas 4-1 are arranged in sequence along the first direction, a portion of the third gate signal detection conductive area 4-1 extends along the second direction to a side of the corresponding third source signal detection conductive area 4-2, a plurality of fourth upper bridge power chips' gates and a plurality of fourth lower bridge power chips' gates are respectively electrically connected to the corresponding third gate signal detection conductive areas 4-1 to provide gate signals for the power chips.

[0128] Further, in an embodiment, Figure 8 As shown, the second substrate area 102 further includes a third side L7 and a fourth side L8 opposite to each other along the first direction. The third conductive area 2.1 is close to the third side L7, and the fourth conductive area 2.2 is close to the fourth side L8.

[0129] The third conductive region 2.1 further includes a second thermal detection region 402, which is close to a third side L7 of the second substrate region 102 along the first direction and close to a second side L8 of the second substrate region 102 along the second direction.

[0130] For example, the second thermal detection area 402 may be an area where a thermistor is placed, and the temperature of the second substrate area 102 is detected by the thermistor.

[0131] like Figure 1 As shown in or 8, each fifth DC conductive area 3-4 and each seventh DC conductive area 4-4 is provided with a third DC transmission terminal perpendicular to the second substrate area 102, each third AC conductive area 3-3 is provided with a third AC transmission terminal perpendicular to the second substrate area 102, each fourth AC conductive area 4-3 is provided with a fourth AC transmission terminal perpendicular to the second substrate area 102, each sixth DC conductive area 3-5 and each eighth DC conductive area 4-5 is provided with a fourth DC transmission terminal perpendicular to the second substrate area 102, and the third DC transmission terminal, the third AC transmission terminal, the fourth AC transmission terminal and the fourth DC transmission terminal are arranged along the first direction.

[0132] Each second source signal detection conductive area 3-2 is provided with a second source signal detection terminal perpendicular to the second substrate area 102, each third source signal detection conductive area 4-2 is provided with a third source signal detection terminal perpendicular to the second substrate area 102, each second gate signal conductive area 3-1 is provided with a second gate signal detection terminal perpendicular to the second substrate area 102, each third gate signal detection conductive area 4-1 is provided with a third gate signal detection terminal perpendicular to the second substrate area 102, and the second thermal detection area 402 is provided with two second thermal detection terminals perpendicular to the second substrate area 102.

[0133] A second heat detection terminal, a second source signal detection terminal and a third source signal detection terminal are arranged in sequence along the first direction, and another second heat detection terminal, a second gate signal detection terminal and a third gate signal detection terminal are arranged in sequence along the first direction. In this way, it is easy to install.

[0134] Among them, in the embodiment, Figure 1 As shown, the power terminals and signal terminals can be pin terminals or other suitable terminals, and the pin terminals extend through the housing of the semiconductor module 100 and can be connected to an external circuit to reduce the occupied space. Figure 8 As shown, the two third AC transmission terminals can correspond to the connection ports 7 and 8 in the schematic diagram to connect the transformer circuit of the resonant conversion circuit, that is, the external transformer circuit can be connected through the two third AC transmission terminals to form a resonant conversion circuit. The two fourth AC transmission terminals can correspond to the connection ports 14 and 15 in the schematic diagram to connect the transformer circuit of the DC conversion circuit, that is, the external transformer circuit can be connected through the fourth AC transmission terminals to form a DC conversion circuit.

[0135] The chip layout of the third substrate region of the semiconductor module is described below.

[0136] Fig. 9(1) and (2) are a schematic diagram and a layout diagram of power chip connection in the third substrate region according to an embodiment of the present invention.

[0137] like Fig. 9 As shown, a fifth sub-conductive region 7-4, a sixth sub-conductive region 7-5 and a seventh sub-conductive region 7-6 are formed on the third substrate region 103 and are arranged in sequence along the first direction and extend along a second direction perpendicular to the first direction.

[0138] The switching circuit of the secondary side circuit of the DC conversion circuit includes multiple fifth power chips connected in parallel (for example, Q17 and two power chips connected in parallel with Q17) and multiple sixth power chips connected in parallel (for example, Q18 and two power chips connected in parallel with Q18).

[0139] A plurality of fifth power chips are located in the fifth sub-conductive area 7-4, and the sources of the plurality of fifth power chips are electrically connected to the sixth sub-conductive area 7-5, for example, by a binding wire or a conductive tape or other electrical connector. A plurality of sixth power chips are located in the seventh sub-conductive area 7-6, and the sources of the plurality of sixth power chips are electrically connected to the sixth sub-conductive area 7-5, for example, by a binding wire or a conductive tape or other electrical connector.

[0140] like Fig. 9 As shown, the third substrate region 103 includes a first side L9 and a second side L10 along the second direction.

[0141] The third substrate region 103 further includes a first DC pin terminal 701 , a second DC pin terminal 702 and a third DC pin terminal 703 .

[0142] Among them, the first DC pin terminal 701 is connected to the fifth sub-conductive area 7-4 and extends along the second direction from the first side of the third substrate area 103, which is used to transmit DC signals; the second DC pin terminal 702 is connected to the sixth sub-conductive area 7-5 and extends along the second direction from the first side L9 of the third substrate area 103, which is used to transmit DC signals; the third DC pin terminal 703 is connected to the seventh sub-conductive area 7-6 and extends along the second direction from the first side of the third substrate area 103, which is used to transmit DC signals. The first DC pin terminal 701, the second DC pin terminal 702 and the third DC pin terminal 703 are arranged along the first direction. The DC conversion circuit can realize DC conversion such as step-down or step-up. In an embodiment of the utility model, the DC conversion circuit can be used to convert the medium and high voltage output by the power battery or the resonant conversion circuit into low voltage, and then provide it to the low-voltage battery to realize charging of the low-voltage battery, and then the low-voltage battery can power the vehicle-mounted low-voltage equipment. The above three DC pin terminals can correspond to Figure 3 T4-, T4 and T4+ in the schematic diagram output DC to the low-voltage battery to charge the low-voltage battery.

[0143] In an embodiment, the switching circuit output of the DC conversion circuit adopts a DC pin terminal, which can be ultrasonically welded to the third substrate area, that is, a high-power terminal is used to output the DC signal required by the battery. Compared with the pin power end, the output current is larger and the structural strength is improved.

[0144] Furthermore, if Fig. 9 As shown, the third substrate region 103 further includes a fourth source signal detection conductive region 5 - 2 and a fifth source signal detection conductive region 5 - 3 .

[0145] The fourth source signal detection conductive area 5-2 and the fifth source signal detection conductive area 5-3 both extend along the second direction. The fourth source signal detection conductive area 5-2 is located along the first direction on a side of the fifth sub-conductive area 7-4 away from the sixth sub-conductive area 7-5. One end of the fourth source signal detection conductive area 5-2 close to the second side L10 of the third substrate area 103 is bent along the first direction to the side of the second side L10 of the fifth sub-conductive area 7-4 close to the third substrate area 103. The fifth source signal detection conductive area 5-3 is located along the first direction on a side of the seventh sub-conductive area 7-6 away from the sixth sub-conductive area 7-5. One end of the fifth source signal detection conductive area 5-3 close to the second side L10 of the third substrate area 103 is bent along the first direction to the side of the second side L10 of the seventh sub-conductive area 7-6 close to the third substrate area 103.

[0146] The sources of multiple fifth power chips are electrically connected to the fourth source signal detection conductive area 5-2, for example, by binding wires or conductive tapes or other forms of electrical connectors, and the sources of multiple sixth power chips are electrically connected to the fifth source signal detection conductive area 5-3 to provide source signals for the power chips.

[0147] like Fig. 9 As shown, a fourth gate signal detection conductive region 5 - 1 and a fifth gate signal detection conductive region 5 - 4 extending along the second direction are also formed on the third substrate region 103 .

[0148] The fourth gate signal detection conductive area 5-1 is located along the first direction on a side of the fourth source signal detection conductive area 5-2 away from the fifth sub-conductive area 7-4, and one end of the fourth gate signal detection conductive area 5-1 close to the second side L10 of the third substrate area 103 is bent along the first direction to the side of the fourth source signal detection conductive area 5-2 close to the second side L10 of the third substrate area 103; the fifth gate signal detection conductive area 5-4 is located along the first direction on a side of the fifth source signal detection conductive area 5-3 away from the seventh sub-conductive area 7-6.

[0149] like Fig. 9As shown, a plurality of first gate resistors 601 and a plurality of second gate resistors 602 are also provided on the third substrate area 103. The plurality of first gate resistors 601 are located in the fourth gate signal detection conductive area 5-1, and the plurality of first gate resistors 601 are connected to the gates of the plurality of fifth power chips accordingly, and the plurality of second gate resistors 602 are located in the fifth gate signal detection conductive area 5-4, and the plurality of second gate resistors 602 are connected to the gates of the plurality of sixth power chips accordingly, so as to play a role in current limiting. Setting a built-in gate resistor can play a role in current limiting, and prevent damage to the chip caused by excessive current.

[0150] like Fig. 9 As shown, a third thermal detection area 403 is also formed on the third substrate area 103. The third thermal detection area 403 is close to the second side L10 of the third substrate area 103 along the second direction. The third thermal detection area 403 is located between the bending part of the fourth source signal detection conductive area 5-2 and the bending part of the fifth source signal detection conductive area 5-3 along the first direction.

[0151] For example, the third thermal detection area 403 may be an area where a thermistor is placed, and the temperature of the third substrate area 103 is detected by the thermistor.

[0152] like Fig. 9 As shown, the fourth source signal detection conductive area 5-2 is provided with a fourth source signal detection terminal perpendicular to the third substrate area 103, and is electrically connected to the fourth source signal detection conductive area 5-2 through the fourth source signal detection terminal, so as to provide a source signal for the fifth power chip whose source is connected to the fourth source signal detection conductive area; the fifth source signal detection conductive area 5-3 is provided with a fifth source signal detection terminal perpendicular to the third substrate area 103, and is electrically connected to the fifth source signal detection conductive area 5-3 through the fifth source signal detection terminal, so as to provide a source signal for the sixth power chip whose source is connected to the fifth source signal detection conductive area 5-3; the fourth gate signal detection conductive area 5-1 is provided with a fourth gate signal detection terminal perpendicular to the third substrate area 103, so as to provide a gate signal of the fifth power chip through the fourth gate signal detection terminal; the fifth gate signal detection conductive area 5-4 is provided with a fifth gate signal detection terminal perpendicular to the third substrate area 103, so as to provide a gate signal of the sixth power chip.

[0153] The third thermal detection area 403 is provided with a third thermal detection terminal perpendicular to the third substrate area 103 to transmit a thermal detection signal of the third substrate area; Fig. 9 As shown, the fourth gate signal detection terminal, the fourth source signal detection terminal, the third heat detection terminal, the fifth source signal detection terminal and the fifth gate signal detection terminal are arranged along the first direction.

[0154] In an embodiment, the above detection terminal may be a pin terminal, and the pin terminal may be connected to an external circuit through the plastic package housing of the semiconductor module 100 to obtain a detection signal.

[0155] As described above, in the embodiments, an integrated SMD chip layout can be adopted for the power chip in the semiconductor module 100, and the SMD chip is connected to the corresponding conductive area through electrical connectors such as binding wires or conductive tapes. Then, during packaging, sealant can be used to fill and cure the module to fix the chip and electrical connectors inside the module to avoid short circuit caused by movement.

[0156] The above layout of each substrate area has at least the following technical effects:

[0157] 1. From the perspective of electrical isolation and transformer installation. The present application scheme combines the electrical insulation between different switch circuits with the convenience of external connection of the transformer, wherein the power factor correction circuit integrated in the same semiconductor module, such as the switch circuit of the PFC single-phase circuit or the PFC three-phase circuit, the switch circuit of the resonant conversion circuit, and the switch circuit of the DC conversion circuit are divided into regions. For example, the switch circuit of the power factor correction circuit and the switch circuit of the resonant conversion primary circuit, the switch circuit of the resonant conversion secondary circuit and the switch circuit of the DC conversion primary circuit, and the switch circuit of the DC conversion secondary circuit are each divided into a substrate area to ensure electrical isolation between the switch circuit of the resonant conversion primary circuit and the switch circuit of the resonant conversion secondary circuit, and between the switch circuit of the DC conversion primary circuit and the switch circuit of the DC conversion secondary circuit. Insulating parts such as the spacing beam part of the insulating outer frame are provided between the substrate areas to further enhance the electrical insulation between the substrate areas. At the same time, the switch circuit of the power factor correction circuit and the switch circuit of the resonant conversion primary circuit, and the switch circuit of the resonant conversion secondary circuit and the switch circuit of the DC conversion primary circuit belong to the same substrate area, and the substrate areas are close to each other, so that the internal layout of the semiconductor module 100 is more compact, which facilitates the external connection of the transformer.

[0158] 2. From the perspective of parasitic inductance. The size of the self-generated inductance is proportional to the length of the current path, and the size of the mutual inductance is inversely proportional to the magnetic flux that cancels out the magnetic effects of the current. Since in the present application, the current path in the substrate area is shorter than the current path of the pin in the prior art solution of the single-tube device, and because the conductive layer in the opposite direction of the current flow to the substrate is wider than the pin path, the magnetic flux generated by the magnetic effect of the current cancels out more, so the inductance of the semiconductor module of the present application is low, which reduces the module voltage spike accordingly and reduces the switching loss.

[0159] 3. In terms of heat dissipation performance. For power devices, the spacing between devices will affect the heat dissipation performance to a certain extent. The semiconductor module of the embodiment of the utility model can adopt an integrated patch chip layout in the substrate area, with fewer solder joints and shortened required length of the substrate and increased width. In addition, the semiconductor module of the embodiment of the utility model can directly weld the substrate to the bottom plate, and then the bottom plate can be connected to the heat dissipation structure to achieve direct heat dissipation, thereby improving the overall heat dissipation performance of the module, reducing the operating junction temperature, and improving the operating life and maximum output capacity.

[0160] 4. In terms of reliability and cost. Each discrete single-tube device has independent pins and is sealed in an independent shell. The existing technical solutions use a large number of discrete single-tube devices, resulting in a large overall volume and high material costs. At the same time, a large number of welding points will be generated when assembling the module, the production efficiency is not high and the structural strength is insufficient. When the module fails, checking the discrete single-tube devices one by one will greatly increase the workload and time cost. The semiconductor module of this application uses a surface-mount power chip to replace the discrete device, which eliminates the installation and welding process of a large number of discrete devices when assembling the module. The chip installation can be quickly completed through automated surface-mount equipment. The external insulation frame and plastic-sealed shell form a shell such as a plastic shell to achieve the packaging of the integrated circuit structure, with high reliability and low manufacturing cost; the power chip inside the module is electrically connected to the corresponding conductive area to form a circuit, without the need for independent pins and shells, and the required material cost is low. At the same time, the volume of the finished module is greatly reduced, and the power density is improved; the use of surface-mount power chips can also achieve different functional combinations through the use of multiple models, with higher flexibility.

[0161] In addition, the power terminals and signal terminals use pin terminals and are perpendicular to the substrate area. The semiconductor module 100 has a smaller volume and higher power density. Through the sealant filling and curing, the influence of external factors on the electrical connectors and layout of the module can be reduced, and the service life of the module can be improved. In addition, the built-in gate resistors used in the power terminals and the types of other built-in electronic components are also different, which can reduce the excessive current during the current signal transmission process, play a current limiting role, protect the power device, and avoid unnecessary switching losses caused by the absorption capacitor.

[0162] Based on the semiconductor module of the above embodiment, the second embodiment of the utility model further provides a charger.

[0163] The charger includes the semiconductor module 100 of the above embodiment, a first transformer circuit, and a second transformer circuit.

[0164] The primary end of the first transformer circuit is connected to the switch circuit of the resonant conversion primary circuit of the semiconductor module, and the secondary end of the first transformer circuit is connected to the switch circuit of the resonant conversion secondary circuit of the semiconductor module. Figure 3 As shown, the first transformer circuit is equivalent to the transformer circuit inside the resonant conversion circuit. In this application, the semiconductor module is connected to the external PCB board to connect the first transformer circuit, for example, including Figure 3 Transformers TX1, Lr2, Lr3, Cr1HE Cr2, etc. are used to form a resonant conversion circuit.

[0165] The primary end of the second transformer circuit is connected to the switch circuit of the DC conversion primary circuit of the semiconductor module, and the secondary end of the second transformer circuit is connected to the switch circuit of the DC conversion secondary circuit of the semiconductor module. Figure 3 As shown, the second transformer circuit is equivalent to the transformer circuit inside the DC conversion circuit. In this application, the semiconductor module is connected to the external PCB board to connect the second transformer circuit, for example, including Figure 3 Transformers TX2 and Lr4, etc., are used to form a DC conversion circuit.

[0166] According to the charger of the embodiment of the utility model, by adopting the semiconductor module 100 of the above embodiment, the semiconductor module 100 has a higher degree of integration, and while ensuring the charging efficiency, it can reduce the space occupied in the vehicle, and the high and low voltage insulation inside the semiconductor module 100 is high, thereby improving the charging performance.

[0167] Furthermore, a second AC transmission terminal of a switch circuit connected to a primary side circuit of a resonant conversion is provided on the first substrate area of ​​the semiconductor module 100, and a third AC transmission terminal of a switch circuit connected to a secondary side circuit of a resonant conversion is provided on the second substrate area of ​​the semiconductor module; the primary end of the first transformer circuit is connected to the second AC transmission terminal, and the secondary end of the first transformer circuit is connected to the third AC transmission terminal.

[0168] A fourth AC transmission terminal connected to the switching circuit of the DC conversion primary circuit is provided on the second substrate area of ​​the semiconductor module, and three DC pin terminals connected to the switching circuit of the DC conversion secondary circuit are provided on the third substrate area of ​​the semiconductor module; the primary end of the second transformer circuit is connected to the fourth AC transmission terminal, and the secondary end of the second transformer circuit is connected to the three DC pin terminals.

[0169] Specifically, by connecting the corresponding terminals of the semiconductor module to the external PCB, the overall circuit of the charger can be quickly and efficiently constructed, and installation is convenient.

[0170] Based on the charger of the above embodiment, the third aspect of the utility model further provides a vehicle.

[0171] The vehicle comprises a power battery and the charger of the above embodiment, and the charger is connected to the power battery to charge the power battery.

[0172] According to the vehicle of the embodiment of the utility model, by adopting the charger of the above embodiment, the charging efficiency is high and the charger occupies little space in the vehicle.

[0173] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0174] Although the embodiments of the present invention have been shown and described, those skilled in the art will appreciate that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor module, characterized in that: include: a first substrate region, a second substrate region and a third substrate region, wherein the first substrate region, the second substrate region and the third substrate region extend along the same plane, the first substrate region includes a first conductive region and a second conductive region, the second substrate region includes a third conductive region and a fourth conductive region, the third conductive region is adjacent to the second conductive region, and the fourth conductive region is adjacent to the third substrate region; a switch circuit of a power factor correction circuit, wherein the switch circuit of the power factor correction circuit is located in the first conductive area; a switching circuit of a resonant conversion circuit, wherein the switching circuit of the resonant conversion circuit comprises a switching circuit of a resonant conversion primary circuit and a switching circuit of a resonant conversion secondary circuit, wherein the switching circuit of the resonant conversion primary circuit is located in the second conductive region, and the switching circuit of the resonant conversion secondary circuit is located in the third conductive region; a switch circuit of a DC conversion circuit, wherein the switch circuit of the DC conversion circuit comprises a switch circuit of a DC conversion primary circuit and a switch circuit of a DC conversion secondary circuit, wherein the switch circuit of the DC conversion primary circuit is located in the fourth conductive area, and the switch circuit of the DC conversion secondary circuit is located on the third substrate area; A first insulating member and a second insulating member, wherein the first insulating member is located between the first substrate region and the second substrate region, and the second insulating member is located between the second substrate region and the third substrate region.

2. The semiconductor module according to claim 1, characterized in that The first substrate region, the second substrate region and the third substrate region are arranged in sequence along a first direction, the first conductive region and the second conductive region are arranged along the first direction, and the third conductive region and the fourth conductive region are arranged along the first direction.

3. The semiconductor module according to claim 2, characterized in that The semiconductor module further comprises: A bottom plate, wherein the first substrate area, the second substrate area and the second substrate area are all located on the bottom plate; An insulating frame, the insulating frame is located on the bottom plate, and the insulating frame surrounds the first substrate area, the second substrate area, and the third substrate area; The insulating frame is configured with a first spacing beam located between the first substrate area and the second substrate area and extending along a second direction perpendicular to the first direction as the first insulating member; The insulating frame is further configured with a second spacing beam located between the second substrate area and the third substrate area and extending along the second direction to serve as the second insulating member.

4. The semiconductor module according to claim 3, characterized in that A first fixed connection portion is provided on the first spacing beam, and the first fixed connection portion is used to fixedly connect the insulating frame and the plastic-encapsulated shell; The second spacing beam is provided with a second fixed connection portion, and the second fixed connection portion is used to fixedly connect the insulating frame and the plastic package shell.

5. The semiconductor module according to claim 1, characterized in that The first conductive region includes a plurality of first sub-conductive regions that are arranged at intervals along a first direction and extend along a second direction perpendicular to the first direction, wherein the plurality of first sub-conductive regions include at least one first DC conductive region, at least one first AC conductive region, and at least one second DC conductive region; The switching circuit of the power factor correction circuit includes multiple first upper bridge power chips and multiple first lower bridge power chips, the multiple first upper bridge power chips are located in the at least one first DC conductive area, the source electrodes of the multiple first upper bridge power chips are electrically connected to the at least one second DC conductive area, the multiple first lower bridge power chips are located in the at least one first AC conductive area, and the source electrodes of the multiple first lower bridge power chips are electrically connected to the at least one second DC conductive area.

6. The semiconductor module according to claim 5, characterized in that The plurality of first sub-conductive regions include one first DC conductive region, two AC conductive regions, and two second DC conductive regions, the two first AC conductive regions are located at both sides of the first DC conductive region along the first direction, and the two second DC conductive regions are located at one side of the two first AC conductive regions away from the first DC conductive region along the first direction; The switching circuit of the power factor correction circuit includes two of the first upper bridge power chips and two of the first lower bridge power chips, the two first upper bridge power chips are located in the first DC conductive area, the source electrodes of the two first upper bridge power chips are electrically connected to the two first AC conductive areas, respectively, the two first lower bridge power chips are located in the two first AC conductive areas, respectively, and the source electrodes of the two first lower bridge power chips are electrically connected to the two second DC conductive areas, respectively.

7. The semiconductor module according to claim 6, characterized in that One of the two first upper bridge power chips and one of the two first lower bridge power chips are MOS chips, and the other of the two first upper bridge power chips and the other of the two first lower bridge power chips are IGBT chips; One of the MOS chip and the IGBT chip is located in the first DC conductive area, and another of the MOS chip and another of the IGBT chip is located in two of the first AC conductive areas respectively; Two FRD chips are also provided corresponding to the two IGBT chips, one of the FRD chips is located in the first DC conductive area, and the other FRD chip is located in the first AC conductive area where the other IGBT chip is located, one end of one FRD chip is electrically connected to the first AC conductive area where the other FRD chip is located, and the other FRD chip is electrically connected to the second DC conductive area to which the other IGBT chip is connected.

8. The semiconductor module according to claim 5, characterized in that The second conductive region includes a plurality of second sub-conductive regions that are spaced apart along the first direction and extend along the second direction, and the plurality of second sub-conductive regions include at least one third DC conductive region, at least one second AC conductive region, and at least one fourth DC conductive region; The switching circuit of the resonant conversion main side circuit includes multiple second upper bridge power chips and multiple second lower bridge power chips, the multiple second upper bridge power chips are located on the at least one third DC conductive area, the source electrodes of the multiple second upper bridge power chips are respectively electrically connected to the at least one second AC conductive area, the multiple second lower bridge power chips are located on the at least one second AC conductive area, and the source electrodes of the multiple second lower bridge power chips are respectively electrically connected to the at least one fourth DC conductive area.

9. The semiconductor module according to claim 8, characterized in that The plurality of second sub-conductive regions include two third DC conductive regions, two second AC conductive regions and two fourth DC conductive regions, the two second AC conductive regions are located on both sides of the two fourth DC conductive regions along the first direction, the two third DC conductive regions are located on a side of the two second AC conductive regions away from the fourth DC conductive region along the first direction, and ends of the two third DC conductive regions close to an edge of the first substrate region extend along the first direction and surround the second AC conductive region and the fourth DC conductive region; The switching circuit of the resonant conversion main side circuit includes two second upper bridge power chips and two second lower bridge power chips, the two second upper bridge power chips are respectively located on the two third DC conductive areas, the source electrodes of the two second upper bridge power chips are respectively electrically connected to the adjacent second AC conductive areas, the two second lower bridge power chips are respectively located on the two second AC conductive areas, and the source electrodes of the two second lower bridge power chips are respectively electrically connected to the adjacent fourth DC conductive areas.

10. The semiconductor module according to claim 8, characterized in that The first substrate region includes a first side and a second side opposite to each other in the second direction; One end of the first sub-conductive region and the second sub-conductive region is close to the first edge of the first substrate region; A plurality of first source signal detection conductive areas are further formed in the first conductive area and the second conductive area, the plurality of first source signal detection conductive areas are located along the second direction on one side of the plurality of first sub-conductive areas and the plurality of second sub-conductive areas close to the second side of the first substrate area, and the plurality of first source signal detection conductive areas are arranged in sequence along the first direction; The sources of the first upper bridge power chips, the sources of the first lower bridge power chips, the sources of the second upper bridge power chips and the sources of the second lower bridge power chips are electrically connected to the corresponding first source signal detection conductive areas respectively.

11. The semiconductor module according to claim 10, characterized in that The first conductive region and the second conductive region further form a plurality of first gate signal detection conductive regions, the plurality of first gate signal detection conductive regions are located along the second direction on a side of the plurality of first source signal detection conductive regions away from the first sub-conductive region and the second sub-conductive region, the plurality of first gate signal detection conductive regions are sequentially arranged along the first direction, the plurality of first gate signal detection conductive regions are arranged one-to-one with the plurality of first source signal detection conductive regions, and a portion of the first gate signal detection conductive region extends along the second direction to a side surface of the corresponding first source signal detection conductive region; The gates of the first upper bridge power chips, the gates of the first lower bridge power chips, the gates of the second upper bridge power chips and the gates of the second lower bridge power chips are electrically connected to the corresponding first gate signal detection conductive areas respectively.

12. The semiconductor module according to claim 11, characterized in that The first substrate region further includes a third side and a fourth side opposite to each other along the first direction; The first conductive region is close to a third side of the first substrate region, and the second conductive region is close to a fourth side of the first substrate region; The second conductive area also includes a first thermal detection area, the first thermal detection area is close to the fourth side of the first substrate area along the first direction, the first thermal detection area is close to the second side of the first substrate area along the second direction, the first thermal detection area and multiple first gate signal detection conductive areas are arranged along the first direction, and the first thermal detection area is also arranged along the first direction with multiple first source signal detection conductive areas.

13. The semiconductor module according to claim 12, characterized in that Each of the first DC conductive areas and each of the third DC conductive areas is provided with a first DC transmission terminal perpendicular to the first substrate area, each of the first AC conductive areas is provided with a first AC transmission terminal perpendicular to the first substrate area, each of the second AC conductive areas is provided with a second AC transmission terminal perpendicular to the first substrate area, each of the second DC conductive areas and the fourth DC conductive areas is provided with a second DC transmission terminal perpendicular to the first substrate area, and the first DC transmission terminal, the first AC transmission terminal, the second AC transmission terminal and the second DC transmission terminal are arranged along the first direction; Each of the first source signal detection conductive regions is provided with a first source signal detection terminal perpendicular to the first substrate region to transmit a source signal; Each of the first gate signal detection conductive areas is provided with a first gate signal detection terminal perpendicular to the first substrate area to transmit a gate signal; The first thermal detection area is provided with two first thermal detection terminals for transmitting thermal detection signals; Among them, a plurality of the first source signal detection terminals and one first heat detection terminal are arranged along the first direction, and a plurality of the first gate signal detection terminals and another first heat detection terminal are arranged along the first direction.

14. The semiconductor module according to claim 1, characterized in that The third conductive region includes a plurality of third sub-conductive regions arranged at intervals along a first direction and extending along a second direction perpendicular to the first direction, wherein the plurality of third sub-conductive regions include at least one fifth DC conductive region, at least one third AC conductive region and at least one sixth DC conductive region; The switching circuit of the resonant conversion secondary circuit includes multiple third upper bridge power chips and multiple third lower bridge power chips, the multiple third upper bridge power chips are located on the at least one fifth DC conductive area, the source electrodes of the multiple third upper bridge power chips are respectively electrically connected to the at least one third AC conductive area, the multiple third lower bridge power chips are located in the at least one third AC conductive area, and the source electrodes of the multiple third lower bridge power chips are respectively electrically connected to the at least one sixth DC conductive area.

15. The semiconductor module according to claim 14, characterized in that The switch circuit of the resonant conversion secondary circuit comprises two fifth DC conductive areas, two third AC conductive areas and two sixth DC conductive areas, the two third AC conductive areas are located on both sides of the two sixth DC conductive areas along the first direction, the two fifth DC conductive areas are located on a side of the two third AC conductive areas away from the sixth DC conductive areas along the first direction, and one end of the two fifth DC conductive areas close to the edge of the second substrate area extends along the first direction and surrounds the third AC conductive areas and the sixth DC conductive areas; The switching circuit of the resonant conversion secondary circuit includes two third upper bridge power chips and two third lower bridge power chips, the two third upper bridge power chips are respectively located on the two fifth DC conductive areas, the source electrodes of the two third upper bridge power chips are respectively electrically connected to the adjacent third AC conductive areas, the two third lower bridge power chips are respectively located on the two third AC conductive areas, and the source electrodes of the two third lower bridge power chips are respectively electrically connected to the two sixth DC conductive areas.

16. The semiconductor module according to claim 14, characterized in that The second substrate region includes a first side and a second side opposite to each other along the second direction; The plurality of third sub-conductive regions are close to the first side of the second substrate region; The third conductive region further comprises a plurality of second source signal detection conductive regions, the plurality of second source signal detection conductive regions are located along the second direction on one side of the plurality of third sub-conductive regions close to the second side of the second substrate region, and the plurality of second source signal detection conductive regions are arranged along the first direction; The sources of the plurality of third upper bridge power chips and the sources of the plurality of third lower bridge power chips are electrically connected to the corresponding second source signal detection conductive areas, respectively.

17. The semiconductor module according to claim 16, characterized in that The third conductive region further includes a plurality of second gate signal detection conductive regions, the plurality of second gate signal detection conductive regions are located along the second direction on a side of the plurality of second source signal detection conductive regions away from the third sub-conductive region, the plurality of second gate signal detection conductive regions are sequentially arranged along the first direction, the plurality of second gate signal detection conductive regions are arranged in one-to-one correspondence with the plurality of second source signal detection conductive regions, and a portion of the second gate signal detection conductive region extends along the second direction to a side corresponding to the second source signal detection conductive region; The gates of the plurality of third upper bridge power chips and the gates of the plurality of third lower bridge power chips are electrically connected to the corresponding second gate signal detection conductive areas, respectively.

18. The semiconductor module according to claim 17, characterized in that The fourth conductive region includes a plurality of fourth sub-conductive regions arranged at intervals along the first direction and extending along the second direction, wherein the plurality of fourth sub-conductive regions include at least one seventh DC conductive region, at least one fourth AC conductive region and at least one eighth DC conductive region; The switching circuit of the DC conversion main side circuit includes multiple fourth upper bridge power chips and multiple fourth lower bridge power chips, the multiple fourth upper bridge power chips are located in the at least one seventh DC conductive zone, the source electrodes of the multiple fourth upper bridge power chips are respectively electrically connected to the at least one fourth AC conductive zone, the multiple fourth lower bridge power chips are located in the at least one fourth AC conductive zone, and the source electrodes of the multiple fourth lower bridge power chips are respectively electrically connected to the at least one eighth DC conductive zone.

19. The semiconductor module according to claim 18, characterized in that The plurality of fourth sub-conductive regions include two seventh DC conductive regions, two fourth AC conductive regions and two eighth DC conductive regions, the two fourth AC conductive regions are located on both sides of the two eighth DC conductive regions along the first direction, the two seventh DC conductive regions are located on a side of the two fourth AC conductive regions away from the eighth DC conductive region along the first direction, and one end of the two seventh DC conductive regions close to the first side of the second substrate region extends along the first direction and surrounds the fourth AC conductive region and the eighth DC conductive region; The switching circuit of the DC conversion main side circuit includes two fourth upper bridge power chips and two fourth lower bridge power chips, the two fourth upper bridge power chips are respectively located in the two seventh DC conductive areas, the source electrodes of the two fourth upper bridge power chips are respectively electrically connected to the adjacent fourth AC conductive areas, the two fourth lower bridge power chips are respectively located in the two fourth AC conductive areas, and the source electrodes of the two fourth lower bridge power chips are respectively electrically connected to the two eighth DC conductive areas.

20. The semiconductor module according to claim 18, characterized in that The fourth conductive area further includes a plurality of third source signal detection conductive areas and a plurality of third gate signal detection conductive areas, and the plurality of third source signal detection conductive areas are arranged in one-to-one correspondence with the plurality of third gate signal detection conductive areas; Among them, the plurality of third source signal detection conductive areas are located along the second direction on one side of the plurality of fourth sub-conductive areas close to the second side of the second substrate area, the plurality of third source signal detection conductive areas are arranged along the first direction, and the source electrodes of the plurality of fourth upper bridge power chips and the source electrodes of the plurality of fourth lower bridge power chips are electrically connected to the corresponding third source signal detection conductive areas respectively; The plurality of third gate signal detection conductive areas are located along the second direction on a side of the plurality of third source signal detection conductive areas away from the fourth sub-conductive area, the plurality of third gate signal detection conductive areas are arranged in sequence along the first direction, a portion of the third gate signal detection conductive area extends along the second direction to a side of the corresponding third source signal detection conductive area, and the gates of the plurality of fourth upper bridge power chips and the gates of the plurality of fourth lower bridge power chips are electrically connected to the corresponding third gate signal detection conductive areas, respectively.

21. The semiconductor module according to claim 20, characterized in that The second substrate region further includes a third side and a fourth side opposite to each other along the first direction; The third conductive region is close to the third side of the second substrate region, and the fourth conductive region is close to the fourth side of the second substrate region; The third conductive region further includes a second thermal detection region, the second thermal detection region is close to a third side of the second substrate region along the first direction, and the second thermal detection region is close to a second side of the second substrate region along the second direction.

22. The semiconductor module according to claim 21, characterized in that Each of the fifth DC conductive areas and each of the seventh DC conductive areas is provided with a third DC transmission terminal perpendicular to the second substrate area, each of the third AC conductive areas is provided with a third AC transmission terminal perpendicular to the second substrate area, each of the fourth AC conductive areas is provided with a fourth AC transmission terminal perpendicular to the second substrate area, each of the sixth DC conductive areas and each of the eighth DC conductive areas is provided with a fourth DC transmission terminal perpendicular to the second substrate area, and the third DC transmission terminal, the third AC transmission terminal, the fourth AC transmission terminal and the fourth DC transmission terminal are arranged along the first direction; Each of the second source signal detection conductive areas is provided with a second source signal detection terminal perpendicular to the second substrate area, each of the third source signal detection conductive areas is provided with a third source signal detection terminal perpendicular to the second substrate area, each of the second gate signal detection conductive areas is provided with a second gate signal detection terminal perpendicular to the second substrate area, each of the third gate signal detection conductive areas is provided with a third gate signal detection terminal perpendicular to the second substrate area, and the second heat detection area is provided with two second heat detection terminals perpendicular to the second substrate area; One of the second thermal detection terminals, the second source signal detection terminal and the third source signal detection terminal is arranged in sequence along the first direction, and another of the second thermal detection terminal, the second gate signal detection terminal and the third gate signal detection terminal is arranged in sequence along the first direction.

23. The semiconductor module according to claim 1, characterized in that A fifth sub-conductive region, a sixth sub-conductive region and a seventh sub-conductive region are formed on the third substrate region and are arranged in sequence along a first direction and extend along a second direction perpendicular to the first direction; The switch circuit of the secondary circuit of the DC conversion circuit includes a plurality of fifth power chips connected in parallel and a plurality of sixth power chips connected in parallel; A plurality of the fifth power chips are located in the fifth sub-conductive area, and source electrodes of the plurality of the fifth power chips are electrically connected to the sixth sub-conductive area; The plurality of sixth power chips are located in the seventh sub-conductive region, and the sources of the plurality of sixth power chips are electrically connected to the sixth sub-conductive region.

24. The semiconductor module according to claim 23, characterized in that The third substrate region includes a first side and a second side along the second direction; The third substrate region further includes: a first DC pin terminal, the first DC pin terminal being connected to the fifth sub-conductive area and extending along the second direction and being led out from a first edge of the third substrate area for transmitting a DC signal; a second DC pin terminal, the second DC pin terminal being connected to the sixth sub-conductive area and extending along the second direction and being led out from the first edge of the third substrate area for transmitting a DC signal; a third DC pin terminal, the third DC pin terminal being connected to the seventh sub-conductive region and extending along the second direction from the first edge of the third substrate region, and being used for transmitting a DC signal; The first DC pin terminal, the second DC pin terminal and the third DC pin terminal are arranged along the first direction.

25. The semiconductor module according to claim 24, characterized in that The third substrate region further includes a fourth source signal detection conductive region and a fifth source signal detection conductive region; The fourth source signal detection conductive region and the fifth source signal detection conductive region both extend along the second direction, the fourth source signal detection conductive region is located along the first direction at a side of the fifth sub-conductive region away from the sixth sub-conductive region, one end of the fourth source signal detection conductive region close to the second side of the third substrate region is bent along the first direction to a side of the fifth sub-conductive region close to the second side of the third substrate region, the fifth source signal detection conductive region is located along the first direction at a side of the seventh sub-conductive region away from the sixth sub-conductive region, and one end of the fifth source signal detection conductive region close to the second side of the third substrate region is bent along the first direction to a side of the seventh sub-conductive region close to the second side of the third substrate region; The sources of the plurality of fifth power chips are electrically connected to the fourth source signal detection conductive area, respectively, and the sources of the plurality of sixth power chips are electrically connected to the fifth source signal detection conductive area, respectively.

26. The semiconductor module according to claim 25, characterized in that A fourth gate signal detection conductive area and a fifth gate signal detection conductive area extending along the second direction are also formed on the third substrate area; The fourth gate signal detection conductive region is located along the first direction at a side of the fourth source signal detection conductive region away from the fifth sub-conductive region, and one end of the fourth gate signal detection conductive region close to the second side of the third substrate region is bent along the first direction to a side of the fourth source signal detection conductive region close to the second side of the third substrate region; The fifth gate signal detection conductive region is located along the first direction at a side of the fifth source signal detection conductive region away from the seventh sub-conductive region; A plurality of first gate resistors and a plurality of second gate resistors are also arranged on the third substrate area; Multiple first gate resistors are located in the fourth gate signal detection conductive area, and multiple first gate resistors are correspondingly connected to the gates of multiple fifth power chips. Multiple second gate resistors are located in the fifth gate signal detection conductive area, and multiple second gate resistors are correspondingly connected to the gates of multiple sixth power chips.

27. The semiconductor module according to claim 26, characterized in that A third thermal detection area is also formed on the third substrate area. The third thermal detection area is close to the second edge of the third substrate area along the second direction. The third thermal detection area is located between the bending part of the fourth source signal detection conductive area and the bending part of the fifth source signal detection conductive area along the first direction.

28. The semiconductor module according to claim 27, characterized in that The fourth source signal detection conductive area is provided with a fourth source signal detection terminal perpendicular to the third substrate area to provide a source signal of the fifth power chip; A fifth source signal detection terminal perpendicular to the third substrate region is disposed on the fifth source signal detection conductive region to provide a source signal of the sixth power chip; The fourth gate signal detection conductive area is provided with a fourth gate signal detection terminal perpendicular to the third substrate area to provide a gate signal for the fifth power chip; A fifth gate signal detection terminal perpendicular to the third substrate region is provided on the fifth gate signal detection conductive region to provide a gate signal for the sixth power chip; The third thermal detection area is provided with a third thermal detection terminal perpendicular to the third substrate area to transmit a thermal detection signal of the third substrate area; The fourth gate signal detection terminal, the fourth source signal detection terminal, the third heat detection terminal, the fifth source signal detection terminal, and the fifth gate signal detection terminal are arranged along the first direction.

29. A charger, characterized in that: include: The semiconductor module according to any one of claims 1 to 28; a first transformer circuit, wherein a primary end of the first transformer circuit is connected to a switch circuit of a resonant conversion primary circuit of the semiconductor module, and a secondary end of the first transformer circuit is connected to a switch circuit of a resonant conversion secondary circuit of the semiconductor module; A second transformer circuit, wherein the primary end of the second transformer circuit is connected to the switch circuit of the DC conversion primary circuit of the semiconductor module, and the secondary end of the second transformer circuit is connected to the switch circuit of the DC conversion secondary circuit of the semiconductor module.

30. The charger according to claim 29, characterized in that: A second AC transmission terminal connected to the switch circuit of the resonant conversion primary circuit is provided on the first substrate area of ​​the semiconductor module, and a third AC transmission terminal connected to the switch circuit of the resonant conversion secondary circuit is provided on the second substrate area of ​​the semiconductor module; The primary end of the first transformer circuit is connected to the second AC transmission terminal, and the secondary end of the first transformer circuit is connected to the third AC transmission terminal; A fourth AC transmission terminal connected to the switch circuit of the DC conversion primary circuit is provided on the second substrate area of ​​the semiconductor module, and three DC pin terminals connected to the switch circuit of the DC conversion secondary circuit are provided on the third substrate area of ​​the semiconductor module; The primary end of the second transformer circuit is connected to the fourth AC transmission terminal, and the secondary end of the second transformer circuit is connected to the three DC pin terminals.

31. A vehicle, characterized in that: It comprises a power battery and the charger according to claim 29 or 30, wherein the charger is connected to the power battery.

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