Power semiconductor device
By adopting a multi-trench structure in power semiconductor devices and filling the insulating layer, the problems of increased inter-electrode resistance and manufacturing difficulty are solved, and higher reliability and yield are achieved.
Patent Information
- Application Number
- CN202420880364.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-25
- Publication Date
- 2025-01-14
- Estimated Expiration
- 2034-04-25
AI Technical Summary
In power semiconductor devices, as the cell density increases, the inter-electrode resistance increases, switching losses increase, and the gate conductor is higher than the substrate surface, resulting in increased difficulty in planarization and lithography processes, which are prone to parameter failure and reliability risks .
Design a power semiconductor device, adopting a multiple trench structure, wherein the lower part of the second trench is completely filled with the second insulating layer, avoiding leakage and short circuit between the gate wiring and the shielding conductor, and reducing the width and depth of the trench Manufacturing difficulty and cost to improve device reliability.
It effectively avoids gate-source and drainage and short circuits, reduces parameter failure, improves the yield and reliability of the device, reduces contact resistance, and optimizes the structure and manufacturing process of power semiconductor devices.
Smart Images
Figure CN222356844U_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular to a power semiconductor device. Background Art
[0002] In power semiconductor devices, lower conduction loss and switching loss are important indicators for evaluating device performance. The trench process changes the channel from horizontal to vertical, eliminating the influence of the parasitic JFET resistance of the planar structure, greatly reducing the cell size, and on this basis increasing the cell density and the total width of the channel per unit area, which can increase the channel width-to-length ratio of the device on a unit silicon wafer, thereby increasing the current, reducing the on-resistance, and optimizing related parameters, achieving the goal of having a smaller die with greater power and higher performance. Therefore, the trench process is increasingly used in new power semiconductor devices.
[0003] As the cell density increases, the inter-electrode resistance will increase, and the switching loss will increase accordingly, among which the gate-drain capacitance Cgd is directly related to the switching characteristics of the device. The SGT (Split Gate Trench) structure reduces the gate-drain capacitance Cgd, improves the switching speed, and reduces the switching loss because the gate conductor extends to the drift region and the gate conductor and the drain are separated by a thick oxide layer. At the same time, due to the special structure of SGT, the shielding conductor under the gate conductor and the source are usually connected together and grounded together, introducing a charge balance effect, so that the vertical direction of the device has a RESURF (Reduced SURface Field) effect, further reducing the on-resistance Rdson and reducing the conduction loss.
[0004] In the prior art, the gate conductor is higher than the substrate surface. When the trench width is reduced to a certain size, this structure will increase the difficulty of the subsequent planarization process and photolithography process, and easily cause parameter failure, resulting in low yield and reliability risks. How to reduce photolithography, reduce manufacturing costs, and optimize the structure and manufacturing process of power semiconductor devices is the content that people in this technical field need to study. Utility Model Content
[0005] In view of the above problems, an object of the present invention is to provide a power semiconductor device to improve the reliability of the device.
[0006] According to one aspect of the present invention, a power semiconductor device is provided, comprising: a semiconductor substrate of a first doping type; a plurality of trenches located in the semiconductor substrate, the plurality of trenches comprising a first trench located in a first region, a second trench in a second region, and a third trench in a third region of the semiconductor substrate, the width of the first trench being greater than the width of the second trench and the width of the third trench being greater than the width of the second trench; a shielding conductor located in a lower portion of the first trench, the shielding conductor and the semiconductor substrate being isolated via a shielding dielectric layer; a gate conductor located in an upper portion of the first trench, the gate conductor and the semiconductor substrate being isolated via a gate dielectric layer, and the gate conductor and the shielding conductor being isolated via a first insulating layer; a second insulating layer filling the lower portion of the second trench; A gate wiring, located at the upper part of the second groove, the gate wiring and the semiconductor substrate are isolated by the gate dielectric layer; a shielding wiring, located in the third groove, the shielding wiring is isolated from the semiconductor substrate by the shielding dielectric layer, and the shielding wiring is electrically connected to the shielding conductor; a body region, located in the semiconductor substrate, the body region is adjacent to the upper part of the first groove, the second groove and the third groove, and is of a second doping type, and the second doping type is opposite to the first doping type; a source region, located in the body region of the first region, the source region is of a first doping type; a source electrode, electrically connected to the source region; a gate electrode, electrically connected to the gate wiring; a shielding electrode, electrically connected to the shielding wiring; and a drain electrode, located on a side surface of the semiconductor substrate away from the body region.
[0007] Optionally, the depth of the second groove is smaller than the depth of the first groove and the depth of the second groove is smaller than the depth of the third groove.
[0008] Optionally, a width of the second groove is less than or equal to twice the thickness of the shielding dielectric layer.
[0009] Optionally, the width of the first groove and the third groove is 0.1 micron to 5 microns, and the depth is 0.5 micron to 20 microns; the width of the second groove is 0.1 micron to 4 microns, and the depth is 0.5 micron to 18 microns.
[0010] Optionally, the thickness of the shielding dielectric layer in the first trench is 300 angstroms to 20,000 angstroms.
[0011] Optionally, the gate dielectric layer covers the upper sidewalls of the first trench and the upper sidewalls of the second trench; the gate conductor is flush with the surface of the semiconductor substrate, and the gate wiring is flush with the surface of the semiconductor substrate.
[0012] Optionally, the gate dielectric layer covers the upper side wall of the first trench, the surface of the semiconductor substrate in the first region, the upper side wall of the second trench and the surface of the semiconductor substrate in the second region; the gate conductor is flush with the surface of the gate dielectric layer on the semiconductor substrate, and the gate wiring is flush with the surface of the gate dielectric layer on the semiconductor substrate.
[0013] Optionally, it also includes a first contact region, a second contact region and a third contact region, the first contact region is located in the body region and the source region of the first region, the second contact region is located in the gate wiring, and the third contact region is located in the shielding wiring; the source electrode is electrically connected to the source region via the first contact region; the gate electrode is electrically connected to the gate wiring via the second contact region; and the shielding electrode is electrically connected to the shielding wiring via the third contact region.
[0014] Optionally, it also includes an interlayer dielectric layer, which is located above the semiconductor substrate, above the gate conductor, above the gate wiring and above the shielding wiring, and the source electrode, the gate electrode and the shielding electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first contact area, the second contact area and the third contact area.
[0015] Optionally, the source electrode is located in the first region, the gate electrode is located in the second region, the shielding electrode is located in the third region, and the source electrode, the gate electrode and the shielding electrode are separated from each other.
[0016] In the power semiconductor device provided by the embodiment of the utility model, the lower part of the second trench is completely filled with the second insulating layer, and the second insulating layer replaces the shielding conductor structure in the traditional technology, thereby avoiding gate-source leakage and gate-source short circuit between the gate wiring at the upper part of the second trench and the shielding conductor at the lower part of the second trench, thereby improving reliability.
[0017] Furthermore, the width of the second groove is smaller than the width of the first groove and the width of the second groove is smaller than the width of the third groove. By setting the width of the second groove to be narrower, the lower part of the second groove is filled with the second insulating layer, so that there is no extra space in the lower part of the second groove to form a shielding conductor, thereby avoiding gate-source leakage and gate-source short circuit, reducing parameter failures, and improving yield and reliability.
[0018] Furthermore, the source electrode, gate electrode and shield electrode are electrically connected to the source region, gate wiring and shield wiring via the first contact region, the second contact region and the third contact region respectively, which can reduce contact resistance and enhance EAS (single pulse avalanche breakdown energy).
[0019] Furthermore, the width of the second trench is less than or equal to twice the thickness of the shielding dielectric layer, so as to ensure that the lower portion of the second trench is completely filled with the second insulating layer (shielding dielectric layer).
[0020] Furthermore, by back-etching the second insulating layer in the second trench, a gate wiring is formed on the upper portion of the second trench, and the gate wiring is further located inside the second trench. Compared with the conventional technology of arranging the gate wiring in the area above the semiconductor substrate, this embodiment can further reduce the size of the device.
[0021] Furthermore, the gate wiring is placed on the top of the second groove, which reduces the number of lithography times, reduces manufacturing costs, optimizes the power semiconductor device structure and manufacturing process, reduces the difficulty of the manufacturing process, reduces parameter failures, and improves yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The above and other purposes, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
[0023] Figure 1a A schematic cross-sectional view of a power semiconductor device according to an embodiment of the present application is shown;
[0024] Figure 1b for Figure 1a A partial enlarged view of the second groove;
[0025] Figures 2a to 2j The cross-sectional views at various stages in the preparation process of the power semiconductor device according to the embodiment of the present application are shown. DETAILED DESCRIPTION
[0026] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.
[0027] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art of the technical field of the present utility model. The terms used in the specification of this disclosure are only for the purpose of describing specific embodiments and are not intended to limit this disclosure. The term "and / or" used in this disclosure includes any and all combinations of one or more related listed items.
[0028] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.
[0029] Unless otherwise specified below, the various layers or regions of the semiconductor device may be formed of materials known to those skilled in the art. Semiconductor materials include, for example, III-V semiconductors, such as gallium arsenide (GaAs), gallium nitride (GaN), etc., IV-IV semiconductors, such as silicon carbide (SiC), etc., II-VI compound semiconductors, such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and IV semiconductors, such as silicon (Si), germanium (Ge), etc. The gate conductor may be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials, such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer may be made of SiO2 or a material with a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, and titanates. Furthermore, the gate dielectric may be formed not only of materials known to those skilled in the art, but also of materials to be developed in the future for use as gate dielectrics.
[0030] In the present disclosure, the term "semiconductor structure" refers to a general term for the entire semiconductor structure formed in various steps of manufacturing a semiconductor device, including all layers or regions that have been formed.
[0031] The specific implementation of the present disclosure is further described in detail below in conjunction with the drawings and examples.
[0032] Figure 1a A schematic cross-sectional view of a power semiconductor device according to an embodiment of the present application is shown. Figure 1b for Figure 1aA partial enlarged view of the second groove in FIG. Figure 1a and Figure 1b As shown, the power semiconductor device includes a semiconductor substrate 201 and a first trench 220 a located in a first region z21 , a second trench 220 b located in a second region z22 , and a third trench 220 c located in a third region z23 of the semiconductor substrate 201 .
[0033] The semiconductor substrate 201 may be a silicon substrate, a germanium silicon substrate, a III-V group element compound substrate, or other semiconductor material substrates known to those skilled in the art. In this embodiment, a silicon substrate is used. More specifically, semiconductor devices such as MOS field effect transistors, IGBT insulated gate bipolar transistors, and Schottky diodes may be formed in the semiconductor substrate used in this embodiment. The semiconductor substrate 201 has a first doping type. The first doping type is one of N-type and P-type, and the second doping type is the other of N-type and P-type. In this embodiment, the first doping type is, for example, N-type doping.
[0034] The semiconductor substrate 201 has a first surface and a second surface opposite to each other, and the first to third trenches 220a to 220c extend from the first surface of the semiconductor substrate 201 to the inside thereof, and reach a predetermined depth in the semiconductor substrate 201. The widths of the first to third trenches 220a to 220c are determined according to the structure and process capability of the product, and the depths are matched according to parameters such as epitaxy, withstand voltage, doping, and gate oxide thickness of the product. In this embodiment, the first trench 220a and the third trench 220c have the same width and depth, the width of the second trench 220b is smaller than the width of the first trench 220a, and the width of the second trench 220b is smaller than the width of the third trench 220c; further, the depth of the second trench 220b is shallower than the depth of the first trench 220a, and the depth of the second trench 220b is shallower than the depth of the third trench 220c.
[0035] In one embodiment, the width of the first trench 220a and the third trench 220c is 0.1 micrometer to 5 micrometers, and the depth is 0.5 micrometer to 20 micrometers; the width of the second trench 220b is 0.1 micrometer to 4 micrometers, and the depth is 0.5 micrometer to 18 micrometers.
[0036] Furthermore, a gate conductor 224a and a shield conductor 222a are formed in the first trench 220a, a gate wiring 224b is formed in the second trench 220b, and a shield wiring 222b is formed in the third trench 220c.
[0037] Specifically, the first trench 220a includes a shielding dielectric layer 221a located at the bottom and lower side wall of the first trench 220a, a shielding conductor 222a located at the lower portion of the first trench 220a, a gate dielectric layer 2231 located at the upper side wall of the first trench 220a, a gate conductor 224a located at the upper portion of the first trench 220a, and a first insulating layer 2232 between the gate conductor 224a and the shielding conductor 222a. The shielding conductor 222a is isolated from the semiconductor layer substrate 201 via the shielding dielectric layer 221a, the gate conductor 224a is isolated from the semiconductor substrate 201 via the gate dielectric layer 2231, and the shielding conductor 222a is isolated from the gate conductor 224a via the first insulating layer 2232.
[0038] In this embodiment, the shielding conductor 222a includes a first portion surrounded by the shielding dielectric layer 221a and a second portion higher than the shielding dielectric layer 221a. The first insulating layer 2232 covers the top and sidewalls of the second portion of the shielding conductor 222a. The top of the shielding conductor 222a is at a certain distance from the top of the first trench 220a. The gate conductor 224a is located at the upper portion of the first trench 220a and covers the first insulating layer 2232, and is isolated from the shielding conductor 222a by the first insulating layer 2232.
[0039] The second trench 220b includes a second insulating layer 221b filling the lower portion of the second trench 220b, a gate dielectric layer 2231 located on the upper side wall of the second trench 220b, and a gate wiring 224b located on the upper portion of the second trench 220b. The gate wiring 224b is isolated from the semiconductor substrate 201 via the gate dielectric layer 2231 in the second trench 220b and the second insulating layer 221b in the second trench 220b.
[0040] The third trench 220c includes a shielding dielectric layer 221c located at the bottom and sidewalls of the third trench 220c and a shielding wiring 222b located in the third trench 220c. The shielding wiring 222b is isolated from the semiconductor substrate 201 via the shielding dielectric layer 221c.
[0041] The power semiconductor device includes a body region 250 of a second doping type and a source region 260 of a first doping type, wherein the second doping type is opposite to the first doping type. The body region 250 is located in the semiconductor substrate 201, extending downward from the first surface of the semiconductor layer substrate 201, the body region 250 is located in the first region z21, the second region z22 and the third region z23, and is adjacent to the sidewalls of the first trench 220a, the second trench 220b and the third trench 220c, respectively, and the source region 260 is located in the body region 250 of the first region z21.
[0042] The power semiconductor device includes an interlayer dielectric layer 270, a source electrode 281, a gate electrode 282, and a shielding electrode 283. The interlayer dielectric layer 270 covers the first surface of the semiconductor substrate 201. The power semiconductor device also includes first to third contact regions 271 to 273, wherein the first contact region 271 is located in the body region 250 and the source region 260 of the first region z21. The second contact region 272 is located in the gate wiring 224b, and the third contact region 273 is located in the shielding wiring 222c. The source electrode 281 penetrates the interlayer dielectric layer 270, extends to the first contact region 271 in the first region z21, and is electrically connected to the source region 260 in the first region z21 via the first contact region 271; the gate electrode 282 penetrates the interlayer dielectric layer 270, extends to the second contact region 272 in the second region z22, and is electrically connected to the gate wiring 224b in the second region z22 via the second contact region 272; the shielding electrode 283 penetrates the interlayer dielectric layer 270, extends to the third contact region 273 in the third region z23, and is electrically connected to the shielding wiring 222b in the third region z23 via the third contact region 273. The first contact region 271, the second contact region 272, and the third contact region 273 can reduce the contact resistance and enhance the EAS (single pulse avalanche breakdown energy).
[0043] Although not shown, it should be known that the power semiconductor device of this embodiment further includes a drain electrode, which is located on the second surface of the semiconductor substrate 201 (the surface away from the body region 250 ).
[0044] It should be noted that although Figure 1a In the embodiment, the shield conductor 222a and the shield wiring 222b in different grooves are isolated from each other, and the gate conductor 224a and the gate wiring 224b are isolated from each other. However, in an actual power semiconductor device, the shield conductor 222a and the shield wiring 222b in the above-mentioned different grooves are connected to each other, and the gate conductor 224a and the gate wiring 224b are connected to each other.
[0045] Furthermore, in the present embodiment, the gate dielectric layer 2231 covers the upper side wall of the first trench 220a, the first surface of the semiconductor substrate 201 in the first region, the upper side wall of the second trench 220b and the first surface of the semiconductor substrate 201 in the second region; the top of the gate wiring 224b is flush with the surface of the gate dielectric layer 2231 on the semiconductor substrate 201, and the top of the gate conductor 224a is flush with the surface of the gate dielectric layer 2231 on the semiconductor substrate 201.
[0046] In other embodiments, the gate dielectric layer 2231 covers the upper sidewalls of the first trench 220a and the upper sidewalls of the second trench 220b; the top of the gate wiring 224b is flush with the first surface of the semiconductor substrate 201, and the top of the gate conductor 224a is flush with the first surface of the semiconductor substrate 201.
[0047] In this embodiment, the lower portion of the second trench 220b is completely filled with the second insulating layer 221b, and the second insulating layer 221b replaces the shielding conductor structure in the traditional technology, thereby avoiding gate-source leakage and gate-source short circuit between the gate wiring 224a at the upper portion of the second trench 220b and the shielding conductor at the lower portion of the second trench 220b, thereby improving reliability.
[0048] Furthermore, the width of the second trench 220b is less than or equal to twice the thickness of the shielding dielectric layer 221a, so as to ensure that the second trench 220b is completely filled with the shielding dielectric layer 221a (second insulating layer 221b).
[0049] Figures 2a to 2j The cross-sectional views of various stages in the preparation process of the power semiconductor device of the embodiment of the utility model are shown. Figures 2a to 2j The preparation method of the power semiconductor device according to the embodiment of the utility model is described.
[0050] like Figure 2a As shown, first to third trenches 220 a to 220 c are formed in the first region z21 to the third region z23 of the semiconductor substrate 201 , respectively.
[0051] The semiconductor substrate 201 has a first surface and a second surface relative to each other, and the first to third grooves 220a to 220c extend downward from the first surface of the semiconductor substrate 201 and reach a predetermined depth in the semiconductor substrate 201. The width of the first to third grooves 220a to 220c is determined according to the structure and process capability of the product, and the depth is matched according to parameters such as epitaxy, withstand voltage, doping, and gate oxide thickness of the product. In this embodiment, the first groove 220a and the third groove 220c have the same width w20a, and the width w20b of the second groove 220b is smaller than the width w20a of the first groove 220a and the third groove 220c. Further, the first groove 220a to the third groove 220c are formed by the same etching process. According to the characteristics of the etching process, the depth h20b of the second groove 220b is shallower than the depth h20a of the first groove 220a and the third groove 220c.
[0052] In one embodiment, the width w20a of the first trench 220a and the third trench 220c is 0.1 micron to 5 microns, and the depth h20a is 0.5 micron to 20 microns; the width w20b of the second trench 220b is 0.1 micron to 4 microns, and the depth h20b is 0.5 micron to 18 microns.
[0053] Furthermore, a width w20a of the second trench 220b is less than or equal to twice the thickness of the insulating layer 221 formed in a subsequent step.
[0054] like Figure 2b As shown, an insulating layer 221 is formed on the first surface of the semiconductor substrate 201 and the inner walls of the first to third trenches 220 a to 220 c .
[0055] The insulating layer 221 can be made of undoped silicon dioxide, silicon nitride, silicon oxynitride, etc., or a combination of silicon oxide, silicon nitride, silicon oxynitride, etc. The thickness of the insulating layer 221 needs to be matched with the epitaxy, withstand voltage, doping, trench depth, etc. of the product.
[0056] The process for forming the insulating layer 221 includes an oxidation growth process, a CVD (Chemical Vapor Deposition) process, and the like, specifically including one or more combinations of a LPCVD (Low Pressure Chemical Vapor Deposition) process, a SACVD (Sub Atmospheric Chemical Vapor Deposition) process, a HTO (High Temperature Oxidation) process, and a SRO (Selective Reactive Oxidation) process.
[0057] In one embodiment, the insulating layer 221 is a silicon oxide layer, and is formed by a thermal oxidation growth process. The thickness of the insulating layer 221 is 300 angstroms to 20,000 angstroms.
[0058] After forming the insulating layer 221, a cavity 241a is formed in the first trench 220a and the third trench 220c. Since the width w20a of the second trench 220b is less than or equal to twice the thickness of the insulating layer 221, the second trench 220b is filled with the insulating layer 221, and the top of the second trench 220b is closed to form a recessed portion 241b.
[0059] like Figure 2cAs shown, for example, a deposition process is used to form the first polysilicon layer 222. The first polysilicon layer 222 is located on the insulating layer 221 and fills the cavity 241a and the recessed portion 241b.
[0060] In one embodiment, the first polysilicon layer 222 is made of in-situ doped polysilicon with a sheet resistance of 3 ohm to 20 ohm and a thickness of 500 angstroms to 20,000 angstroms. The deposition temperature for forming the first polysilicon layer 222 is 500° C. to 580° C.
[0061] like Figure 2d As shown, the first polysilicon layer 222 and a portion of the insulating layer 221 above the semiconductor substrate 201 are removed.
[0062] The process of removing the first polysilicon layer 222 and part of the insulating layer 221 includes a combination of one or more methods of dry etching, wet etching, and CMP (Chemical Mechanical Polishing) process. In one embodiment, the first polysilicon layer 222 and part of the insulating layer 221 are removed by using a CMP process and a dry etching process. In other embodiments, only a dry etching process may be used to remove the first polysilicon layer 222 and part of the insulating layer 221.
[0063] After removing the first polysilicon layer 222 and part of the insulating layer 221, a certain thickness of the insulating layer 221 is retained above the semiconductor substrate 201 to serve as an etching mask for removing the first polysilicon layer 222 in the first trench 220a in a subsequent step. In one embodiment, the thickness of the insulating layer 221 retained above the semiconductor substrate 201 is 100 angstroms to 2000 angstroms. After removing the first polysilicon layer 222 and part of the insulating layer 221 above the semiconductor substrate 201, the tops of the first polysilicon layer 222 and the insulating layer 221 in the first trench 220a and the third trench 220c are flush.
[0064] like Figure 2e As shown, a patterned mask layer 228 is formed by photolithography and etching, and the mask layer 228 covers the third region z23 of the semiconductor substrate 201 and exposes the first region z21 and the second region z22 of the semiconductor substrate 201. The first polysilicon layer 222 exposed by the opening of the mask layer 228 is etched to remove part of the first polysilicon layer 222 in the first trench 220a. In this embodiment, the mask layer 228 is, for example, a photoresist mask layer. There is no first polysilicon layer 222 in the second trench 220b, so only a part of the first polysilicon layer 222 in the first trench 220a is removed.
[0065] The process of removing the first polysilicon layer 222 includes a combination of dry etching, wet etching, or one or more etching methods.
[0066] For the follow-up Figure 2f The etching depth of the insulating layer 221 in the step shown in the figure reaches the expected depth. In this embodiment, the first polysilicon layer 222 in the first trench 220a is first etched. The etching depth h21 of the first polysilicon layer 222 needs to be determined in combination with the subsequent etching. Figure 2f The etching depth of the insulating layer 221 in the step shown is determined by: In one embodiment, the etching depth h21 of the first polysilicon layer 222 is 0.2 micrometers to 3 micrometers.
[0067] In this embodiment, since the second trench 220 b is filled with the insulating layer 221 , the etching of the first polysilicon layer 222 in the first trench 220 a will not affect the second trench 220 b .
[0068] like Figure 2f As shown, the exposed insulating layer 221 is etched through the opening of the mask layer 228 to remove portions of the insulating layer 221 in the first trench 220 a and the second trench 220 b .
[0069] in, Figure 2f After the steps shown, a portion of the insulating layer 221 in the first trench 220a is removed, and the remaining insulating layer 221 covers the bottom and lower sidewall of the first trench 220a to form a shielding dielectric layer 221a; the first polysilicon layer 222 in the first trench 220a forms a shielding conductor 222a, and a cavity 242a is formed in the upper part of the first trench 220a. A portion of the insulating layer 221 in the second trench 220b is removed, and the remaining insulating layer 221 fills the lower part of the second trench 220b to form a second insulating layer 221b, and a cavity 242b is formed in the upper part of the second trench 220b. The insulating layer 221 and the first polysilicon layer 222 in the third trench 220c are retained, and the insulating layer 221 retained in the third trench 220c forms a shielding dielectric layer 221c, and the first polysilicon layer 222 retained in the third trench 220c forms a shielding wiring 222b.
[0070] Furthermore, the etching depth of the insulating layer 221 in the first trench 220a is h22a, and the etching depth of the insulating layer 221 in the second trench 220b is h22b, and usually h22b≤h22a. In one embodiment, h22a and h22b are 0.3 micrometers to 0.5 micrometers.
[0071] Furthermore, after forming the cavities 242 a and 242 b , the mask layer 228 is removed.
[0072] like Figure 2g As shown, a gate dielectric layer 2231 and a first insulating layer 2232 are formed.
[0073] In this step, for example, an oxidation growth process is used to form a gate dielectric layer 2231 and a first insulating layer 2232. In the first region z21, the gate dielectric layer 2231 covers the surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the first trench 220a; the first insulating layer 2232 covers the top and exposed sidewalls of the shielding conductor 222a in the first trench 220a. In the second region z21, the gate dielectric layer 2231 covers the surface of the semiconductor substrate 201 and the sidewalls of the upper portion of the second trench 220b.
[0074] In this embodiment, the gate dielectric layer 2231 and the first insulating layer 2232 are formed simultaneously. Due to the characteristics of polycrystalline silicon, the thickness of the first insulating layer 2232 grown on the surface of the shield conductor 222a (polycrystalline silicon) under the same conditions is thicker than the thickness of the gate dielectric layer 2231 grown on the surface of the semiconductor substrate 201 (silicon) and the sidewalls of the first trench 220a and the second trench 220b (silicon). Further, the thickness of the first insulating layer 2232 is generally more than twice the thickness of the gate dielectric layer 2231. In one embodiment, the thickness of the gate dielectric layer 2231 is 50 angstroms to 1000 angstroms.
[0075] like Figure 2h As shown, a gate conductor 224a and a shield wiring 224b are formed.
[0076] In this step, for example, a deposition process is used to form a second polysilicon layer, which fills the cavity 242a and the cavity 242b and covers the surface of the gate dielectric layer 2231 and the shielding dielectric layer 221c above the semiconductor substrate 201. Next, the second polysilicon layer on the surface of the gate dielectric layer 2231 and the shielding dielectric layer 221c above the semiconductor substrate 201 is removed, and the remaining second polysilicon layer in the first trench 220a forms a gate conductor 224a, and the remaining second polysilicon layer in the second trench 220b forms a gate wiring 224b. The surface of the gate conductor 224a and the gate wiring 224b is flush with the surface of the gate dielectric layer 2231.
[0077] The second polysilicon layer is made of in-situ doped polysilicon with a sheet resistance of 3 ohm to 20 ohm and a thickness of 500 angstroms to 20,000 angstroms. The deposition temperature for forming the second polysilicon layer is 500° C. to 580° C.
[0078] The process of removing the second polysilicon layer includes a combination of one or more methods of dry etching, wet etching, and CMP (Chemical Mechanical Polishing) process. In one embodiment, the second polysilicon layer is removed by using a CMP process and a dry etching process. In other embodiments, the second polysilicon layer may also be removed by only using a dry etching process.
[0079] like Figure 2iAs shown, a body region 250 is formed in a semiconductor substrate 201 , and a source region 260 is formed in the body region 250 .
[0080] The process for forming the body region 250 and the source region 260 is, for example, ion implantation. Different types of doped regions are formed by selecting appropriate dopants for implantation, and then thermal annealing is performed to activate the impurities. In the ion implantation, the gate conductor 224a, the gate wiring 224b and the shield wiring 222b are used as hard masks to define the lateral positions of the body region 250 and the source region 260, thereby eliminating the need for a photoresist mask. By controlling the energy of the ion implantation, the implantation depth of the body region 250 and the source region 260 can be defined. The body region 250 is of the second doping type, and the source region 260 is of the first doping type.
[0081] like Figure 2j As shown, an interlayer dielectric layer 270 and a source electrode 281 , a gate electrode 282 and a shielding electrode 283 are formed.
[0082] In this step, an interlayer dielectric layer 270 is formed to cover the surface of the semiconductor structure. Specifically, the interlayer dielectric layer 270 covers the gate dielectric layer 2231, the shielding dielectric layer 221c, and the gate conductor 224a, the gate wiring 224b, and the shielding wiring 222c in the groove on the first surface of the semiconductor substrate 201. Next, a plurality of contact holes reaching the source region 260, the gate wiring 224b, and the shielding wiring 222b are formed in the interlayer dielectric layer 270. The process for forming the contact holes is, for example, dry etching.
[0083] In the first region z21 of the semiconductor substrate 201, the contact hole sequentially passes through the interlayer dielectric layer 270 and the gate dielectric layer 2231, and extends to the junction of the body region 250 and the source region 260. In the second region z22 of the semiconductor substrate 201, the contact hole passes through the interlayer dielectric layer 270, and extends to a predetermined depth in the gate wiring 224b. In the third region z23 of the semiconductor substrate 201, the contact hole passes through the interlayer dielectric layer 270, and extends to a predetermined depth in the shield wiring 222b.
[0084] Next, ion implantation is performed to form first to third contact regions 271 to 273 at the bottom of the plurality of contact holes. In the ion implantation, the interlayer dielectric layer 270 is used as a hard mask to define the lateral positions of the first to third contact regions 271 to 273, thereby eliminating the need for a photoresist mask.
[0085] Next, a source electrode 281, a gate electrode 282, and a shield electrode 283 are formed. This step includes, for example, depositing a metal layer and patterning. The metal layer is, for example, composed of one selected from Ti, TiN, TiSi, W, Al, AlSi, AlSiCu, Cu, Ni, or an alloy thereof. The metal layer is patterned into a source electrode 281, a gate electrode 282, and a shield electrode 283 by etching. The source electrode 281, the gate electrode 282, and the shield electrode 283 are isolated from each other.
[0086] In the first region z21 of the semiconductor substrate 201, the source electrode 281 is electrically connected to the source region 260 via the first contact region 271. In the second region z22 of the semiconductor substrate 201, the gate electrode 282 is electrically connected to the gate wiring 224b via the second contact region 272. In the third region z23 of the semiconductor substrate 201, the shielding electrode 283 is electrically connected to the shielding wiring 222b via the third contact region 273.
[0087] Furthermore, according to the needs of the product, a passivation layer can be added to protect the front structure of the power semiconductor device. After a series of post-processing such as thinning, back gold, and dicing, the final structure of the device is completed.
[0088] It should be noted that although in the above-mentioned cross-sectional view, the shielding conductor 222a and the shielding wiring 222b in different grooves are isolated from each other, and the gate conductor 224a and the gate wiring 224b are isolated from each other, however, in an actual power semiconductor device, from the perspective of the planar structure, the shielding conductor 222a and the shielding wiring 222b in the above-mentioned different grooves can be connected to each other, and the gate conductor 224a and the gate wiring 224b can also be connected to each other.
[0089] The embodiments of the present invention are described above, and these embodiments do not describe all the details in detail, nor do they limit the present invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modifications based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.
Claims
1. A power semiconductor device, characterized in that: include: a semiconductor substrate of a first doping type; A plurality of trenches located in the semiconductor substrate, the plurality of trenches comprising a first trench located in a first region, a second trench located in a second region, and a third trench located in a third region of the semiconductor substrate, the width of the first trench being greater than the width of the second trench and the width of the third trench being greater than the width of the second trench; A shielding conductor, located at a lower portion of the first trench, wherein the shielding conductor and the semiconductor substrate are isolated via a shielding dielectric layer; A gate conductor, located at an upper portion of the first trench, wherein the gate conductor is isolated from the semiconductor substrate via a gate dielectric layer, and the gate conductor is isolated from the shielding conductor via a first insulating layer; a second insulating layer filling a lower portion of the second trench; A gate wiring, located at an upper portion of the second trench, wherein the gate wiring and the semiconductor substrate are isolated via the gate dielectric layer; a shielding wiring, located in the third groove, the shielding wiring being isolated from the semiconductor substrate via the shielding dielectric layer, and the shielding wiring being electrically connected to the shielding conductor; a body region located in the semiconductor substrate, the body region being adjacent to upper portions of the first trench, the second trench and the third trench, and being of a second doping type, the second doping type being opposite to the first doping type; A source region, located in the body region of the first region, the source region being of a first doping type; a source electrode, electrically connected to the source region; a gate electrode electrically connected to the gate wiring; a shielding electrode electrically connected to the shielding wiring; as well as The drain electrode is located on a surface of the semiconductor substrate that is away from the body region.
2. The power semiconductor device according to claim 1, wherein: The depth of the second trench is smaller than that of the first trench and the depth of the second trench is smaller than that of the third trench.
3. The power semiconductor device according to claim 1, wherein: The width of the second trench is less than or equal to twice the thickness of the shielding dielectric layer.
4. The power semiconductor device according to claim 2, wherein: The width of the first groove and the third groove is 0.1 micron to 5 microns, and the depth is 0.5 micron to 20 microns; the width of the second groove is 0.1 micron to 4 microns, and the depth is 0.5 micron to 18 microns.
5. The power semiconductor device according to claim 3, wherein: The thickness of the shielding dielectric layer in the first trench is 300 angstroms to 20,000 angstroms.
6. The power semiconductor device according to claim 1, characterized in that: The gate dielectric layer covers the upper sidewall of the first trench and the upper sidewall of the second trench; The gate conductor is flush with the surface of the semiconductor substrate, and the gate wiring is flush with the surface of the semiconductor substrate.
7. The power semiconductor device according to claim 1, characterized in that: The gate dielectric layer covers the upper sidewall of the first trench, the surface of the semiconductor substrate in the first region, the upper sidewall of the second trench and the surface of the semiconductor substrate in the second region; The gate conductor is flush with the surface of the gate dielectric layer on the semiconductor substrate, and the gate wiring is flush with the surface of the gate dielectric layer on the semiconductor substrate.
8. The power semiconductor device according to claim 1, wherein: It also includes a first contact region, a second contact region and a third contact region, wherein the first contact region is located in the body region and the source region of the first region, the second contact region is located in the gate wiring, and the third contact region is located in the shield wiring; The source electrode is electrically connected to the source region via the first contact region; The gate electrode is electrically connected to the gate wiring via the second contact region; The shield electrode is electrically connected to the shield wiring via the third contact region.
9. The power semiconductor device according to claim 8, wherein: It also includes an interlayer dielectric layer, which is located above the semiconductor substrate, above the gate conductor, above the gate wiring and above the shielding wiring, and the source electrode, the gate electrode and the shielding electrode respectively penetrate the interlayer dielectric layer and are electrically connected to the first contact area, the second contact area and the third contact area.
10. The power semiconductor device according to claim 1, wherein: The source electrode is located in the first region, the gate electrode is located in the second region, the shield electrode is located in the third region, and the source electrode, the gate electrode, and the shield electrode are separated from each other.