Display substrate and display device

Abstract

Aiming at the problem of display effect loss in an under-screen camera area, the utility model discloses a display substrate, which comprises a substrate, at least one first display unit positioned in a display island area and a plurality of second display units positioned in a second display area and arranged in an array. The second display area is located on at least one side of the first display area. The first display area comprises a plurality of display island areas and a plurality of light-transmitting areas which are arranged in an array mode. The first display unit comprises N first light-emitting elements and M first pixel circuits, M and N are integers larger than 1, and M is smaller than N. The at least one first pixel circuit is connected with the at least two first light-emitting elements. The second display unit comprises M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected with the M second light-emitting elements in a one-to-one correspondence mode. The arrangement mode of the N first light-emitting elements of the first display unit is different from the arrangement mode of the M second light-emitting elements of the second display unit.

Description

Technical Field

[0001] The utility model relates to the field of display technology, in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In order to solve the problem of display effect loss in the under-screen camera area, the embodiments of the present utility model provide a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located at least on one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one first display unit; the at least one first display unit comprises: N first light-emitting elements and M first pixel circuits, M and N are both integers greater than 1, and M is less than N; at least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements, and is configured to drive the at least two first light-emitting elements to emit light. The second display area comprises: a plurality of second display units arranged in an array; at least one second display unit among the plurality of second display units comprises: M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

[0006] In some exemplary embodiments, within the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and the display island areas and the light-transmitting areas are alternately arranged and aligned in a second direction; wherein the first direction intersects the second direction.

[0007] In some exemplary embodiments, the M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in a first direction or a second direction, wherein the first direction intersects the second direction.

[0008] In some exemplary embodiments, the at least one first display unit includes: six first light-emitting elements and four first pixel circuits, and the four first pixel circuits are arranged in sequence along the first direction. The six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. The two first light-emitting elements emitting first color light are connected to the same first pixel circuit, the two first light-emitting elements emitting third color light are connected to the same first pixel circuit, and the two first light-emitting elements emitting second color light are electrically connected to the two first pixel circuits in a one-to-one correspondence.

[0009] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. In each group of first light-emitting elements, the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light are arranged in sequence along the second direction, and the first light-emitting elements emitting the third color light are located on the same side of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light along the first direction. The second direction intersects the first direction.

[0010] In some exemplary embodiments, the six first light-emitting elements are divided into two groups of first light-emitting elements, the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. In each group of first light-emitting elements, the first light-emitting element emitting the first color light, the first light-emitting element emitting the second color light, and the first light-emitting element emitting the third color light are arranged in sequence along the first direction.

[0011] In some exemplary embodiments, in the first display area, the connection order of the first pixel circuits and the first light emitting elements of the first display units in adjacent rows of display island areas is different.

[0012] In some exemplary embodiments, in the first display area, the four first pixel circuits located in the display island area of ​​the f-th row may be connected in sequence to two first light-emitting elements emitting first color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting third color light, and another first light-emitting element emitting second color light. The four first pixel circuits of the first display unit located in the display island area of ​​the f-1th row may be connected in sequence to two first light-emitting elements emitting third color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting first color light, and another first light-emitting element emitting second color light; wherein f is an integer greater than 1.

[0013] In some exemplary embodiments, the at least one second display unit includes: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction. The four second light-emitting elements include: a second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and a second light-emitting element emitting a third color light; the second light-emitting element emitting the first color light and the second light-emitting element emitting the third color light are arranged in the same row, and the two second light-emitting elements emitting the second color light are arranged in the same row; along the first direction, the second light-emitting element emitting the first color light, the second light-emitting element emitting the second color light, the second light-emitting element emitting the third color light, and the second light-emitting element emitting the second color light are arranged in sequence.

[0014] In some exemplary embodiments, the first color light is red light, the second color light is green light, and the third color light is blue light.

[0015] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area are connected to a first scan transmission segment and a second scan transmission segment extending along a first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. The first scan transmission segments in the display island areas located in the same row and adjacent to each other are connected through a first scan connection segment; the second scan transmission segments in the display island areas located in the same row and adjacent to each other are connected through a second scan connection segment. The second scan connection segment is located on a side of the first scan connection segment away from the substrate, and the orthographic projection of the first scan connection segment on the substrate at least partially overlaps with the orthographic projection of the second scan connection segment on the substrate.

[0016] In some exemplary embodiments, the first pixel circuit of the first display unit located in the display island area of ​​the same row is further connected to a first reset control line and a first initial signal line extending along the first direction, the first initial signal line is located on a side of the first reset control line away from the substrate; the first scanning connection section is located on a side of the first initial signal line away from the substrate. The orthographic projection of the first scanning connection section on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate; the orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control line on the substrate.

[0017] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area are connected to a light emitting control transmission segment extending along the first direction; the light emitting control transmission segment is configured to transmit a light emitting control signal; the light emitting control transmission segments in the display island areas adjacent to each other in the same row are connected via a light emitting control connection segment. The light emitting control connection segment and the first scanning connection segment are located on both sides of the light-transmitting area between the adjacent display island areas in the second direction. The second direction intersects the first direction.

[0018] In some exemplary embodiments, the first pixel circuit of the first display unit located in the display island area of ​​the same row is further connected to a second reset control line and a second initial signal line extending along the first direction, the second initial signal line is located on a side of the second reset control line away from the substrate; the light emission control connection section is located on a side of the second initial signal line away from the substrate. The orthographic projection of the light emission control connection section on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate; the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate.

[0019] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area are also connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment is configured to transmit a third initial signal. The initial signal transmission segments in the display island areas located in the same row and adjacent to each other are connected through an initial signal connection segment. The light emission control connection segment is located on a side of the initial signal connection segment away from the substrate; the orthographic projection of the initial signal connection segment on the substrate partially overlaps with the orthographic projection of the light emission control connection segment on the substrate.

[0020] In some exemplary embodiments, a plurality of first pixel circuits located in a display island area of ​​the kth row and the hth column and a plurality of first pixel circuits located in a display island area of ​​the k+1th row and the h+1th column are centrally symmetric about a connection point between the display island area of ​​the kth row and the hth column and the display island area of ​​the k+1th row and the h+1th column; wherein k and h are both integers greater than 0.

[0021] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1-th row display island area share a first reset control line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1th row located in the k+1-th row display island area share a second reset control line, wherein i is an integer greater than 1, and e is an integer greater than or equal to 0.

[0022] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area share a first initial signal line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th row display island area share a second initial signal line.

[0023] In some exemplary embodiments, the display island area includes two first display units, and the two first display units are arranged along a first direction or along a second direction, wherein the first direction intersects with the second direction.

[0024] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0025] On the other hand, the present embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located at least on one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits comprises M first pixel circuits, at least one first pixel circuit of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area comprises: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits comprises M second pixel circuits, at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuit and the second pixel circuit located in the same column are connected to the same data line.

[0026] In some exemplary embodiments, each group of first pixel circuits includes four first pixel circuits, the four first pixel circuits are connected to six first light-emitting elements, the six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. Each group of second pixel circuits includes four second pixel circuits, the four second pixel circuits are connected to four second light-emitting elements, the four second light-emitting elements include one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

[0027] In some exemplary embodiments, an arrangement of the six first light emitting elements is different from an arrangement of the four second light emitting elements.

[0028] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the second direction.

[0029] The display substrate provided in this embodiment adopts a pixel circuit built-in method to delete the first pixel circuit and the first light-emitting element in the first display area to form a light-transmitting area, and sets the arrangement of the first light-emitting element to be different from the arrangement of the second light-emitting element. On the basis of improving the light transmittance of the first display area, the display effect of the first display area can be guaranteed, and the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the first display area can be compensated.

[0030] Other features and advantages of the utility model will be described in the following description, and partly become apparent from the description, or understood by implementing the utility model. The purpose and other advantages of the utility model can be realized and obtained through the structures particularly pointed out in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the technical solution of the utility model and constitute a part of the specification. Together with the embodiments of the utility model, they are used to explain the technical solution of the utility model and do not constitute a limitation on the technical solution of the utility model.

[0032] Figure 1 A schematic diagram of a display substrate according to at least one embodiment of the present invention;

[0033] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present utility model;

[0034] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided;

[0035] Figure 4 A partial schematic diagram of a display area of ​​at least one embodiment of the utility model;

[0036] Figure 5 A schematic diagram of the signal correspondence between the first display area and the second display area of ​​at least one embodiment of the utility model;

[0037] Figure 6 A partial top view of the first display area of ​​at least one embodiment of the utility model;

[0038] Figure 7 for Figure 6 A schematic diagram of the first display area after the shielding layer is formed;

[0039] Fig. 8A for Figure 6 A schematic diagram of a first display area after a first semiconductor layer is formed in FIG.

[0040] Figure 8B for Fig. 8A A schematic diagram of a first semiconductor layer in FIG.

[0041] Fig.9A for Figure 6 A schematic diagram of the first display area after the first conductive layer is formed;

[0042] Fig. 9B for Fig.9A A schematic diagram of a first conductive layer and a first semiconductor layer in FIG.

[0043] Fig. 9C for Fig.9A A schematic diagram of a first conductive layer in FIG.

[0044] Fig. 10A for Figure 6 A schematic diagram of the first display area after the second conductive layer is formed;

[0045] Fig. 10B for Fig. 10A A schematic diagram of a second conductive layer in FIG.

[0046] Fig.11A for Figure 6 A schematic diagram of the first display area after the second semiconductor layer is formed;

[0047] Fig. 11B for Fig.11A A schematic diagram of a second semiconductor layer in FIG.

[0048] Fig. 12A for Figure 6 A schematic diagram of the first display area after the third conductive layer is formed;

[0049] Fig. 12B for Fig. 12A A schematic diagram of a third conductive layer in FIG.

[0050] Fig.13 for Figure 6 A schematic diagram of the first display area after the fifth insulating layer is formed;

[0051] Fig.14A for Figure 6 A schematic diagram of the first display area after the fourth conductive layer is formed;

[0052] Fig. 14B for Fig.14A A schematic diagram of a fourth conductive layer in FIG.

[0053] Fig.15 for Figure 6 A schematic diagram of the first display area after the seventh insulating layer is formed;

[0054] Fig.16A for Figure 6 A schematic diagram of the first display area after the fifth conductive layer is formed;

[0055] Fig. 16B for Fig.16A A schematic diagram of a fifth conductive layer in FIG.

[0056] Fig.17 for Figure 6 A schematic diagram of the first display area after the eighth insulating layer is formed;

[0057] Fig.18A for Figure 6 A schematic diagram of the first display area after the sixth conductive layer is formed;

[0058] Fig.18B for Fig.18A A schematic diagram of a sixth conductive layer in FIG.

[0059] Fig.19 for Figure 6 A schematic diagram of the first display area after the ninth insulating layer is formed;

[0060] Fig. 20A for Figure 6 A schematic diagram of the first display area after the anode layer is formed;

[0061] Fig. 20B for Fig. 20A Schematic diagram of the anode layer in FIG.

[0062] Fig.21 for Figure 6 Schematic diagram of the light-transmitting area in FIG.

[0063] Fig. 22 Another partial top view of the first display area of ​​at least one embodiment of the utility model;

[0064] Fig.23 for Fig. 22 A schematic diagram of the first display area after the shielding layer is formed;

[0065] Fig.24A for Fig. 22 A schematic diagram of a first display area after a first semiconductor layer is formed in FIG.

[0066] Fig. 24B for Fig.24A A schematic diagram of a first semiconductor layer in FIG.

[0067] Fig.25A for Fig. 22 A schematic diagram of the first display area after the first conductive layer is formed;

[0068] Fig.25B for Fig.25A A schematic diagram of a first conductive layer in FIG.

[0069] Fig.26A for Fig. 22A schematic diagram of the first display area after the second conductive layer is formed;

[0070] Fig.26B for Fig.26A A schematic diagram of a second conductive layer in FIG.

[0071] Fig.27A for Fig. 22 A schematic diagram of the first display area after the second semiconductor layer is formed;

[0072] Fig.27B for Fig.27A A schematic diagram of a second semiconductor layer in FIG.

[0073] Fig.28A for Fig. 22 A schematic diagram of the first display area after the third conductive layer is formed;

[0074] Fig.28B for Fig.28A A schematic diagram of a third conductive layer in FIG.

[0075] Fig.29A for Fig. 22 A schematic diagram of the first display area after the fourth conductive layer is formed;

[0076] Fig.29B for Fig.29A A schematic diagram of a fourth conductive layer in FIG.

[0077] Fig. 30A for Fig. 22 A schematic diagram of the first display area after the fifth conductive layer is formed;

[0078] Fig. 30B for Fig. 30A A schematic diagram of a fifth conductive layer in FIG.

[0079] Fig.31A for Fig. 22 A schematic diagram of the first display area after the sixth conductive layer is formed;

[0080] Fig.31B for Fig.31A A schematic diagram of a sixth conductive layer in FIG.

[0081] Fig.32 for Fig. 22 A schematic diagram of the first display area after the anode layer is formed;

[0082] Fig.33 for Fig. 22 Schematic diagram of the light-transmitting area in FIG.

[0083] Fig.34 Another schematic diagram of the signal correspondence between the first display area and the second display area of ​​at least one embodiment of the utility model;

[0084] Fig.35 Another partial schematic diagram of the display area of ​​at least one embodiment of the utility model;

[0085] Fig.36 A partial top view of the first display area of ​​at least one embodiment of the utility model;

[0086] Fig.37A for Fig.36 A schematic diagram of the first display area after the anode layer is formed;

[0087] Fig.37B for Fig.37A Schematic diagram of the anode layer in FIG.

[0088] Fig.38 Another partial schematic diagram of the display area of ​​at least one embodiment of the utility model;

[0089] Fig.39 Another partial schematic diagram of the display area of ​​at least one embodiment of the utility model;

[0090] Fig.40 It is a schematic diagram of a display device according to at least one embodiment of the present invention. DETAILED DESCRIPTION

[0091] The embodiments of the utility model will be described in detail below in conjunction with the accompanying drawings. The utility model describes multiple embodiments, but the description is exemplary rather than restrictive, and it is obvious to those of ordinary skill in the art that there may be more embodiments and implementations within the scope of the embodiments described in the utility model. Although many possible feature combinations are shown in the drawings and discussed in the embodiments, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0092] The present invention includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features and elements of the present invention may also be combined with any conventional features or elements to form a unique invention scheme. Any features or elements of any embodiment may also be combined with features or elements from other invention schemes to form another unique invention scheme. Therefore, it should be understood that any feature shown or discussed in the present invention may be implemented individually or in any appropriate combination. Therefore, except for the limitations made according to the attached claims and their equivalents, the embodiments are not subject to other restrictions. In addition, various modifications and changes may be made within the scope of protection of the attached claims.

[0093] In addition, when describing representative embodiments, the specification may have presented the method or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those of ordinary skill in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method or process should not be limited to the steps of performing them in the order written, and those skilled in the art can easily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the utility model.

[0094] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0095] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features.

[0096] In the description of the present invention, “plurality” means at least two, such as two, three, etc., unless otherwise clearly defined.

[0097] In the present invention, unless otherwise clearly specified and limited, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the meanings of the above terms in the present invention can be understood according to the circumstances.

[0098] In the present invention, "electrical connection" includes the situation where the components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having multiple functions.

[0099] In the present utility model, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0100] In the present invention, a transistor refers to an element including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, a drain region, or a drain electrode) and a source (source electrode terminal, a source region, or a source electrode), and current can flow through the drain, the channel region, and the source. In the present invention, a channel region refers to a region where current mainly flows.

[0101] In the present invention, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in the present invention, the "source electrode" and the "drain electrode" may be interchanged. In addition, the gate electrode may also be called a control electrode.

[0102] In the present invention, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0103] In the present invention, circle, ellipse, triangle, rectangle, trapezoid, pentagon or hexagon are not in the strict sense, but may be approximate circle, approximate ellipse, approximate triangle, approximate rectangle, approximate trapezoid, approximate pentagon or approximate hexagon, etc., and there may be some small deformations caused by tolerance, such as chamfer angles, arc edges and deformation.

[0104] The "light transmittance" in the present invention refers to the ability of light to pass through a medium, which is the percentage of the luminous flux passing through a transparent or translucent body to its incident luminous flux.

[0105] In the present invention, "approximately" and "substantially" mean that the limits are not strictly defined and the process and measurement errors are allowed. In the present invention, "same" can include completely consistent and substantially the same situations, and "substantially the same" means that the numerical value differs by less than 10%.

[0106] In the present invention, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the present invention, "A extends along direction B" means "the main part of A extends along direction B.

[0107] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and in-screen hole have appeared one after another. These technologies are to reduce the area occupied by the camera by digging holes in part of the display area and placing a camera under the hole area, thereby increasing the screen-to-body ratio. However, the above technology requires digging out part of the display area, which will cause part of the display screen to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually used in the camera area under the screen.

[0108] The external pixel circuit method refers to setting the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area, and improving the light transmittance of the under-screen camera area by arranging the light-emitting element and the pixel circuit separately. Since there is no pixel circuit in the under-screen camera area, there is no other light-shielding layer in this area except the anode of the light-emitting element, so a higher light transmittance can be achieved. However, in this way, the pixel circuit and the light-emitting element need to be electrically connected through a conductive connecting wire. Limited by the arrangement space of the conductive connecting wire, the size (such as the aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the mask process of the conductive connecting wire, resulting in increased costs. Moreover, the material of the conductive connecting wire is usually a transparent conductive material, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the load of the conductive connecting wire is large, which easily affects the brightness of the light-emitting element in the under-screen camera area, causing the brightness of the under-screen camera area to decrease, thereby causing poor display in the under-screen camera area, such as vertical display poor (Mura). Moreover, the use of conductive connecting wires tends to introduce more vias, which in turn reduces the aperture ratio of the under-screen camera area and is not conducive to optimizing the light transmittance of the under-screen camera area.

[0109] The built-in pixel circuit method refers to setting a light-emitting element and a pixel circuit connected to the light-emitting element in the under-screen camera area. Compared with the external pixel circuit method, the electrical connection between the pixel circuit and the light-emitting element in the under-screen camera area using the built-in method does not require a long conductive connecting wire, which can avoid the poor display of the under-screen camera area caused by the conductive connecting wire. In addition, the built-in method does not limit the size of the under-screen camera area and can support large-aperture under-screen camera areas. However, for complex pixel circuits, due to the large number of wiring, it is difficult to improve the light transmittance of the under-screen camera area by compressing the layout of the pixel circuit, resulting in the inability to meet the light transmittance requirements required for functions such as under-screen video or under-screen face recognition.

[0110] For the pixel circuit built-in method, some of the light-emitting elements and pixel circuits in the under-screen camera area can be deleted so that the remaining light-emitting elements and pixel circuits do not need to be compressed, thereby achieving the light transmittance requirements of the under-screen function. However, when deleting some of the light-emitting elements and pixel circuits in the under-screen camera area to increase the light transmittance, it is easy to affect the display effect.

[0111] The present embodiment provides a display substrate and a display device, which can not only improve the light transmittance of the under-screen camera area, but also compensate for the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the under-screen camera area.

[0112] The present embodiment provides a display substrate, comprising: a substrate, at least one first display unit located in a display island area, and a plurality of second display units located in a second display area and arranged in an array. The substrate comprises: a first display area and a second display area located on at least one side of the first display area. The first display area comprises a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. At least one first display unit comprises: N first light-emitting elements and M first pixel circuits, where M and N are both integers greater than 1, and M is less than N. At least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light. At least one second display unit comprises: M second light-emitting elements and M second pixel circuits, where the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence. The arrangement of the N first light-emitting elements of at least one first display unit is different from the arrangement of the M second light-emitting elements of at least one second display unit.

[0113] In some examples, the shapes and sizes of the multiple display islands in the first display area may be substantially the same, and the shapes and sizes of the multiple light-transmitting areas may be substantially the same. The light-transmitting areas may be formed by deleting the first pixel circuits and the first light-emitting elements, and the number of first pixel circuits deleted corresponding to the light-transmitting areas may be less than or equal to the total number of first pixel circuits included in the multiple display islands.

[0114] In some examples, at least one first pixel circuit in the first display unit may be connected to at least two first light-emitting elements, and at least one first pixel circuit may be connected to at least one first light-emitting element. For example, the first display unit may include four first pixel circuits, wherein two first pixel circuits may be connected to the first light-emitting element in a one-drive-two manner, wherein two first pixel circuits may be connected to the first light-emitting element in a one-drive-one manner. In this example, one-drive-F means that a pixel circuit is connected to F light-emitting elements, and the pixel circuit drives the connected F light-emitting elements to emit light, and F is an integer greater than or equal to 1. For example, one-drive-one means that a pixel circuit is connected to a light-emitting element and drives the connected light-emitting element to emit light; one-drive-two means that a pixel circuit is connected to two light-emitting elements and drives the connected two light-emitting elements to emit light. However, this embodiment is not limited to this. In other examples, the first pixel circuit in the first display unit may be connected to the first light-emitting element in other one-drive-multiple manners such as one-drive-three or one-drive-four.

[0115] In some exemplary embodiments, the second pixel circuit in the second display unit can be connected to the second light-emitting element in a one-to-one manner. The arrangement density of the second pixel circuit in the second display area can be greater than or equal to the arrangement density of the first pixel circuit in the first display area. For example, the arrangement density of the first pixel circuit in the first display area in the first direction can be 0.4 to 0.6 of the arrangement density of the second pixel circuit in the second display area in the first direction, such as 0.45 to 0.55, for example, about 0.5; or, the arrangement density of the first pixel circuit in the first display area in the column direction can be 0.4 to 0.6 of the arrangement density of the second pixel circuit in the second display area in the column direction, such as 0.45 to 0.55, for example, about 0.5. This example can improve the light transmittance of the first display area by deleting the first pixel circuit in the first display area.

[0116] In some examples, the light transmittance of the second display area may be less than the light transmittance of the first display area.

[0117] The display substrate provided in this embodiment adopts a pixel circuit built-in method to delete the first pixel circuit and the first light-emitting element in the first display area to form a light-transmitting area, and sets the arrangement of the first light-emitting element to be different from the arrangement of the second light-emitting element. On the basis of improving the light transmittance of the first display area, the display effect of the first display area can be guaranteed, and the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the first display area can be compensated.

[0118] In some exemplary embodiments, each display island may include a first display unit. In other examples, at least one display island may include a plurality of first display units, for example, two first display units. The two first display units in the display island may be arranged along a first direction, or may be arranged along a second direction. The first direction may intersect with the second direction, for example, the first direction may be perpendicular to the second direction. In some examples, the first direction may be parallel to the row direction of the display islands arranged in an array, and the second direction may be parallel to the column direction of the display islands arranged in an array. This embodiment is not limited to this.

[0119] In some exemplary embodiments, in the first display area, a plurality of display island areas and a plurality of light-transmitting areas are alternately arranged and aligned in the first direction, and a plurality of display island areas and a plurality of light-transmitting areas are alternately arranged and aligned in the second direction. The first direction may intersect with the second direction. However, this embodiment is not limited to this. In other examples, in the second direction, a plurality of display island areas may be arranged continuously and staggered. The arrangement of the display island areas and the light-transmitting areas in the first display area of ​​this example may be beneficial to improving the light transmittance of the first display area.

[0120] In this example, in direction C, A and B are alternately arranged, that is, they are arranged in a periodic manner in the order of AB along direction C. In direction C, A and B are aligned, that is, the edges of A and B roughly coincide with the midline of the direction perpendicular to direction C, and the edge extension lines of A and B can roughly coincide. In direction C, A and B are staggered, that is, the edges of A and B are roughly parallel to the midline of the direction perpendicular to direction C and do not coincide.

[0121] In some exemplary embodiments, the M first pixel circuits of at least one first display unit and the M second pixel circuits of at least one second display unit are aligned in the first direction or the second direction. In this example, the first pixel circuit of the first display area and the second pixel circuit of the second display area can share a signal line extending along the first direction (for example, including a first scan line, a second scan line, a light emitting control line, etc.), and can share a signal line extending along the second direction (for example, including a data line, etc.), so as to facilitate line arrangement.

[0122] In some exemplary embodiments, at least one first display unit may include: six first light-emitting elements and four first pixel circuits, and the four first pixel circuits are arranged in sequence along the first direction. The six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. The two first light-emitting elements emitting first color light are connected to the same first pixel circuit, the two first light-emitting elements emitting third color light are connected to the same first pixel circuit, and the two first light-emitting elements emitting second color light are electrically connected to the two first pixel circuits in a one-to-one correspondence. For example, the first color light is red light, the second color light is green light, and the third color light is blue light. The first light-emitting elements of the first display area of ​​this example can adopt an RGB arrangement, which is conducive to improving the display effect of the first display area.

[0123] In some exemplary embodiments, the six first light-emitting elements of the first display unit may be divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction. Each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light. In each group of first light-emitting elements, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light may be arranged in sequence along the second direction, and the first light-emitting element emitting the third color light may be located on the same side of the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light along the first direction. Alternatively, in each group of first light-emitting elements, the first light-emitting element emitting the first color light, the first light-emitting element emitting the second color light, and the first light-emitting element emitting the third color light may be arranged in sequence along the first direction. The arrangement of the first light-emitting elements of the first display area of ​​this example can optimize the display effect of the first display area.

[0124] In some exemplary embodiments, at least one second display unit may include: four second light-emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction. The four second light-emitting elements may include: a second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and a second light-emitting element emitting a third color light. The second light-emitting element emitting the first color light and the second light-emitting element emitting the third color light are arranged in the same row, and the two second light-emitting elements emitting the second color light are arranged in the same row; along the first direction, the second light-emitting element emitting the first color light, the second light-emitting element emitting the second color light, the second light-emitting element emitting the third color light, and the second light-emitting element emitting the second color light can be arranged in sequence. For example, the first color light is red light, the second color light is green light, and the third color light is blue light. The second display area of ​​this example can adopt the RGBG arrangement method to ensure the display effect of the second display area.

[0125] In some exemplary embodiments, in the first display area, the connection order of the first pixel circuits and the first light-emitting elements of the first display units in the display island areas of adjacent rows may be different. In some examples, the four first pixel circuits of the first display unit located in the display island area of ​​the fth row may be connected in sequence to two first light-emitting elements emitting first color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting third color light, and another first light-emitting element emitting second color light. The four first pixel circuits of the first display unit located in the display island area of ​​the f-1th row may be connected in sequence to two first light-emitting elements emitting third color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting first color light, and another first light-emitting element emitting second color light. Wherein, f is an integer greater than 1. The connection method of the first pixel circuit and the first light-emitting element in the display island area of ​​this example can be beneficial to optimize the display uniformity of the first display area.

[0126] In some exemplary embodiments, in the first display area, the M first pixel circuits of the first display unit in the display island area are connected to the first scan transmission segment and the second scan transmission segment extending along the first direction. The first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal. The first scan transmission segments in the display island areas located in the same row and adjacent to each other can be connected by the first scan connection segment, and the second scan transmission segments in the display island areas located in the same row and adjacent to each other can be connected by the second scan connection segment. For example, the first scan line may include a first scan transmission segment and a first scan connection segment connected at intervals along the first direction, and the first scan transmission segment and the first scan connection segment are located in different film layers; the second scan line may include a second scan transmission segment and a second scan connection segment connected at intervals along the first direction, and the second scan transmission segment and the second scan connection segment are located in different film layers. The second scan connection segment may be located on a side of the first scan connection segment away from the substrate, and the orthographic projection of the first scan connection segment on the substrate and the orthographic projection of the second scan connection segment on the substrate may at least partially overlap. For example, the first scan transmission segment can be located in the first conductive layer, and the first scan connection segment can be located in the fourth conductive layer; the second scan transmission segment can be located in the third conductive layer, and the second scan connection segment can be located in the fifth conductive layer. In this example, the transmission lines of the first scan signal and the second scan signal are switched across layers in sections, so that the first scan connection segment and the second scan connection segment can be overlapped, which is beneficial to increase the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0127] In some exemplary embodiments, the first pixel circuit of the first display unit located in the display island area of ​​the same row may also be connected to the first reset control line and the first initial signal line extending along the first direction, and the first initial signal line may be located on the side of the first reset control line away from the substrate. The first scan connection segment may be located on the side of the first initial signal line away from the substrate. The orthographic projection of the first scan connection segment on the substrate may at least partially overlap with the orthographic projection of the first initial signal line on the substrate, and the orthographic projection of the first initial signal line on the substrate may at least partially overlap with the orthographic projection of the first reset control line on the substrate. For example, the first initial signal line may be located in the third conductive layer, the first reset control line may be located in the first conductive layer, and the first scan connection segment may be located in the fourth conductive layer. In this example, overlapping wiring of the first reset control line, the first initial signal line, and the first scan connection segment may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0128] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area may be connected to a light-emitting control transmission segment extending along the first direction; the light-emitting control transmission segment may be configured to transmit a light-emitting control signal. The light-emitting control transmission segments in the display island areas that are located in the same row and adjacent to each other may be connected through a light-emitting control connection segment. For example, the light-emitting control line may include a light-emitting control transmission segment and a light-emitting control connection segment that are spaced apart and connected along the first direction, and the light-emitting control transmission segment and the light-emitting control connection segment are located in different film layers. For example, the light-emitting control transmission segment may be located in the first conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. The light-emitting control connection segment and the first scanning connection segment may be located on both sides of the light-transmitting area between the adjacent display island areas in the column direction. In this example, the first scanning connection segment and the light-emitting control connection segment are arranged to bypass the light-transmitting area from both sides of the light-transmitting area along the column direction, which can optimize the wiring space, help increase the area of ​​the light-transmitting area, and thus improve the light transmittance of the first display area.

[0129] In some exemplary embodiments, the first pixel circuit of the first display unit located in the display island area of ​​the same row may also be connected to the second reset control line and the second initial signal line extending along the first direction, and the second initial signal line may be located on the side of the second reset control line away from the substrate; the light-emitting control connection segment may be located on the side of the second initial signal line away from the substrate. The orthographic projection of the light-emitting control connection segment on the substrate may at least partially overlap with the orthographic projection of the second initial signal line on the substrate. The orthographic projection of the second initial signal line on the substrate may at least partially overlap with the orthographic projection of the second reset control line on the substrate. For example, the second reset control line may be located in the first conductive layer, the second initial signal line may be located in the third conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. In this example, overlapping wiring of the second reset control line, the second initial signal line, and the light-emitting control connection segment may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0130] In some exemplary embodiments, the M first pixel circuits of the first display unit in the display island area may also be connected to the initial signal transmission segment extending along the first direction; the initial signal transmission segment may be configured to transmit a third initial signal. The initial signal transmission segments in the display island areas that are located in the same row and adjacent to each other may be connected through the initial signal connection segment. For example, the third initial signal line may include an initial signal transmission segment and an initial signal connection segment that are spaced apart and connected along the first direction, and the initial signal transmission segment and the initial signal connection segment may be located in different film layers. The light-emitting control connection segment may be located on the side of the initial signal connection segment away from the substrate. The orthographic projection of the initial signal connection segment on the substrate may partially overlap with the orthographic projection of the light-emitting control connection segment on the substrate. For example, the initial signal transmission segment may be located in the third conductive layer, the initial signal connection segment may be located in the second conductive layer, and the light-emitting control connection segment may be located in the fourth conductive layer. In this example, overlapping wiring of the initial signal connection segment and the light-emitting control connection segment may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0131] In some exemplary embodiments, a plurality of first pixel circuits located in the display island area of ​​the kth row and the hth column and a plurality of first pixel circuits located in the display island area of ​​the kth row and the hth column may be centrally symmetrical about the connection point between the display island area of ​​the kth row and the hth column and the display island area of ​​the kth row and the hth column. Wherein, k and h are both integers greater than 0. In this example, the first pixel circuits in the display island area of ​​the even rows or odd rows are flipped, so that the first pixel circuits in the display island areas of adjacent rows and adjacent columns are centrally symmetrical, which can help reduce the wiring space in the display island area, help increase the area of ​​the light-transmitting area, and thus improve the light transmittance of the first display area.

[0132] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1th row display island area may share a first reset control line, and the first pixel circuit of the i+eth row located in the k-th row display island area and the first pixel circuit of the i+e+1th row located in the k+1th row display island area may share a second reset control line, wherein i is an integer greater than 1, and e is an integer greater than or equal to 0. In some examples, a row of first pixel circuits may be provided for each row of display island areas, and the value of e may be 0; the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1th row display island area may share a first reset control line, and the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i+1th row located in the k+1th row display island area may share a second reset control line. In other examples, each row of the display island area includes at least two rows of first pixel circuits, and the value of e can be greater than or equal to 1. For example, each row of the display island area can include two rows of first pixel circuits, and e can be 1. The first pixel circuit of the i-th row located in the k-th row of the display island area and the first pixel circuit of the i-1th row located in the k-1-th row of the display island area can share a first reset control line, and the first pixel circuit of the i+1th row located in the k-th row of the display island area and the first pixel circuit of the i+2th row located in the k+1-th row of the display island area can share a second reset control line. This example can help reduce wiring space and increase the area of ​​the light-transmitting area by setting two adjacent rows of first pixel circuits in adjacent rows of display island areas to share the first reset control line or the second reset control line, thereby improving the light transmittance of the first display area.

[0133] In some exemplary embodiments, in the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1th row display island area can share a first initial signal line, and the first pixel circuit of the i+eth row located in the k-th row display island area and the first pixel circuit of the i+e+1th row located in the k+1th row display island area can share a second initial signal line. In some examples, each row of display island area can be provided with a row of first pixel circuits, and the value of e can be 0; the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1th row display island area can share a first initial signal line, and the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i+1th row located in the k+1th row display island area can share a second initial signal line. In other examples, each row of display island area includes at least two rows of first pixel circuits, and the value of e can be greater than or equal to 1. For example, each row of the display island area may include two rows of first pixel circuits, and e may be 1. The first pixel circuit of the i-th row located in the k-th row of the display island area and the first pixel circuit of the i-1th row located in the k-1-th row of the display island area may share a first initial signal line, and the first pixel circuit of the i+1th row located in the k-th row of the display island area and the first pixel circuit of the i+2th row located in the k+1-th row of the display island area may share a second initial signal line. In this example, by setting two adjacent rows of first pixel circuits in adjacent rows of the display island area to share the first initial signal line or the second initial signal line, it is beneficial to reduce the wiring space, increase the area of ​​the light-transmitting area, and thus improve the light transmittance of the first display area.

[0134] The solution of this embodiment is described below by means of some examples.

[0135] Figure 1 Schematic diagram of a display substrate of at least one embodiment of the present utility model. In some examples, such as Figure 1 As shown, the display substrate may include: a display area AA and a peripheral area BB located outside the display area AA. The display area AA may include at least: a first display area A1 and a second display area A2, and the second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0136] In some examples, such as Figure 1As shown, the first display area A1 can be called the Full Display With Camera (FDC) area. The second display area A2 can also be called the normal display area. The light transmittance of the first display area A1 can be greater than the light transmittance of the second display area A2. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate can be located in the first display area A1 of the display substrate. In some examples, such as Figure 1 As shown, the first display area A1 may be circular, and the size of the sensor's orthographic projection on the display substrate may be smaller than or equal to the size of the first display area A1. In other examples, the first display area A1 may be rectangular, and the size of the sensor's orthographic projection on the display substrate may be smaller than or equal to the size of the inscribed circle of the first display area A1. This embodiment is not limited to this.

[0137] In some examples, such as Figure 1 As shown, the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other positions such as the upper left corner, upper right corner, lower left corner or lower right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0138] In some examples, such as Figure 1 As shown, the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be a circle or an ellipse. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon or other shapes.

[0139] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0140] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0141] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present utility model. The pixel circuit of this example is described by taking an 8T1C structure as an example. In some examples, such as Figure 2 As shown, the pixel circuit of this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first light emission control transistor, the sixth transistor T6 may also be referred to as a second light emission control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

[0142] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be first type transistors, for example, P type transistors, and the second transistor T2 may be second type transistors, for example, N type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors of the pixel circuit may all be P type transistors, or may all be N type transistors.

[0143] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can adopt a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can adopt an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0144] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1 and the second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The light emission control line EML can be configured to provide a light emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line can be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0145] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0146] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0147] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided is as follows. Figure 3 right Figure 2The working process of the pixel circuit shown in FIG. 1 is described as follows. The first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit are P-type transistors, and the second transistor T2 is an N-type transistor.

[0148] In some examples, such as Figure 2 and Figure 3 As shown, in a frame display time period, the working process of the pixel circuit may at least include: a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4.

[0149] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, which turns on the second transistor T2. The eighth transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, so that the fourth transistor T4, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0150] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, and the first transistor T1 is turned on; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. The first transistor T1 and the second transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0151] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scanning signal SCAN1 provided by the first scanning line GL1 is a low level signal, and the fourth transistor T4 is turned on; the second scanning signal SCAN2 provided by the second scanning line GL2 is a high level signal, and the second transistor T2 is turned on. In this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4 and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light control signal EM provided by the light control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0152] In the fourth stage S4, the light control signal EM provided by the light control line EML can be switched from a high level signal to a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a low level signal, so that the second transistor T2 is turned off. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal VDD output by the first power line PL1 provides a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, so as to drive the light emitting element EL to emit light.

[0153] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0154] I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth]2 =K×[VDD-Vdata] 2 ;

[0155] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0156] It can be seen from the above formula that the current flowing through the light-emitting element has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the poor display caused by low frequency and improve the display effect of the light-emitting element.

[0157] In some examples, such as Figure 1 As shown, the first display area A1 may include: a plurality of first pixel circuits 11 and a plurality of first light-emitting elements 13; the second display area A2 may include: a plurality of second pixel circuits 12 and a plurality of second light-emitting elements 14. At least one first pixel circuit 11 may be connected to at least one first light-emitting element 13, and configured to drive the at least one first light-emitting element 13 connected thereto to emit light. At least one second pixel circuit 12 may be connected to at least one second light-emitting element 14, and configured to drive the at least one second light-emitting element 14 connected thereto to emit light. In this example, the first display area A1 uses a pixel circuit built-in method to drive the first light-emitting element to emit light.

[0158] Figure 4 It is a partial schematic diagram of a display area of ​​at least one embodiment of the utility model. Figure 4 The arrangement of the plurality of first light-emitting elements in the first display area and the plurality of second light-emitting elements in the second display area is illustrated in FIG. Figure 4 In the example, eight rows and four columns of display islands in the first display area are used for illustration. This example does not limit the number of display islands in the first display area.

[0159] In some examples, such as Figure 4 As shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. In a first direction X (parallel to the row direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. In a second direction Y (parallel to the column direction), the display island areas A11 and the light-transmitting areas A12 may be alternately arranged and aligned. However, this embodiment is not limited to this. In other examples, adjacent rows of display island areas may be staggered, for example, at least one first pixel circuit in adjacent rows of display island areas may be aligned.

[0160] In some examples, the shapes and sizes of the plurality of display island regions A11 may be substantially the same, and the shapes and sizes of the plurality of light-transmitting regions A12 may be substantially the same. For example, the display island region A11 may be substantially in the shape of a rectangular island.

[0161] In some examples, such as Figure 4 As shown, at least one display island A11 may include: a first display unit 21. The first display unit 21 may include: six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include: two first light-emitting elements 13a and 13d emitting first color light, two first light-emitting elements 13b and 13e emitting second color light, and two first light-emitting elements 13c and 13f emitting third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. This embodiment is not limited to this.

[0162] In some examples, such as Figure 4 As shown, the six first light-emitting elements of the first display unit 21 can be divided into two groups of first light-emitting elements, and each group of first light-emitting elements can include three first light-emitting elements that emit light of different colors. For example, the first group of first light-emitting elements can include: three first light-emitting elements 13a, 13b and 13c; the second group of first light-emitting elements can include: three first light-emitting elements 13d, 13e and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements can be arranged in sequence along the first direction X. In the first group of first light-emitting elements, the first light-emitting elements 13a and 13b can be arranged in sequence along the second direction Y, and the first light-emitting element 13c can be located on the same side of the first light-emitting elements 13a and 13b in the first direction X. For example, the first light-emitting element 13a can be located on one side of the first light-emitting element 13b in the second direction Y, and the first light-emitting element 13c can be located on one side of the first light-emitting elements 13a and 13b in the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d and 13e may be arranged in sequence along the second direction Y, and the first light-emitting element 13f may be located on the same side of the first light-emitting elements 13d and 13e in the first direction X. For example, the first light-emitting element 13d may be located on one side of the first light-emitting element 13e in the second direction Y, and the first light-emitting element 13f may be located on one side of the first light-emitting elements 13d and 13e in the first direction X. In this example, the three first light-emitting elements emitting light of different colors in each group of first light-emitting elements of the first display unit 21 may be arranged in a Pentile RGB manner.

[0163] In some examples, such as Figure 4As shown, the second display area A2 may include: a plurality of second display units 22 arranged in an array. At least one second display unit 22 may include: four second light-emitting elements and four second pixel circuits. The four second light-emitting elements may include: a second light-emitting element 14a emitting a first color light, two second light-emitting elements 14b and 14d emitting a second color light, and a second light-emitting element 14c emitting a third color light. The four second light-emitting elements may be electrically connected to the four second pixel circuits in a one-to-one correspondence. Each second pixel circuit may be configured to drive a corresponding second light-emitting element to emit light. In a second display unit 22, the second light-emitting elements 14a, 14b, 14c and 14d may be arranged in different columns in sequence along the first direction X, the second light-emitting elements 14a and 14c may be arranged in the same row, and the second light-emitting elements 14b and 14d may be arranged in the same row. In the second display area A2, multiple second light-emitting elements 14a and 14c can be arranged in the same row at intervals, multiple second light-emitting elements 14b and 14d can be arranged in the same row at intervals, and the row where the second light-emitting elements 14a and 14c are located can be arranged in the second direction Y at intervals with the row where the second light-emitting elements 14b and 14d are located, so that multiple second light-emitting elements 14a and 14c can be arranged in the same column at intervals, and multiple second light-emitting elements 14b and 14d are arranged in the same column at intervals. In this example, the multiple second light-emitting elements in the second display area can be arranged in RGBG.

[0164] Figure 5 The figure is a schematic diagram of the signal correspondence between the first display area and the second display area in at least one embodiment of the present invention. Figure 5 In the description, a first display unit in the first display area A1 and a second display unit in the second display area A2 are taken as examples.

[0165] In some examples, such as Figure 5As shown, the four first pixel circuits of the first display unit may include: first pixel circuits 11a, 11b, 11c and 11d arranged in sequence along the first direction X. The first pixel circuit 11a can be connected to two first light-emitting elements 13a and 13d that emit the first color light, and is configured to drive the two first light-emitting elements 13a and 13d to emit light. The first pixel circuit 11b can be connected to a first light-emitting element 13b that emits the second color light, and is configured to drive the first light-emitting element 13b to emit light. The first pixel circuit 11c can be connected to two first light-emitting elements 13c and 13f that emit the third color light, and is configured to drive the two first light-emitting elements 13c and 13f to emit light. The first pixel circuit 11d can be connected to a first light-emitting element 13e that emits the second color light, and is configured to drive the first light-emitting element 13e to emit light. In this example, the first pixel circuits 11a and 11c are both connected to the first light-emitting element in a one-drive-two manner, and the first pixel circuits 11b and 11d are both connected to the first light-emitting element in a one-drive-one manner.

[0166] In some examples, such as Figure 5 As shown, the orthographic projection of the first pixel circuit 11a on the substrate may at least partially overlap with the orthographic projection of the first light-emitting elements 13a and 13b on the substrate. The orthographic projection of the first pixel circuit 11b on the substrate may at least partially overlap with the orthographic projection of the first light-emitting element 13c on the substrate. The orthographic projection of the first pixel circuit 11c on the substrate may at least partially overlap with the orthographic projection of the first light-emitting elements 13d and 13e on the substrate. The orthographic projection of the first pixel circuit 11d on the substrate may at least partially overlap with the orthographic projection of the first light-emitting element 13f on the substrate. In this example, the orthographic projection of the first pixel circuit and the connected first light-emitting element on the substrate may partially overlap, or there may be no overlap.

[0167] In some examples, such as Figure 5 As shown, the four second pixel circuits of the second display unit may include: second pixel circuits 12a, 12b, 12c and 12d arranged in sequence along the first direction X. The second pixel circuit 12a can be connected to a second light-emitting element 14a that emits a first color light, and is configured to drive the second light-emitting element 14a to emit light. The second pixel circuit 12b can be connected to a second light-emitting element 14b that emits a second color light, and is configured to drive the second light-emitting element 14b to emit light. The second pixel circuit 12c can be connected to a second light-emitting element 14c that emits a third color light, and is configured to drive the second light-emitting element 14c to emit light. The second pixel circuit 12d can be connected to a second light-emitting element 14d that emits a second color light, and is configured to drive the second light-emitting element 14d to emit light. In this example, the four second pixel circuits can all be connected to the second light-emitting elements in a one-to-one manner.

[0168] In some examples, such as Figure 5 As shown, the orthographic projection of the second pixel circuit 12a on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14a on the substrate. The orthographic projection of the second pixel circuit 12b on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14b on the substrate. The orthographic projection of the second pixel circuit 12c on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14c on the substrate. The orthographic projection of the second pixel circuit 12d on the substrate may at least partially overlap with the orthographic projection of the second light-emitting element 14d on the substrate. In this example, the orthographic projections of the second pixel circuit and the second light-emitting element connected to it on the substrate may at least partially overlap.

[0169] In some examples, such as Figure 5 As shown, the four first pixel circuits of the first display unit can be aligned with the four second pixel circuits of the second display unit in the second direction Y. For example, the first pixel circuit 11a and the second pixel circuit 12a can be aligned in the second direction Y, the first pixel circuit 11b and the second pixel circuit 12b can be aligned in the second direction Y, the first pixel circuit 11c and the second pixel circuit 12c can be aligned in the second direction Y, and the first pixel circuit 11d and the second pixel circuit 12d can be aligned in the second direction Y.

[0170] In some examples, such as Figure 5 As shown, the first pixel circuit 11a of the first display unit and the second pixel circuit 12a of the second display unit can be located in the same column of pixel circuits and connected to the same data line (e.g., data line DL(j)) extending along the second direction Y. The first pixel circuit 11b of the first display unit and the second pixel circuit 12b of the second display unit can be located in the same column of pixel circuits and connected to the same data line (e.g., data line DL(j+1)) extending along the second direction Y. The first pixel circuit 11c of the first display unit and the second pixel circuit 12c of the second display unit can be located in the same column of pixel circuits and connected to the same data line (e.g., data line DL(j+2)) extending along the second direction Y. The first pixel circuit 11d of the first display unit and the second pixel circuit 12d of the second display unit can be located in the same column of pixel circuits and connected to the same data line (e.g., data line DL(j+3)) extending along the second direction Y. Wherein, j can be a positive integer.

[0171] In some examples, such as Figure 5As shown, the four first pixel circuits of the first display unit may be arranged in the same row of pixel circuits and connected to the same first scan line (e.g., the first scan line GL1(f)) extending along the first direction X. The four second pixel circuits of the second display unit may be arranged in the same row of pixel circuits and connected to the same first scan line (e.g., the first scan line GL1(f+1)) extending along the first direction X. Wherein, f may be a positive integer.

[0172] In some examples, such as Figure 4 and Figure 5 As shown, the multiple second light-emitting elements of the second display area A2 can adopt an RGBG arrangement, and the second pixel circuit and the second light-emitting element can be in a one-to-one correspondence. The multiple first light-emitting elements of the first display area A1 can adopt a Pentile RGB arrangement, and by reducing the number of first pixel circuits, four first pixel circuits can drive six first light-emitting elements to emit light. With one RGB unit as a first pixel unit and one RGBG unit as a second pixel unit, two first pixel units can be set in the pixel space corresponding to a second pixel unit, so that the resolution (PPI) of the first display area can be equivalent to the resolution of the second display area. Moreover, since the display effect of the RGB arrangement with a resolution (PPI) of a can be equivalent to a PPI of a*[2 ∧ (1 / 2)], therefore, in this example, based on the pixel circuit deletion in the first display area to improve the light transmittance of the first display area, the arrangement of the first light-emitting elements is set to be different from the arrangement of the second light-emitting elements, so as to optimize the display effect of the first display area, thereby improving the display uniformity of the first display area and the second display area.

[0173] Figure 6 It is a partial top view schematic diagram of the first display area of ​​at least one embodiment of the utility model. Figure 6 , a partial top view of two rows (e.g., the kth row and the k+1th row) and two columns (e.g., the hth column and the h+1th column) of the display island area is shown, where k and h are both integers greater than 0. In some examples, such as Figure 6 As shown, the first display area may include: a plurality of display island areas and a plurality of light-transmitting areas A12. A single light-transmitting area A12 may be surrounded by two display island areas in the first direction X and may be surrounded by two display island areas in the second direction Y.

[0174] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer and a light emitting structure layer disposed on the substrate. The light emitting structure layer may be located on a side of the circuit structure layer away from the substrate. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light emitting structure layer of the first display area may include a plurality of first light emitting elements.

[0175] In some examples, the circuit structure layer may include: a shielding layer, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer arranged on the substrate. A buffer layer may be arranged between the shielding layer and the first semiconductor layer. A first insulating layer may be arranged between the first semiconductor layer and the first conductive layer, a second insulating layer may be arranged between the first conductive layer and the second conductive layer, a third insulating layer may be arranged between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be arranged between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be arranged between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be arranged between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be arranged between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be arranged on the side of the sixth conductive layer away from the substrate. In some examples, the buffer layer, the first insulating layer to the sixth insulating layer may be an inorganic insulating layer, and the seventh insulating layer to the ninth insulating layer may be an organic insulating layer. This embodiment is not limited to this. In other examples, the shielding layer may be omitted. In other examples, an insulating layer may be arranged between the fourth conductive layer and the fifth conductive layer. In some other examples, two insulating layers may be provided on the side of the sixth conductive layer away from the substrate to improve the planarization effect of the anode layer.

[0176] In some examples, the light emitting structure layer may include: an anode layer, a pixel definition layer, an organic light emitting layer, and a cathode layer sequentially arranged on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light emitting layer may be connected to the anode layer, the cathode layer may be connected to the organic light emitting layer, and the organic light emitting layer may emit light of corresponding colors under the drive of the anode layer and the cathode layer.

[0177] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate. The "patterning process" mentioned in the present utility model includes the processes of coating photoresist, mask exposure, development, etching, stripping photoresist, etc. for metal materials, inorganic materials or transparent conductive materials, and includes the processes of coating organic materials, mask exposure and development, etc. for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited by the present utility model. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0178] The “A and B are arranged in the same layer” mentioned in the present invention means that A and B are formed simultaneously through the same patterning process, or the distance between the surfaces of A and B close to the substrate side and the substrate is basically the same, or the surfaces of A and B close to the substrate side are in direct contact with the same film layer. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present invention, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present invention refers to the shape of the orthographic projection of A on the substrate.

[0179] The following takes four first pixel circuits (for example, including first pixel circuits 11a, 11b, 11c and 11d) in a display island area of ​​the first display area (for example, a display island area located in the kth row and the hth column) as an example to illustrate the film layer of the circuit structure layer. This example is explained by taking the first pixel circuit as the aforementioned 8T1C structure as an example. Among them, the first pixel circuit 11a may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a and a storage capacitor; the first pixel circuit 11b may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can refer to Figure 2 The equivalent circuit diagram is shown.

[0180] In some examples, the preparation process of the display substrate may include the following steps.

[0181] (1) Provide a substrate. In some examples, the substrate may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the water and oxygen resistance of the substrate.

[0182] (2) Forming a shielding layer. In some examples, a shielding film is deposited on the substrate, and the shielding film is patterned by a patterning process to form a shielding layer disposed on the substrate. In some examples, the shielding layer may also be referred to as a bottom shielding metal layer (BSM).

[0183] Figure 7 for Figure 6 Schematic diagram of the first display area after the shielding layer is formed in FIG. Figure 7 As shown, the shielding layer of the first display area may include at least: a shielding block 300 located in the display island area. Each display island area may be provided with a shielding block 300. The shielding blocks 300 of the display island areas in adjacent rows of the display island areas in adjacent columns may be interconnected as an integrated structure. The plurality of shielding blocks 300 of the first display area may be interconnected as an integrated structure.

[0184] In some examples, such as Figure 7As shown, the shielding block 300 located in the display island area may have two first hollow parts 301, two second hollow parts 302, two third hollow parts 303 and two fourth hollow parts 304. The shielding block 300 may be roughly symmetrical about the second center line O2. The two first hollow parts 301 may be roughly symmetrical about the second center line O2, and a single first hollow part 301 may be roughly symmetrical about the first center line O1 or the third center line O3. The second hollow part 302, the third hollow part 303 and the fourth hollow part 304 may be located on one side of the first hollow part 301 in the opposite direction of the second direction Y, and the fourth hollow part 304 may be located between the second hollow part 302 and the third hollow part 303 in the first direction X. One second hollow part 302 and one third hollow part 303 may be roughly symmetrical about the first center line O1, and another second hollow part 302 and another third hollow part 303 may be roughly symmetrical about the third center line O3. One fourth hollow portion 304 may be substantially symmetrical about the first center line O1, and another fourth hollow portion 304 may be substantially symmetrical about the third center line O3. In this example, a light shielding block is provided in the display island area to provide a light shielding effect for the first type transistor of the first pixel circuit in the display island area, and by providing a hollow portion in the light shielding block, it is possible to avoid using a large area of ​​metal to cause parasitic capacitance between other metal film layers, thereby affecting the display effect.

[0185] In some examples, the shielding layer may extend to the peripheral area and be electrically connected to the first power supply line in the peripheral area to receive the first voltage signal to avoid affecting other signal routings.

[0186] (3) Forming a first semiconductor layer. In some examples, a buffer film and a first semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the first semiconductor film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the buffer layer. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0187] Fig. 8A for Figure 6 Schematic diagram of the first display area after the first semiconductor layer is formed. Figure 8B for Fig. 8A Schematic diagram of the first semiconductor layer in FIG. Fig. 8A and Figure 8BAs shown, the first semiconductor layer of the first display area may include at least: active layers of multiple first type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor; the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor).

[0188] In some examples, such as Fig. 8A and Figure 8B As shown, the first semiconductor layer patterns of the first pixel circuits 11a and 11b in the display island area may be substantially symmetrical about the first center line O1, the first semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetrical about the second center line O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the third center line O3. The first semiconductor layer patterns of the first pixel circuits 11a and 11b and the first semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the second center line O2. The first semiconductor layer patterns of different display island areas may be independent of each other.

[0189] In some examples, such as Fig. 8A and Figure 8B As shown, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer and the seventh active layer of the four first pixel circuits in the display island area can be an integrated structure connected to each other. Among them, the seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b can be directly connected, the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c can be directly connected, and the seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d can be directly connected.

[0190] In some examples, such as Fig. 8A and Figure 8BAs shown, the first semiconductor layer pattern of the first pixel circuit 11a is taken as an example for description. The first active layer 310a and the fourth active layer 340a of the first pixel circuit 11a may be located on one side of the third active layer 330a along the second direction Y, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a and the eighth active layer 380a may be located on one side of the third active layer 330a in the opposite direction of the second direction Y. The first active layer 310a, the sixth active layer 360a and the seventh active layer 370a may be aligned in the second direction Y.

[0191] In some examples, the shape of the third active layer 330a may be approximately U-shaped, the shape of the fourth active layer 340a may be approximately I-shaped, and the shapes of the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a may be approximately L-shaped. However, this embodiment is not limited to this. The arrangement and shape of the first semiconductor layer pattern of the first pixel circuits 11b, 11c, and 11d are similar to the arrangement and shape of the first semiconductor layer pattern of the first pixel circuit 11a, so they are not repeated here.

[0192] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and has semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors. This embodiment is not limited to this.

[0193] In some examples, such as Fig. 8A As shown, the orthographic projection of the blocking layer of the first display area on the substrate may partially overlap with the orthographic projection of the first semiconductor layer on the substrate. The orthographic projection of the blocking block 300 of the display island area on the substrate may cover the orthographic projections of the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, the seventh active layer and the eighth active layer of the four first pixel circuits on the substrate, and partially overlap with the orthographic projection of the first active layer on the substrate. For example, the orthographic projection of the blocking block 300 on the substrate may cover the orthographic projection of the channel region of the active layer of the first type transistor of the four first pixel circuits on the substrate. In this example, by setting a blocking layer to block the channel region of the active layer of the first type transistor located in the first semiconductor layer, it is possible to prevent external light from affecting the transistor of the pixel circuit, thereby ensuring the performance of the transistor.

[0194] (4) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0195] Fig.9A for Figure 6 Schematic diagram of the first display area after the first conductive layer is formed. Fig. 9B for Fig.9A Schematic diagram of the first conductive layer and the first semiconductor layer in FIG. Fig. 9C for Fig.9A Schematic diagram of the first conductive layer in FIG. 9A to 9C As shown, the first conductive layer of the first display area may include at least: a first scanning transmission segment 251 of multiple first scanning lines (for example, including first scanning lines GL1(k), GL1(k+1)), a light-emitting control transmission segment 261 of multiple light-emitting control lines (for example, including light-emitting control lines EML(k), EML(k+1)), multiple first reset control lines (for example, including first reset control lines RST1(k), RST1(k+1), RST1(k+2)), multiple second reset control lines (for example, including second reset control lines RST2(k-1), RST2(k), RST2(k+1)), and first electrodes of storage capacitors of multiple first pixel circuits (for example, including first electrodes 391a, 391b).

[0196] In some examples, the first scan transmission segment 251 and the light emission control transmission segment 261 may be located in the display island region where the connected first pixel circuit is located. The first scan transmission segment 251 of the first scan line GL1(k) may be located on one side of the first electrode (e.g., first electrode 391a, 391b) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1(k) may be located on one side of the first scan transmission segment 251 of the first scan line GL1(k) in the second direction Y. The light emission control transmission segment 261 of the light emission control line EML(k) may be located on one side of the first electrode (e.g., first electrode 391a, 391b) of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y, and the second reset control line RST2(k) may be located on one side of the light emission control transmission segment 261 of the light emission control line EML(k) in the opposite direction of the second direction Y. The first reset control line RST1(k+1) may be located on one side of the second reset control line RST2(k) in the opposite direction of the second direction Y.

[0197] In some examples, the first reset control line RST1(k) may be located at one side of the light-transmitting area A12 in the kth row and the h+1th column in the second direction Y, and the line segment of the first reset control line RST1(k) close to the light-transmitting area A12 may be substantially a straight line extending along the first direction X. The second reset control line RST2(k) may be located at one side of the light-transmitting area A12 in the kth row and the h+1th column in the opposite direction of the second direction Y, and the line segment of the second reset control line RST2(k) close to the light-transmitting area A12 may be substantially a straight line extending along the first direction X. The first scan line GL1(k) bypasses the light-transmitting area A12 from one side of the light-transmitting area A12 in the second direction Y using the first scan connection line, and the light-emitting control line EML(k) bypasses the light-transmitting area A12 from one side of the light-transmitting area A12 in the opposite direction of the second direction Y using the light-emitting control connection line. The routing arrangement of the first conductive layer in this example may be beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area.

[0198] In some examples, the shape of the line segment of the first reset control line RST1(k) located in the display island region where the connected first pixel circuit is located can be substantially in the shape of a folded line extending along the first direction X. For example, in the display island region of the kth row and the hth column, the overlapping region of the first reset control line RST1(k) and the first active layers of the four first pixel circuits can serve as the gates of the first transistors of the four first pixel circuits (for example, including the gate of the first transistor 31a and the gate of the first transistor 31b).

[0199] In some examples, the shape of the first scan transmission segment 251 of the first scan line GL1(k) may be substantially a zigzag line extending along the first direction X. For example, in the display island region of the kth row and the hth column, the overlapping region of the first scan transmission segment 251 of the first scan line GL1(k) and the fourth active layers of the four first pixel circuits may serve as the gates of the fourth transistors of the four first pixel circuits (e.g., including the gates of the fourth transistor 34a and the gates of the fourth transistor 34b).

[0200] In some examples, the shape of the light-emitting control transmission segment 261 of the light-emitting control line EML(k) may be approximately a zigzag line extending along the first direction X. For example, in the display island area of ​​the kth row and the hth column, the overlapping area of ​​the light-emitting control transmission segment 261 of the light-emitting control line EML(k) and the fifth active layer of the four first pixel circuits may be used as the gate of the fifth transistor of the four first pixel circuits (for example, including the gate of the fifth transistor 35a, 35b), and the overlapping area of ​​the light-emitting control transmission segment 261 of the light-emitting control line EML(k) and the sixth active layer of the four first pixel circuits may be used as the gate of the sixth transistor of the four first pixel circuits (for example, including the gate of the sixth transistor 36a, 36b).

[0201] In some examples, the shape of the line segment of the second reset control line RST2(k) located in the display island region where the connected first pixel circuit is located can be roughly in the shape of a folded line extending along the first direction X. For example, in the display island region of the kth row and the hth column, the overlapping region of the second reset control line RST2(k) and the seventh active layer of the four first pixel circuits can be used as the gate of the seventh transistor of the four first pixel circuits (for example, including the gate of the seventh transistor 37a, 37b), and the overlapping region of the second reset control line RST2(k) and the eighth active layer of the four first pixel circuits can be used as the gate of the eighth transistor of the four first pixel circuits (for example, including the gate of the eighth transistor 38a, 38b).

[0202] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b. The orthographic projections of the first electrodes 391a and 391b on the substrate can be roughly rectangular. This embodiment is not limited to this.

[0203] (5) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0204] Fig. 10A for Figure 6 Schematic diagram of the first display area after the second conductive layer is formed. Fig. 10B for Fig. 10A Schematic diagram of the second conductive layer in FIG. Fig. 10A and Fig. 10B As shown, the second conductive layer of the first display area may include at least: a second scanning auxiliary transmission segment 271 of multiple second scanning auxiliary lines (for example, including second scanning auxiliary lines GL2b(k), GL2b(k)), second electrodes of storage capacitors of multiple first pixel circuits (for example, including second electrodes 392a, 392b), and an initial signal connection segment 292 of multiple third initial signal lines (for example, including third initial signal lines INIT3(k-1), INIT3(k), INIT3(k+1)).

[0205] In some examples, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) may be located in the display island region where the connected first pixel circuit is located. The shape of the second scanning auxiliary transmission segment 271 may be substantially a fold line extending along the first direction X. For example, in the display island region of the kth row and the hth column, the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) may be located on one side of the second electrode (e.g., the second electrodes 392a and 392b) of the storage capacitor of the first pixel circuit in the second direction Y.

[0206] In some examples, within the display island area, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate may be roughly a rectangular structure having a hollow area, and the orthographic projection of the hollow area on the substrate may be roughly a rectangle, and the rectangle may have rounded corners or chamfers. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b may be electrically connected through a first plate connection block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c may be electrically connected through a second plate connection block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d may be electrically connected through another first plate connection block 392-1. The side of the second electrode 392a of the storage capacitor of the first pixel circuit 11a away from the first pixel circuit 11b can be connected to a second plate connection block 392-2, and the side of the second electrode of the storage capacitor of the first pixel circuit 11d away from the first pixel circuit 11c can be electrically connected to another second plate connection block 392-2. The length of the first plate connection block 392-1 along the second direction Y can be less than the length of the second plate connection block 392-2 along the second direction Y. The second electrode of the storage capacitor can subsequently be electrically connected to the first power line through the second plate connection block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits in the first display island area can be an integrated structure that is interconnected, which is conducive to ensuring the uniform transmission of the first voltage signal along the first direction X.

[0207] In some examples, the initial signal connection segment 292 of the third initial signal line INIT3(k) may be located in adjacent rows and adjacent columns of the display island area where the connected first pixel circuit is located. For example, the initial signal connection segment 292 of the third initial signal line INIT3(k) connected to the first pixel circuit in the display island area of ​​the kth row and the hth column may be located in the display island area of ​​the k+1th row and the h+1th column, and may be located on one side of the light-transmitting area A12 of the kth row and the h+1th column in the opposite direction of the second direction Y. The shape of the initial signal connection segment 292 may be roughly a straight line extending along the first direction X. The initial signal connection segment 292 may be configured to connect the initial signal transmission segments in the adjacent display island areas formed subsequently, so as to realize the transmission of the third initial signal along the first direction X in the first display area.

[0208] (6) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0209] Fig.11A for Figure 6 Schematic diagram of the first display area after the second semiconductor layer is formed. Fig. 11B for Fig.11A Schematic diagram of the second semiconductor layer in FIG. Fig.11A and Fig. 11B As shown, the second semiconductor layer of the first display area may include at least: an active layer of a second type transistor of a plurality of first pixel circuits (for example, including: a second active layer 320a of the second transistor 32a of the first pixel circuit 11a, a second active layer 320b of the second transistor 32b of the first pixel circuit 11b).

[0210] In some examples, within the display island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the third center line O3. The second semiconductor layer patterns of the first pixel circuits 11a and 11b and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the second center line O2.

[0211] In some examples, the second active layers 320a and 320b may be shaped substantially like an inverted L. The overlapping region between the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second active layer 320a may serve as the bottom gate of the second transistor 32a, and the overlapping region between the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second active layer 320b may serve as the bottom gate of the second transistor 32b.

[0212] In some examples, the orthographic projection of the second semiconductor layer on the substrate may partially overlap with the orthographic projection of the shielding layer on the substrate. The orthographic projection of the channel region of the second active layer on the substrate may not overlap with the orthographic projection of the shielding layer on the substrate. For example, the orthographic projection of the channel region of the second active layers 320a and 320b on the substrate may be located within the orthographic projection range of the first hollow area 301 on the substrate.

[0213] (7) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0214] Fig. 12A for Figure 6 Schematic diagram of the first display area after the third conductive layer is formed. Fig. 12B for Fig. 12A Schematic diagram of the third conductive layer in FIG. In some examples, such as Fig. 12A and Fig. 12B As shown, the third conductive layer of the first display area may include at least: a second scanning transmission segment 281 of multiple second scanning lines (for example, including second scanning lines GL2(k), GL2(k+1)), multiple first initial signal lines (for example, including first initial signal lines INIT1(k), INIT1(k+1), INIT1(k+2)), multiple second initial signal lines (for example, including second initial signal lines INIT2(k-1), INIT2(k), INIT2(k+1)), and an initial signal transmission segment 291 of multiple third initial signal lines (for example, including third initial signal lines INIT3(k), INIT3(k+1)).

[0215] In some examples, in the display island area, the second scan transmission segment 281 of the first initial signal line INIT1(k) and the second scan line GL2(k) may be located on one side of the storage capacitor along the second direction Y, and the initial signal transmission segments 291 of the second initial signal line INIT2(k) and the third initial signal line INIT3(k) may be located on one side of the storage capacitor in the opposite direction of the second direction Y. The first initial signal line INIT1(k) may be located on one side of the second scan transmission segment 281 of the second scan line GL2(k), the initial signal transmission segment 291 of the third initial signal line INIT3(k) and the second initial signal line INIT2(k) may be located on one side of the second scan transmission segment 281 of the second scan line GL2(k) in the opposite direction of the second direction Y, and the second initial signal line INIT2(k) may be located on one side of the initial signal transmission segment 291 of the third initial signal line INIT3(k) in the opposite direction of the second direction Y.

[0216] In some examples, the first initial signal line INIT1(k) may be located on one side of the light-transmitting area A12 in the kth row and the h+1th column in the second direction Y. The second initial signal line INIT2(k) may be located on one side of the light-transmitting area A12 in the kth row and the h+1th column in the opposite direction of the second direction Y. The shape of the line segment of the first initial signal line INIT1(k) located in the display island area where the connected first pixel circuit is located may be roughly in the shape of a folded line extending along the first direction X. The shape of the line segment of the first initial signal line INIT1(k) adjacent to the light-transmitting area A12 may be roughly in the shape of a straight line extending along the first direction X. The shape of the line segment of the second initial signal line INIT2(k) located in the display island area where the connected first pixel circuit is located may be roughly in the shape of a folded line extending along the first direction X. The shape of the line segment of the second initial signal line INIT2(k) adjacent to the light-transmitting area A12 may be roughly in the shape of a straight line extending along the first direction X. The routing arrangement of the third conductive layer of this example may be beneficial to increasing the area of ​​the light-transmitting area and improving the light transmittance of the first display area.

[0217] In some examples, the orthographic projection of the first initial signal line INIT1(k) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(k) on the substrate. For example, the orthographic projection of the first initial signal line INIT1(k) on the substrate may include the orthographic projection of the first reset control line RST1(k) on the substrate. The orthographic projection of the second scanning transmission segment 281 of the second scanning line GL2(k) on the substrate may partially overlap with the orthographic projection of the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) on the substrate. The orthographic projection of the initial signal transmission segment 291 of the third initial signal line INIT3(k) on the substrate may partially overlap with the orthographic projection of the light emission control transmission segment 261 of the light emission control line EML(k) on the substrate. The orthographic projection of the second initial signal line INIT2(k) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(k) on the substrate. For example, the orthographic projection of the second initial signal line INIT2(k) on the substrate may include the orthographic projection of the second reset control line RST2(k) on the substrate. In this example, by stacking the wiring of different conductive layers (for example, including the first conductive layer, the second conductive layer, and the third conductive layer), it is possible to avoid occupying too much wiring space, which is beneficial to saving wiring space, thereby improving the light transmittance of the first display area.

[0218] (8) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0219] Fig.13 for Figure 6 Schematic diagram of the first display area after the fifth insulating layer is formed in FIG. Fig.13 As shown, the fifth insulating layer of the first display area may be provided with a plurality of vias, for example, may include a first type via (for example, including the first via V1 to the nineteenth via V19), a second type via (for example, including the twenty-first via V21, the twenty-second via V22, the thirty-fifth via V35, and the thirty-eighth via V38), a third type via (for example, including the twenty-third via V23, the twenty-fourth via V24, the thirty-seventh via V37, and the fortieth via V40), a plurality of fourth type vias (for example, including the thirty-first via V31 to the thirty-fourth via V34) and a plurality of fifth type vias (for example, including the twenty-fifth via V25 to the twenty-ninth via V29, the thirty-sixth via V36, and the thirty-ninth via V39).

[0220] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first type via can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second type via can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the third type via can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer in the fourth type via can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer in the fifth type via can be removed to expose a portion of the surface of the third conductive layer.

[0221] In some examples, the first type via, the second type via, and the third type via may be formed by a same patterning process, and the fourth type via and the fifth type via may be formed by a same patterning process.

[0222] (9) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source-drain metal layer.

[0223] Fig.14A for Figure 6 Schematic diagram of the first display area after the fourth conductive layer is formed. Fig. 14B for Fig.14A Schematic diagram of the fourth conductive layer in FIG. In some examples, such as Fig.14A and Fig. 14B As shown, the fourth conductive layer of the first display area may include at least: a plurality of pixel connection electrodes (for example, including the first pixel connection electrode 401 to the seventeenth pixel connection electrode 417), a plurality of routing conversion electrodes (for example, including the first routing conversion electrode 283, the second routing conversion electrode 293), a first scanning connection segment 252 of a plurality of first scanning lines (for example, including the first scanning line GL1(k), GL1(k+1)), and a light-emitting control connection segment 262 of a plurality of light-emitting control lines (for example, including the light-emitting control line EML(k), EML(k+1)).

[0224] In some examples, the shape of the first pixel connection electrode 401 may be substantially rectangular. The first pixel connection electrode 401 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the third via hole V3.

[0225] In some examples, the shape of the second pixel connection electrode 402 may be substantially a strip extending along the second direction Y. One end of the second pixel connection electrode 402 may be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through the thirty-first via hole V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a through the twenty-first via hole V21. The second pixel connection electrode 402 is electrically connected to the gate of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a, and the second pixel connection electrode 402 may serve as the first node of the first pixel circuit 11a.

[0226] In some examples, the shape of the third pixel connection electrode 403 may be substantially a strip extending along the second direction Y. One end of the third pixel connection electrode 403 may be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the second via hole V2, and the other end may be electrically connected to the second active layer 320a of the second transistor 32a through the thirty-second via hole V32, and may also be electrically connected to the third active layer of the third transistor 33a through the sixth via hole V6. The third pixel connection electrode 403 may serve as a third node of the first pixel circuit 11a.

[0227] In some examples, the shape of the fourth pixel connection electrode 404 may be substantially a zigzag shape extending along the second direction Y. The fourth pixel connection electrode 404 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the fourth via hole V4, and may also be electrically connected to the eighth active layer 380a of the eighth transistor 38a through the eighth via hole V8.

[0228] In some examples, the fifth pixel connection electrode 405 may be shaped substantially like a strip extending along the second direction Y. The fifth pixel connection electrode 405 may be electrically connected to the fifth active layer 350a of the fifth transistor 35a of the first pixel circuit 11a through the fifth via hole V5, and may also be electrically connected to the second plate connection block 392-2 connected to the second electrode 392a of the storage capacitor of the first pixel circuit 11a through the twenty-third via hole V23, thereby achieving electrical connection with the second electrode 392a of the storage capacitor of the first pixel circuit 11a.

[0229] In some examples, the shape of the sixth pixel connection electrode 406 may be substantially rectangular. The sixth pixel connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through the seventh via hole V7.

[0230] In some examples, the shape of the seventh pixel connection electrode 407 may be substantially L-shaped. The seventh pixel connection electrode 407 may be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a through the ninth via hole V9, and may also be electrically connected to the initial signal transmission section 291 of the third initial signal line INIT3(k) through the twenty-sixth via hole V26.

[0231] In some examples, the shape of the eighth pixel connection electrode 408 may be substantially a strip extending along the second direction Y. The eighth pixel connection electrode 408 may be electrically connected to the seventh active layer 370a of the seventh transistor 37a of the first pixel circuit 11a through the tenth via hole V10, and may also be electrically connected to the second initial signal line INIT2(k) through the twenty-seventh via hole V27.

[0232] In some examples, the shape of the ninth pixel connection electrode 409 may be approximately a flat 8-shaped shape. One end of the ninth pixel connection electrode 409 may be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through the first via hole V1, and the other end may be electrically connected to the first initial signal line INIT1(k) through the twenty-fifth via hole V25.

[0233] In some examples, the shape of the tenth pixel connection electrode 410 may be approximately a flat 8-shaped shape. One end of the tenth pixel connection electrode 410 may be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the eleventh via hole V11, and the other end may be electrically connected to the first initial signal line INIT1(k) through the twenty-eighth via hole V28.

[0234] In some examples, the eleventh pixel connection electrode 411 may be substantially rectangular in shape. The eleventh pixel connection electrode 411 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the thirteenth via hole V13.

[0235] In some examples, the shape of the twelfth pixel connection electrode 412 may be substantially a strip extending along the second direction Y. One end of the twelfth pixel connection electrode 412 may be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b through the thirty-third via hole V31, and the other end may be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b through the twenty-second via hole V22. The twelfth pixel connection electrode 412 is electrically connected to the gate of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b, and the twelfth pixel connection electrode 412 may serve as the first node of the first pixel circuit 11b.

[0236] In some examples, the shape of the thirteenth pixel connection electrode 413 may be substantially a strip extending along the second direction Y. One end of the thirteenth pixel connection electrode 413 may be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the twelfth via hole V12, and the other end may be electrically connected to the second active layer 320b of the second transistor 32b through the thirty-fourth via hole V34, and may also be electrically connected to the third active layer 330b of the third transistor 33b through the sixteenth via hole V16. The thirteenth pixel connection electrode 413 may serve as the third node of the first pixel circuit 11b.

[0237] In some examples, the shape of the fourteenth pixel connection electrode 414 may be substantially a zigzag shape extending along the second direction Y. The fourteenth pixel connection electrode 414 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the fourteenth via hole V14, and may also be electrically connected to the eighth active layer 380b of the eighth transistor 38b through the eighteenth via hole V18.

[0238] In some examples, the shape of the fifteenth pixel connection electrode 415 may be substantially a strip extending along the second direction Y. The fifteenth pixel connection electrode 415 may be electrically connected to the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b through the fifteenth via hole V15, and may also be electrically connected to the second plate connection block 392-2 connected to the second electrode 392b of the storage capacitor of the first pixel circuit 11b through the twenty-fourth via hole V24, thereby achieving electrical connection with the second electrode 392b of the storage capacitor of the first pixel circuit 11b.

[0239] In some examples, the shape of the sixteenth pixel connection electrode 416 may be substantially rectangular. The sixteenth pixel connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the seventeenth via hole V17.

[0240] In some examples, the shape of the seventeenth pixel connection electrode 417 may be substantially L-shaped. The seventeenth pixel connection electrode 417 may be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b through the nineteenth via hole V19, and may also be electrically connected to the initial signal transmission section 291 of the third initial signal line INIT3(k) through the twenty-ninth via hole V29.

[0241] In some examples, within the display island area, the first pixel circuits 11a and 11b may be roughly symmetrical about the second center line O2, the first pixel circuits 11c and 11d may be roughly symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, the first pixel circuits 11c and 11d may be roughly symmetrical about the first center line O1.

[0242] In some examples, the shape of the first routing switching electrode 283 can be substantially L-shaped. The first routing switching electrode 283 can be connected to the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) through the thirty-seventh via hole V37, and can also be connected to the second scanning transmission segment 281 of the second scanning line GL2(k) through the thirty-sixth via hole V36.

[0243] In some examples, the shape of the second routing transfer electrode 293 can be roughly rectangular. The second routing transfer electrode 293 can be connected to the initial signal transmission segment 291 located in the third conductive layer through the thirty-ninth via hole V39, and can also be connected to the initial signal connection segment 292 located in the second conductive layer through the fortieth via hole V40. In this example, the two ends of the initial signal connection segment 292 can be connected to the initial signal transmission segments 291 located in the same row and in two adjacent display islands through the second routing transfer electrode 293, thereby realizing the transmission of the third initial signal along the first direction X.

[0244] In some examples, the shape of the first scan connection segment 252 of the first scan line GL1(k) may be roughly a fold line extending along the first direction X. The first scan connection segment 252 of the first scan line GL1(k) may be located on one side of the light-transmitting area A12 of the kth row and the h+1th column along the second direction Y. The first scan connection segment 252 may, for example, be located in the display island area of ​​the k-1th row and the h+1th column. The orthographic projection of the first scan connection segment 252 on the substrate may partially overlap with the orthographic projection of the first reset control line RST1(k) and the first initial signal line INIT1(k) on the substrate. One end of the first scan connection segment 252 may be connected to the first scan transmission segment 251 located in the first conductive layer in the display island area of ​​the kth row and the hth column through the thirty-fifth via hole V35, and the other end may be connected to the first scan transmission segment in the display island area of ​​the kth row and the h+1th column. The first scan connection segment 252 may connect the first scan transmission segments in two adjacent display island areas along the first direction X, thereby realizing the transmission of the first scan signal along the first direction X.

[0245] In some examples, the shape of the light-emitting control connection segment 262 of the light-emitting control line EML(k) may be roughly a fold line extending along the first direction X. The light-emitting control connection segment 262 of the light-emitting control line EML(k) may be located on the side of the light-transmitting area A12 of the kth row and the h+1th column in the opposite direction of the second direction Y. The light-emitting control connection segment 262 may, for example, be located in the display island area of ​​the k+1th row and the h+1th column. The orthographic projection of the light-emitting control connection segment 262 on the substrate may partially overlap with the orthographic projection of the second reset control line RST2(k), the second initial signal line INIT2(k) and the initial signal connection segment 292 on the substrate. One end of the light-emitting control connection segment 262 may be connected to the light-emitting control transmission segment 261 located in the first conductive layer in the display island area of ​​the kth row and the hth column through the thirty-eighth via V38, and the other end may be connected to the light-emitting control transmission segment in the display island area of ​​the kth row and the h+1th column. The light-emitting control connecting segment 262 can connect the light-emitting control transmission segments in two adjacent display islands along the first direction X, thereby realizing the transmission of the light-emitting control signal along the first direction X.

[0246] (10) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated, and the seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0247] Fig.15 for Figure 6 Schematic diagram of the first display area after the seventh insulating layer is formed in FIG. Fig.15 As shown, the seventh insulating layer of the first display area may be provided with a plurality of via holes, for example, may include: the 41st via hole V41 to the 47th via hole V47. The seventh insulating layer and the sixth insulating layer in the 41st via hole V41 to the 47th via hole V47 may be removed to expose part of the surface of the fourth conductive layer.

[0248] (11) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source-drain metal layer.

[0249] Fig.16A for Figure 6 Schematic diagram of the first display area after the fifth conductive layer is formed. Fig. 16B for Fig.16A Schematic diagram of the fifth conductive layer in FIG. Fig.16A and Fig. 16BAs shown, the fifth conductive layer of the first display area may include at least: a plurality of data lines (for example, data lines DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7), DL(j+8)), a plurality of first anode connection electrodes (for example, first anode connection electrodes 422a, 422b, 422c, and 422d), a plurality of first power connection electrodes (for example, first power connection electrodes 423a, 423b, and 423c), a plurality of first shielding electrodes (for example, first shielding electrodes 421a and 421b), and a second scan connection segment 282 of a plurality of second scan lines (for example, second scan lines GL2(k), GL2(k+1)). Wherein, j is an integer greater than 0.

[0250] In some examples, the plurality of data lines may be roughly in the shape of a folded line extending along the second direction Y. The four first pixel circuits in each display island region may be electrically connected to the four data lines in a one-to-one correspondence. The data line DL(j) may be electrically connected to the first pixel connection electrode 401 through the forty-first via hole V41, thereby being electrically connected to the fourth transistor of the first pixel circuit 11a. The data line DL(j+1) may be electrically connected to the eleventh pixel connection electrode 411 through the forty-fifth via hole V45, thereby being electrically connected to the fourth transistor of the first pixel circuit 11b. The data line DL(j+2) may be electrically connected to the fourth transistor of the first pixel circuit 11c. The data line DL(j+3) may be electrically connected to the fourth transistor of the first pixel circuit 11d.

[0251] In some examples, the four data lines electrically connected to the four first pixel circuits in the display island area can be divided into two groups to bypass the light-transmitting area A12 adjacent to the display island area in the second direction Y. For example, the data line DL(j) connected to the first pixel circuit 11a and the data line DL(j+1) connected to the first pixel circuit 11b can bypass the light-transmitting area A12 located in the hth column from the side in the opposite direction of the first direction X, and the data line DL(j+2) connected to the first pixel circuit 11c and the data line DL(j+3) connected to the first pixel circuit 11d can bypass the light-transmitting area A12 located in the hth column from one side of the first direction X. In this example, by setting the data lines to bend and bypass the light-transmitting area, it is beneficial to reduce the space occupied by the wiring, thereby improving the light transmittance of the first display area.

[0252] In some examples, the shape of the first anode connection electrodes 422a, 422b, 422c and 422d can be substantially rectangular. The first anode connection electrodes 422a and 422b can be located between the data lines DL(j) and DL(j+1), and the first anode connection electrodes 422c and 422d can be located between the data lines DL(j+2) and DL(j+3).

[0253] In some examples, the first anode connection electrode 422a may be electrically connected to the sixth pixel connection electrode 406 through the forty-third via hole V43, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 422b may be electrically connected to the sixteenth pixel connection electrode 416 through the forty-sixth via hole V46, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 422c may be electrically connected to the sixth transistor of the first pixel circuit 11c. The first anode connection electrode 422d may be electrically connected to the sixth transistor of the first pixel circuit 11d.

[0254] In some examples, the shapes of the first power connection electrodes 423a, 423b and 423c can be substantially rectangular. The first power connection electrode 423a can be located between the data lines DL(j) and DL(j-1), the first power connection electrode 423b can be located between the data lines DL(j+1) and DL(j+2), and the first power connection electrode 423c can be located between the data lines DL(j+3) and DL(j+4).

[0255] In some examples, the first power connection electrode 423a can be electrically connected to the fifth pixel connection electrode 405 through the 42nd via hole V42, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuit 11a. The second power connection electrode 423b can be electrically connected to the fifteenth pixel connection electrode 415 through the 44th via hole V44, thereby achieving electrical connection with the fifth transistor and storage capacitor of the first pixel circuits 11b and 11c. The third power connection electrode 423c can be electrically connected to the fifth transistor and storage capacitor of the first pixel circuit 11d.

[0256] In some examples, the shape of the first shielding electrodes 421a and 421b can be roughly n-shaped. The first shielding electrode 421a can be located between the data lines DL(j) and DL(j+1), and the first shielding electrode 421b can be located between the data lines DL(j+2) and DL(j+3). The positive projection of the first shielding electrode 421a on the substrate can cover the positive projection of the second pixel connection electrode 402 and the twelfth pixel connection electrode 412 on the substrate, and can achieve shielding of the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the influence of the remaining signals on the first nodes of the first pixel circuits 11a and 11b. The second shielding electrode 421b can achieve shielding of the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of the remaining signals on the first nodes of the first pixel circuits 11c and 11d.

[0257] In some examples, the shape of the second scan connection segment 282 of the second scan line GL2(k) may be approximately a fold line extending along the first direction X. The second scan connection segment 282 of the second scan line GL2(k) may be located on one side of the light-transmitting area A12 of the kth row and the h+1th column along the second direction Y. The second scan connection segment 282 may, for example, be located in the display island area of ​​the k-1th row and the h+1th column. The orthographic projection of the second scan connection segment 282 on the substrate may partially overlap with the orthographic projection of the first scan connection segment 252, the first reset control line RST1(k), and the first initial signal line INIT1(k) on the substrate. One end of the second scan connection segment 282 can be connected to the first routing transfer electrode 283 in the display island area of ​​the kth row and the hth column through the forty-seventh via hole V47, so as to realize the connection with the second scan transmission segment 281 and the second scan auxiliary transmission segment 271 in the display island area of ​​the kth row and the hth column, and the other end of the second scan connection segment 282 can be connected to the second scan transmission segment 281 and the second scan auxiliary transmission segment 271 in the display island area of ​​the kth row and the h+1th column. The second scan connection segment 282 can connect the second scan transmission segments in two adjacent display island areas along the first direction X, and can also connect the second scan auxiliary transmission segments in two adjacent display island areas along the first direction X, so as to realize the transmission of the second scan signal along the first direction X.

[0258] (12) Forming an eighth insulating layer. In some examples, an eighth insulating layer is coated on the substrate on which the aforementioned pattern is formed, and the eighth insulating layer is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second flat layer.

[0259] Fig.17 for Figure 6 Schematic diagram of the first display area after the eighth insulating layer is formed in FIG. Fig.17 As shown, the eighth insulating layer of the first display area may be provided with a plurality of via holes, for example, may include the fifty-first via hole V51 to the fifty-ninth via hole V59. The eighth insulating layer within the fifty-first via hole V51 to the fifty-ninth via hole V59 may be removed to expose part of the surface of the fifth conductive layer.

[0260] (13) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source-drain metal layer.

[0261] Fig.18A for Figure 6 Schematic diagram of the first display area after the sixth conductive layer is formed. Fig.18B for Fig.18A Schematic diagram of the sixth conductive layer in FIG. In some examples, such as Fig.18A and Fig.18B As shown, the sixth conductive layer of the first display area may include at least: a plurality of second anode connecting electrodes (for example, including second anode connecting electrodes 432a, 432b, 432c and 432d), a plurality of first voltage transmission lines (for example, including first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (for example, including second power connection electrodes 453a, 453b and 453c).

[0262] In some examples, the shape of the first voltage transmission lines 451a and 451b can be a zigzag shape extending along the second direction Y. The first voltage transmission lines 451a and 451b can be arranged at intervals along the first direction X. The first voltage transmission line 451a can be electrically connected to the first power connection electrode 423a through the fifty-third via V53, and the first voltage transmission line 451b can be electrically connected to the first power connection electrode 423c through the fifty-fifth via V55. The first voltage transmission lines 451a and 451b can access the first voltage signal. For example, the first voltage transmission lines 451a and 451b can extend to the peripheral area, and access the first voltage signal by being electrically connected to the first power supply line in the peripheral area.

[0263] In some examples, the shape of the power connection bar 452 may be roughly a straight line extending along the first direction X. The power connection bar 452 may connect two adjacent first voltage transmission lines 451a and 451b. The power connection bar 452 in a single display island area may be connected to three second power connection electrodes 453a, 453b, and 453c. The shape of the second power connection electrodes 453a, 453b, and 453c may be roughly a straight line extending along the second direction Y. The second power connection electrode 453a may be connected to the first shielding electrode 421a through the fifty-first via hole V51, the second power connection electrode 453b may be connected to the first power connection electrode 432b through the fifty-fourth via hole V54, and the second power connection electrode 453c may be connected to the second shielding electrode 421b through the fifty-second via hole V52. The power connection bar 452, the first voltage transmission lines 451a and 451b, and the plurality of second power connection electrodes 453a, 453b and 453c may be an integrated structure connected to each other, thereby forming a mesh connection structure for transmitting the first voltage signal in the first display area to ensure the transmission uniformity of the first voltage signal.

[0264] In some examples, the second anode connection electrode 432a can be located between the first voltage transmission line 451a and the second power connection electrode 453a, the second anode connection electrode 432b can be located between the second power connection electrodes 453a and 453b, the second anode connection electrode 432c can be located between the second power connection electrodes 453b and 453c, and the second anode connection electrode 432d can be located between the second power connection electrode 453c and the first voltage transmission line 451b.

[0265] In some examples, the shape of the second anode connection electrodes 432a, 432b, 432c and 432d can be substantially strip-shaped extending along the second direction Y. The second anode connection electrode 432a can be electrically connected to the first anode connection electrode 422a through the fifty-sixth via hole V56. The second anode connection electrode 432b can be electrically connected to the first anode connection electrode 422b through the fifty-seventh via hole V57. The second anode connection electrode 432c can be electrically connected to the first anode connection electrode 422c through the fifty-eighth via hole V58. The second anode connection electrode 432d can be electrically connected to the first anode connection electrode 422d through the fifty-ninth via hole V59.

[0266] In this example, the fifth conductive layer and the sixth conductive layer are arranged to arrange the data line and the first voltage transmission line, which can avoid that the conductive layer close to the anode layer has too many lines and affects the flatness of the anode layer. In addition, the first voltage transmission line is arranged in the sixth conductive layer and the data line is arranged in the fifth conductive layer, which can increase the distance between the data line and the anode layer, and avoid the data line transmission signal affecting the anode layer.

[0267] (14) Forming a ninth insulating layer. In some examples, a ninth insulating layer is coated on the substrate on which the aforementioned pattern is formed, and the ninth insulating layer is patterned by a patterning process to form the ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third flat layer.

[0268] Fig.19 for Figure 6 Schematic diagram of the first display area after the ninth insulating layer is formed in FIG. Fig.19 As shown, the ninth insulating layer of the first display area may be provided with a plurality of via holes, for example, may include the 61st to 64th via holes V61. The ninth insulating layer within the 61st to 64th via holes V61 may be removed to expose a portion of the surface of the sixth conductive layer.

[0269] At this point, the circuit structure layer can be prepared. The film structure of the circuit structure layer of the second display area is similar to that of the first display area, so it is not repeated here. Among them, the first scan line, the second scan line, the second scan auxiliary line, the light control line and the third initial signal line of the second display area may not adopt a segmented switching design.

[0270] (15) Forming a light-emitting structure layer. In some examples, an anode film is deposited on the substrate having the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer.

[0271] Fig. 20A for Figure 6 Schematic diagram of the first display area after the anode layer is formed. Fig. 20B for Fig. 20A Schematic diagram of the anode layer in FIG. In some examples, such as Fig. 20A and Fig. 20B As shown, the anode layer of the first display area may include at least: anodes of multiple first light-emitting elements (for example, including anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, and anode 131f of first light-emitting element 13f), multiple anode connection blocks (for example, including anode connection blocks 132a, 132b, 132c and 132d), and multiple anode connection strips (for example, including first anode connection strip 133 and second anode connection strip 134).

[0272] In some examples, the shapes of anodes 131a, 131b, 131c, 131d, 131e, and 131f may be substantially rectangular. Anode 131a may be located on one side of anode 131b in the second direction Y, and anode 131c may be located on one side of anodes 131a and 131b in the first direction X. Anode 131d may be located on one side of anode 131e in the second direction Y, and anode 131f may be located on one side of anodes 131d and 131e in the first direction X.

[0273] In some examples, the shape of the anode connection block 132a may be roughly hexagonal. The anode 131a and the anode connection block 132a may be an integrated structure connected to each other. The anode connection block 132a may be electrically connected to the second anode connection electrode 432a through the sixty-first via hole V61 to achieve electrical connection with the first pixel circuit 11a. The shapes of the anode connection blocks 132b, 132c and 132d may be roughly V-shaped. The anode 131b and the anode connection block 132b may be an integrated structure connected to each other. The anode connection block 132b may be electrically connected to the second anode connection electrode 432b through the sixty-second via hole V62 to achieve electrical connection with the first pixel circuit 11b. The anode 131c and the anode connection block 132c may be an integrated structure connected to each other. The anode connection block 132c may be electrically connected to the second anode connection electrode 432c through the sixty-third via hole V63 to achieve electrical connection with the first pixel circuit 11c. The anode 131e and the anode connection block 132d may be an integrated structure connected to each other. The anode connection block 132d can be electrically connected to the second anode connection electrode 432d through the sixty-fourth via hole V64 to achieve electrical connection with the first pixel circuit 11d.

[0274] In some examples, the shape of the first anode connection bar 133 may be substantially a zigzag shape extending along the first direction X. Both ends of the first anode connection bar 133 may be connected to the anodes 131a and 131d, respectively. The first anode connection bar 133 may be located on one side of the anode 131c in the second direction Y. The first anode connection bar 133, the anodes 131a and 131d, and the anode connection block 132a may be an integrated structure connected to each other.

[0275] In some examples, the shape of the second anode connection bar 134 can be substantially a straight line extending along the first direction X. Both ends of the second anode connection bar 134 can be connected to the anodes 131c and 131f, respectively. The second anode connection bar 134 can be located between the anodes 131d and 131e. The second anode connection bar 134, the anodes 131c and 131f, and the anode connection block 132c can be an integrated structure connected to each other.

[0276] In some examples, a pixel definition film is coated on the substrate on which the aforementioned pattern is formed, and a pixel definition layer is formed through masking, exposure and development processes. Figure 6As shown, the pixel definition layer of the first display area can form a plurality of first pixel openings (for example, including first pixel openings 130a, 130b, 130c, and 130d). The shape of the plurality of first pixel openings can be substantially rectangular. The first pixel opening 130a of the first light-emitting element 13a and the first pixel opening 130d of the first light-emitting element 13d can be substantially the same in size, the first pixel opening 130c of the first light-emitting element 13c and the first pixel opening 130f of the first light-emitting element 13f can be substantially the same in size, and the first pixel opening 130b of the first light-emitting element 13b and the first pixel opening 130e of the first light-emitting element 13e can be substantially the same in size. The first pixel opening 130c of the first light-emitting element 13c can be larger than the first pixel opening 130a of the first light-emitting element 13a, and can be larger than the first pixel opening 130b of the first light-emitting element 13b.

[0277] In some examples, the light emitting region of the light emitting element may be a portion of the light emitting element located at a pixel opening of the pixel definition layer. For example, the area of ​​the light emitting region of the first light emitting element 13a may be greater than or equal to the area of ​​the light emitting region of the first light emitting element 13b, and the area of ​​the light emitting region of the first light emitting element 13c may be greater than the area of ​​the light emitting region of the first light emitting element 13a and greater than the area of ​​the light emitting region of the first light emitting element 13b.

[0278] In some examples, an organic light emitting layer is formed in the pixel opening formed above, and the organic light emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode layer, and the cathode layer can be connected to the organic light emitting layer.

[0279] Fig.21 for Figure 6 In some examples, such as Fig.21 As shown, the light-transmitting area A12 may include: a first area A121 and a second area A122. The orthographic projections of the first area A121 and the second area A122 on the substrate may not overlap. The light-transmitting area A12 may be roughly elliptical as a whole, and the shapes of the plurality of light-transmitting areas A12 are roughly the same, and are roughly wide at the top and narrow at the bottom. The first area A121 may be an irregular shape, and the second area A122 may be located at the edge of the first area A121. The cathode layer in the first area A121 may be removed, and the cathode layer in the second area A122 may be retained.

[0280] In some examples, such as Fig.21As shown, the maximum length L11 of the light-transmitting area A12 along the second direction Y can be 30 microns to 40 microns, such as about 35 microns. The maximum length L12 of the first area A121 of the light-transmitting area A12 along the first direction X can be 70 microns to 90 microns, such as about 81 microns. The minimum length L13 of the side of the lower part of the first area A121 extending along the second direction Y in the first direction X can be 65 microns to 82 microns, such as about 74 microns.

[0281] In some examples, after preparing the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode. In some examples, the encapsulation structure layer can include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer, the first encapsulation layer and the third encapsulation layer can be made of inorganic materials, the second encapsulation layer can be made of organic materials, and the second encapsulation layer can be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0282] In some examples, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The seventh insulating layer, the eighth insulating layer and the ninth insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment is not limited to this.

[0283] The structure of the display substrate of this embodiment and its preparation process are only an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, and has simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0284] In the display substrate of this example, compared with the second display area, the light-transmitting area and the display island area are formed by deleting the first pixel circuit and the first light-emitting element in the first display area, and the first pixel circuit and the first light-emitting element in the display island area are set to a combination of one-drive-one and one-drive-many, and the arrangement of the first light-emitting elements in the display island area is different from the arrangement of the second light-emitting elements in the second display area. Therefore, the display effect of the first display area can be optimized on the basis of improving the light transmittance of the first display area.

[0285] In some examples, the first scan signal in the first display area can be transmitted through the first scan line formed by the cross-layer connection of the first scan transmission segment and the first scan connection segment, and the second scan signal can be transmitted through the second scan line formed by the cross-layer connection of the second scan transmission segment and the second scan connection segment. The first scan connection segment and the second scan connection segment can be located in different film layers and overlapped in wiring, which can help save wiring space and thus help increase the area of ​​the light-transmitting area. In some examples, the first scan connection segment, the second scan connection segment, the first reset control line, and the first initial signal line can be located in different film layers and overlapped in wiring, which can help save wiring space.

[0286] In some examples, the light-emitting control signal in the first display area can be transmitted through the light-emitting control line formed by the cross-layer connection between the light-emitting control transmission segment and the light-emitting control connection segment. The light-emitting control connection segment and the first scanning connection segment and the second scanning connection segment can bypass the light-transmitting area from both sides of the light-transmitting area along the second direction, which is conducive to rational wiring. In some examples, the light-emitting control connection segment, the second reset control line, and the second initial signal line can be located in different film layers and overlapped, which can help save wiring space, thereby facilitating the increase of the area of ​​the light-transmitting area.

[0287] In some examples, the third initial signal in the first display area can be transmitted through a third initial signal line formed by cross-layer connection between the initial signal transmission segment and the initial signal connection segment. The initial signal connection segment and the light-emitting control connection segment can be located in different film layers and overlapped, which can help save wiring space.

[0288] Fig. 22 Another partial top view of the first display area of ​​at least one embodiment of the utility model. Fig. 22 , a partial top view of two rows (e.g., the kth row and the k+1th row) and two columns (e.g., the hth column and the h+1th column) of the display island area is shown, where k and h are both integers greater than 0. In some examples, such as Fig. 22As shown, the first display area may include: a plurality of display island areas and a plurality of light-transmitting areas A12. A single light-transmitting area A12 is surrounded by two display island areas in the first direction X and by two display island areas in the second direction Y. The number of film layers and the stacking order of the circuit structure layer of the display substrate of this example are similar to those of the aforementioned embodiment, and the film layer structure of the display island area of ​​the kth row and hth column and the display island area of ​​the k+1th row and h+1th column are used as examples for description.

[0289] In some examples, the value of k may be 2d, where d is an integer greater than 0. The kth row may be an odd row, and the k+1th row and the k-1th row may be even rows. In other examples, the value of k may be 2d-1, where d is an integer greater than 0. The kth row may be an even row, and the k+1th row and the k-1th row may be odd rows. In this example, an odd row refers to a row with an odd row number; an even row refers to a row with an even row number.

[0290] Fig.23 for Fig. 22 Schematic diagram of the first display area after the shielding layer is formed in FIG. Fig.23 As shown, the blocking layer of the first display area may include at least: a plurality of blocking blocks (for example, a blocking block 300a located in the display island area of ​​the kth row and the hth column and a blocking block 300b located in the display island area of ​​the k+1th row and the h+1th column). A blocking block 300a may be provided for each display island area located in the kth row, and a blocking block 300b may be provided for each display island area located in the k+1th row. The blocking block 300a and the connected blocking block 300b may be centrally symmetrical about the connection point between the two. The blocking blocks 300a and 300b of the display island areas of adjacent rows in the display island areas of adjacent columns may be interconnected integral structures. The plurality of blocking blocks 300a and 300b of the first display area may be interconnected integral structures. The shapes of the blocking blocks may refer to the description of the aforementioned embodiments, so they will not be described in detail here.

[0291] Fig.24A for Fig. 22 Schematic diagram of the first display area after the first semiconductor layer is formed. Fig. 24B for Fig.24A Schematic diagram of the first semiconductor layer in FIG. Fig.24A and Fig. 24B As shown, the first semiconductor layer of the first display area may include at least: an active layer of a plurality of first type transistors of a plurality of first pixel circuits. The first semiconductor layer pattern of the four first pixel circuits located in the display island area of ​​the kth row and the hth column and the first semiconductor layer pattern of the four first pixel circuits located in the display island area of ​​the k+1th row and the h+1th column may be centrally symmetrical about the connection point between the two. The description of the first semiconductor layer pattern in each display island area can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0292] Fig.25A for Fig. 22 Schematic diagram of the first display area after the first conductive layer is formed. Fig.25B for Fig.25A Schematic diagram of the first conductive layer in FIG. Fig.25A and Fig.25B As shown, the first conductive layer of the first display area may include at least: a plurality of first scan lines (for example, including first scan lines GL1(k-1), GL1(k), GL1(k+1), GL1(k+2)), a plurality of light-emitting control lines (for example, including light-emitting control lines EML(k), EML(k+1)), a plurality of first reset control lines (for example, including first reset control lines RST1(k), RST1(k+2)), a plurality of second reset control lines (for example, including second reset control lines RST2(k), RST2(k+2)), and first electrodes of storage capacitors of a plurality of first pixel circuits (for example, including first electrodes 391a, 391b).

[0293] In some examples, the first scan line GL1(k), the first reset control line RST1(k), and the first scan line GL1(k-1) may be sequentially arranged along the second direction Y, and located on one side of the first electrode of the storage capacitor of the first pixel circuit in the display island region of the kth row in the second direction Y. The light emitting control line EML(k), the second reset control line RST2(k), and the light emitting control line EML(k+1) may be sequentially arranged along the second direction Y, and located on one side of the first electrode of the storage capacitor of the first pixel circuit in the display island region of the kth row in the opposite direction of the second direction Y, and located on one side of the first electrode of the storage capacitor of the first pixel circuit in the display island region of the k+1th row in the second direction Y.

[0294] In some examples, the first scan line GL1(k) may be located on one side of the k-th row of light-transmitting area A12 in the second direction Y, and the light emission control line EML(k) may be located on one side of the k-th row of light-transmitting area A12 in the opposite direction of the second direction Y. The first scan line GL1(k) and the light emission control line EML(k) may bypass the light-transmitting area A12 from opposite sides of the k-th row of light-transmitting area A12 in the second direction Y.

[0295] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) and the first pixel circuit in the k-1-th row display island area (e.g., the first pixel circuit in the i-1-th row) can share the first reset control line RST1(k). The first pixel circuit in the k+1-th row display island area (e.g., the first pixel circuit in the i+1-th row) and the first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) can share the second reset control line RST2(k). In this example, by flipping the first pixel circuit in the even-numbered row display island area upside down, the first pixel circuit in the even-numbered row display island area can share the first reset control line or the second reset control line with the first pixel circuit in the adjacent odd-numbered row display island area to save wiring arrangement space.

[0296] Fig.26A for Fig. 22 Schematic diagram of the first display area after the second conductive layer is formed. Fig.26B for Fig.26A Schematic diagram of the second conductive layer in FIG. Fig.26A and Fig.26B As shown, the second conductive layer of the first display area may include at least: a second scanning auxiliary transmission segment 271 of a plurality of second scanning auxiliary lines, and a second electrode of the storage capacitor of a plurality of first pixel circuits (for example, including second electrodes 392a, 392b). The second electrodes of the storage capacitors of the four first pixel circuits in a single display island may be an integrated structure connected to each other. In the display island in the kth row and the hth column, the second scanning auxiliary transmission segment 271 may be located on one side of the second electrode of the storage capacitor of the first pixel circuit in the second direction Y; in the display island in the k+1th row and the h+1th column, the second scanning auxiliary transmission segment 271 may be located on one side of the second electrode of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y.

[0297] Fig.27A for Fig. 22 Schematic diagram of the first display area after the second semiconductor layer is formed. Fig.27B for Fig.27A Schematic diagram of the second semiconductor layer in FIG. Fig.27A and Fig.27B As shown, the second semiconductor layer of the first display area may include at least: an active layer of a second type transistor of a plurality of first pixel circuits. The second semiconductor layer pattern in the display island area of ​​the kth row and the hth column and the second semiconductor layer pattern in the display island area of ​​the k+1th row and the h+1th column may be centrally symmetrical about the connection point of the two display island areas.

[0298] Fig.28A for Fig. 22 Schematic diagram of the first display area after the third conductive layer is formed. Fig.28B for Fig.28A Schematic diagram of the third conductive layer in FIG. In some examples, such as Fig.28A and Fig.28B As shown, the third conductive layer of the first display area may include at least: a second scanning transmission segment 281 of multiple second scanning lines (for example, including second scanning lines GL2(k), GL2(k+1)), multiple first initial signal lines (for example, including first initial signal lines INIT1(k), INIT1(k+1)), multiple second initial signal lines (for example, including second initial signal lines INIT2(k)), and multiple third initial signal lines (for example, including third initial signal lines INIT3(k), INIT3(k+1)).

[0299] In some examples, the first pixel circuits in each display island area are arranged in the same row. The first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) and the first pixel circuit in the k-1-th row display island area (e.g., the first pixel circuit in the i-1-th row) can share the first initial signal line INIT1(k). The first pixel circuit in the k+1-th row display island area (e.g., the first pixel circuit in the i+1-th row) and the first pixel circuit in the k-th row display island area (e.g., the first pixel circuit in the i-th row) can share the second initial signal line INIT2(k). The first pixel circuit in the k+1-th row display island area (e.g., the first pixel circuit in the i+1-th row) and the first pixel circuit in the k+2-th row display island area (e.g., the first pixel circuit in the i+2-th row) can share the first initial signal line INIT1(k+1). In this example, the first pixel circuit in the even-numbered row display island area is flipped upside down so that the first pixel circuit in the even-numbered row display island area can share the first initial signal line or the second initial signal line with the first pixel circuit in the adjacent odd-numbered row display island area to save wiring layout space.

[0300] Fig.29A for Fig. 22 Schematic diagram of the first display area after the fourth conductive layer is formed. Fig.29B for Fig.29A Schematic diagram of the fourth conductive layer in FIG. In some examples, such as Fig.29A and Fig.29BAs shown, the fourth conductive layer of the first display area may include at least: a plurality of pixel connection electrodes (for example, including the first pixel connection electrode 401 to the seventeenth pixel connection electrode 417), and a plurality of routing switching electrodes (for example, including the first routing switching electrode 283). The shape of the first routing switching electrode 283 may be roughly L-shaped. The first routing switching electrode 283 may be connected to the second scanning auxiliary transmission segment 271 of the second scanning auxiliary line GL2b(k) and the second scanning transmission segment 281 of the second scanning line GL2(k). The fourth conductive layer pattern in the display island area of ​​the kth row and the hth column and the fourth conductive layer pattern in the display island area of ​​the k+1th row and the h+1th column may be centrally symmetrical about the connection point of the two display island areas.

[0301] Fig. 30A for Fig. 22 Schematic diagram of the first display area after the fifth conductive layer is formed. Fig. 30B for Fig. 30A Schematic diagram of the fifth conductive layer in FIG. Fig. 30A and Fig. 30B As shown, the fifth conductive layer of the first display area may include at least: a plurality of data lines (for example, data lines DL(j-1), DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7), DL(j+8)), a plurality of first anode connection electrodes (for example, first anode connection electrodes 422a, 422b, 422c, 422d, 422e, 422f, 422g, and 422h), a plurality of first power connection electrodes (for example, first power connection electrodes 423a, 423b, and 423c), a plurality of first shielding electrodes (for example, first shielding electrodes 421a and 421b), and a plurality of second scan connection segments 282 of second scan lines. The fifth conductive layer pattern in the display island area of ​​the kth row and the hth column and the fifth conductive layer pattern in the display island area of ​​the k+1th row and the h+1th column may be centrally symmetrical about the connection point of the two display island areas. The first anode connecting electrode 422e is connected to the first first pixel circuit in the display island area of ​​the k+1th row and the h+1th column, the first anode connecting electrode 422f is connected to the second first pixel circuit in the display island area of ​​the k+1th row and the h+1th column, the first anode connecting electrode 422g is connected to the third first pixel circuit in the display island area of ​​the k+1th row and the h+1th column, and the first anode connecting electrode 422h is connected to the fourth first pixel circuit in the display island area of ​​the k+1th row and the h+1th column.

[0302] Fig.31A for Fig. 22 Schematic diagram of the first display area after the sixth conductive layer is formed. Fig.31B for Fig.31A Schematic diagram of the sixth conductive layer in FIG. In some examples, such as Fig.31A and Fig.31B As shown, the sixth conductive layer of the first display area may include at least: a plurality of second anode connection electrodes (for example, including second anode connection electrodes 432a, 432b, 432c, 432d, 432e, 432f, 432g and 432h), a plurality of first voltage transmission lines (for example, including first voltage transmission lines 451a and 451b), a plurality of power connection bars 452, and a plurality of second power connection electrodes (for example, including second power connection electrodes 453a, 453b and 453c). The second anode connection electrodes 432e, 432f, 432g and 432h may be substantially in the shape of bars extending along the second direction Y. The second anode connection electrode 432e may be connected to the first anode connection electrode 422e, the second anode connection electrode 432f may be connected to the first anode connection electrode 422f, the second anode connection electrode 432g may be connected to the first anode connection electrode 422g, and the second anode connection electrode 432h may be connected to the first anode connection electrode 422h.

[0303] Fig.32 for Fig. 22 Schematic diagram of the first display area after the anode layer is formed in FIG. Fig.32 As shown, the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, anode 131f of first light-emitting element 13f), a plurality of anode connection blocks (e.g., anode connection blocks 132a, 132b, 132c, and 132d), and a plurality of anode connection bars (e.g., first anode connection bar 133 and second anode connection bar 134). The anode layer pattern in the display island area of ​​the kth row and the hth column is substantially the same as the anode layer pattern in the display island area of ​​the k+1th row and the h+1th column. The anodes of the two first light-emitting elements emitting the first color light in the display island area of ​​the k+1th row can be connected to the first first pixel circuit through the second anode connection electrode 432e and the first anode connection electrode 422e, the anode of one first light-emitting element emitting the second color light can be connected to the second first pixel circuit through the second anode connection electrode 432f and the first anode connection electrode 422f, the anodes of the two first light-emitting elements emitting the third color light can be connected to the third first pixel circuit through the second anode connection electrode 432g and the first anode connection electrode 422g, and the anode of another first light-emitting element emitting the second color light can be connected to the fourth first pixel circuit through the second anode connection electrode 432h and the first anode connection electrode 422h. The patterning of the anode layer of this example is similar to the anode layer pattern of the aforementioned embodiment, so it is not repeated here.

[0304] Fig.33 for Fig. 22 Schematic diagram of the light-transmitting area in . In some examples, the light-transmitting area A12 of the kth row and the h+1th column and the light-transmitting area A12 of the k+1th row and the hth column may be centrally symmetric about the connection point of the display island area of ​​the kth row and the h+1th column and the display island area of ​​the k+1th row and the h+1th column. The light-transmitting area A12 as a whole may be roughly elliptical, for example, the light-transmitting area A12 of the k+1th row and the hth column may be narrow at the top and wide at the bottom. The light-transmitting area A12 may include: a first area A121 and a second area A122. The orthographic projections of the first area A121 and the second area A122 on the substrate may not overlap. The first area A121 may be an irregular shape, and the second area A122 may be located at the edge of the first area A121. The cathode layer in the first area A121 may be removed, and the cathode layer in the second area A122 may be retained.

[0305] In some examples, such as Fig.33 As shown, the maximum length L21 of the light-transmitting area A12 along the second direction Y may be 34 to 42 microns, such as about 38 microns. The maximum length L22 of the first area A121 of the light-transmitting area A12 along the first direction X may be 75 to 95 microns, such as about 85 microns; the minimum length L23 of the side of the first area A121 extending along the second direction Y in the first direction X may be 65 to 81 microns, such as about 73 microns.

[0306] Compared with the above-mentioned embodiment, the display substrate of this example flips the first pixel circuits in the display island area of ​​the even rows (or odd rows) upside down, so that the first pixel circuits in adjacent rows and columns can be centrally symmetrical, and the first pixel circuits in adjacent rows can share the first reset control line and the first initial signal line, or can share the second reset control line and the second initial signal line, which is beneficial to saving the wiring space in the display island area, and is beneficial to increasing the area of ​​the light-transmitting area, thereby improving the light transmittance of the first display area. The rest of the description of the display substrate of this embodiment can refer to the description of the above-mentioned embodiment, so it will not be repeated here.

[0307] Fig.34 Another schematic diagram of the signal correspondence between the first display area and the second display area in at least one embodiment of the present invention. Figure 5 In the figure, a first display unit in the display island area of ​​the fth row and the hth column and a first display unit in the display island area of ​​the f-1th row and the h+1th column of the first display area A1 are taken as examples for illustration, where f is an integer.

[0308] In some examples, such as Fig.34As shown, the four first pixel circuits 11a, 11b, 11c and 11d in the display island area in the fth row and the hth column can be arranged in sequence along the first direction X. The first pixel circuit 11a can be connected to two first light-emitting elements 13a and 13d that emit the first color light, the first pixel circuit 11b can be connected to one first light-emitting element 13b that emits the second color light, the first pixel circuit 11c can be connected to two first light-emitting elements 13c and 13f that emit the third color light, and the first pixel circuit 11d can be connected to another first light-emitting element 13e that emits the second color light.

[0309] In some examples, such as Fig.34 As shown, the four first pixel circuits 11a, 11b, 11c and 11d in the display island area of ​​the fth row and the h+1th column can be arranged in sequence along the first direction X. The first pixel circuit 11a can be connected to two first light-emitting elements 13c and 13f that emit the third color light, the first pixel circuit 11b can be connected to one first light-emitting element 13b that emits the second color light, the first pixel circuit 11c can be connected to two first light-emitting elements 13a and 13d that emit the first color light, and the first pixel circuit 11d can be connected to another first light-emitting element 13e that emits the second color light.

[0310] In this example, the connection order between the first pixel circuits and the first light-emitting elements in the display islands of two adjacent rows is different. For example, the first first pixel circuit in the display island of row f is connected to two first light-emitting elements emitting the first color light, the third first pixel circuit is connected to two first light-emitting elements emitting the third color light, and the four first pixel circuits correspond to RGBG in sequence; the first first pixel circuit in the display island of row f-1 is connected to two first light-emitting elements emitting the third color light, the third first pixel circuit is connected to two first light-emitting elements emitting the first color light, and the four first pixel circuits correspond to BGRG in sequence.

[0311] In this example, by setting the connection sequence of the first pixel circuit and the first light-emitting element in the adjacent rows of display island regions to be different, it is beneficial to improve the display uniformity of the first display region and enhance the display effect of the first display region. The rest of the description of the display substrate of this example can refer to the description of the above embodiment, so it will not be repeated here.

[0312] Fig.35 Another partial schematic diagram of the display area of ​​at least one embodiment of the present invention. Fig.35 FIG. 4 illustrates an arrangement of a plurality of first light emitting elements in the first display area A1 and a plurality of second light emitting elements in the second display area A2. Fig.35 In the figure, the eight rows and four columns of the display islands in the first display area A1 are taken as an example for illustration. This example does not limit the number of the display islands in the first display area.

[0313] In some examples, such as Fig.35 As shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The display island area A11 may include a first display unit 21, and the first display unit 21 may include: six first light-emitting elements and four first pixel circuits. The six first light-emitting elements may include: two first light-emitting elements 13a and 13d emitting first color light, two first light-emitting elements 13b and 13e emitting second color light, and two first light-emitting elements 13c and 13f emitting third color light. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light.

[0314] In some examples, the six first light-emitting elements of the first display unit 21 can be divided into two groups of first light-emitting elements, and each group of first light-emitting elements can include three first light-emitting elements that emit light of different colors. For example, the first group of first light-emitting elements can include: three first light-emitting elements 13a, 13b and 13c; the second group of first light-emitting elements can include: three first light-emitting elements 13d, 13e and 13f. The first group of first light-emitting elements and the second group of first light-emitting elements can be arranged in sequence along the first direction X. In the first group of first light-emitting elements, the first light-emitting elements 13a, 13b and 13c can be arranged in sequence along the first direction X. In the second group of first light-emitting elements, the first light-emitting elements 13d, 13e and 13f can be arranged in sequence along the first direction X. In this example, the three first light-emitting elements that emit light of different colors in each group of first light-emitting elements of the first display unit 21 can adopt the arrangement mode of Real RGB. The arrangement mode of the plurality of second light-emitting elements of the second display area A2 can refer to the description of the aforementioned embodiment, so it is not repeated here.

[0315] Fig.36 It is a partial top view schematic diagram of the first display area of ​​at least one embodiment of the utility model. Fig.37A for Fig.36 Schematic diagram of the first display area after the anode layer is formed. Fig.37B for Fig.37A Schematic diagram of the anode layer in . Fig.36 FIG. 1 shows a partial top view of two rows (e.g., the kth row and the k+1th row) and two columns (e.g., the hth column and the h+1th column) of the display island area. The circuit structure layer of the first display area of ​​this example can be as follows: Fig. 22 In other examples, the circuit structure layer of the first display area of ​​this example can be as follows: Figure 6 The structure of the embodiment shown is not limited to this in this embodiment.

[0316] In some examples, such as Figures 36 to 37BAs shown, the anode layer of the first display area may include at least: anodes of multiple first light-emitting elements (for example, including anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, anode 131d of first light-emitting element 13d, anode 131e of first light-emitting element 13e, and anode 131f of first light-emitting element 13f), multiple anode connection blocks (for example, including anode connection blocks 132a, 132b, 132c and 132d), and multiple anode connection strips (for example, including first anode connection strip 133 and second anode connection strip 134).

[0317] In some examples, the shape of the anodes 131a, 131b, 131c, 131d, 131e, and 131f may be substantially rectangular. The anodes 131a, 131b, 131c, 131d, 131e, and 131f may be arranged in sequence along the first direction X.

[0318] In some examples, the shape of the anode connection block 132a may be roughly hexagonal. The anode 131a and the anode connection block 132a may be an integrated structure connected to each other. The anode connection block 132a may be connected to the first first pixel circuit. The shape of the anode connection block 132b may be roughly oblique. The anode 131b and the anode connection block 132b may be an integrated structure connected to each other. The anode connection block 132b may be connected to the second first pixel circuit. The shape of the anode connection block 132c may be roughly V-shaped. The anode 131c and the anode connection block 132c may be an integrated structure connected to each other. The anode connection block 132c may be connected to the third first pixel circuit. The shape of the anode connection block 132d may be roughly oblique. The anode 131e and the anode connection block 132d may be an integrated structure connected to each other. The anode connection block 132d may be connected to the fourth first pixel circuit.

[0319] In some examples, the shape of the first anode connection bar 133 may be approximately a folded line extending along the first direction X. Both ends of the first anode connection bar 133 may be connected to the anodes 131a and 131d, respectively. The first anode connection bar 133 may be located on one side of the anodes 131b and 131c in the second direction Y. The first anode connection bar 133, the anodes 131a and 131d, and the anode connection block 132a may be an integrated structure connected to each other.

[0320] In some examples, the second anode connection bar 134 may be shaped substantially like a folded line extending along the first direction X. Both ends of the second anode connection bar 134 may be connected to the anode 131f and the anode connection block 132c, respectively. The second anode connection bar 134 may be located on one side of the anodes 131d and 131e in the opposite direction of the second direction Y. The second anode connection bar 134, the anodes 131c and 131f, and the anode connection block 132c may be an integrated structure connected to each other.

[0321] In the display substrate of this example, by setting the first light-emitting element in the display island area to adopt a Real RGB arrangement, the display effect of the first display area can be optimized.

[0322] Fig.38 Another partial schematic diagram of the display area of ​​at least one embodiment of the present invention. Fig.38 FIG. 4 illustrates an arrangement of a plurality of first light emitting elements in the first display area A1 and a plurality of second light emitting elements in the second display area A2. Fig.38 In the figure, the four-row and four-column display islands of the first display area A1 are used as an example for illustration. This example does not limit the number of display islands in the first display area.

[0323] In some examples, such as Fig.38 As shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the second direction Y. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area of ​​this example may be roughly square island-shaped. The arrangement of the first light-emitting element and the first pixel circuit in each first display unit may refer to the description of the aforementioned embodiment, so it will not be repeated here. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the second direction Y.

[0324] Fig.39 Another partial schematic diagram of the display area of ​​at least one embodiment of the present invention. Fig.39 FIG. 4 illustrates an arrangement of a plurality of first light emitting elements in the first display area A1 and a plurality of second light emitting elements in the second display area A2. Fig.39 In the figure, the four-row and four-column display islands of the first display area A1 are used as an example for illustration. This example does not limit the number of display islands in the first display area.

[0325] In some examples, such as Fig.39As shown, the first display area A1 may include: a plurality of display island areas A11 and a plurality of light-transmitting areas A12 arranged in an array. The plurality of display island areas A11 and the plurality of light-transmitting areas A12 may be arranged at intervals along the first direction X and the second direction Y. The display island area A11 may include two first display units 21a and 21b. The two first display units 21a and 21b may be arranged in sequence along the first direction X. Each first display unit may include six first light-emitting elements and four first pixel circuits. The display island area of ​​this example may be roughly in the shape of a rectangular island. The arrangement of the first light-emitting element and the first pixel circuit in each first display unit may refer to the description of the aforementioned embodiment, so it will not be repeated here. In other examples, each display island area may be provided with three or more first display units arranged in sequence along the first direction X.

[0326] In other examples, at least one first pixel circuit in at least one first display unit can be connected to three or four first light-emitting elements to drive the three or four first light-emitting elements to emit light. In other examples, two groups of first light-emitting elements in at least one first display unit can adopt different arrangements, for example, one group of first light-emitting elements adopts a Pentile RGB arrangement, and the other group of first light-emitting elements adopts a Real RGB arrangement. In other examples, the first light-emitting elements in at least one first display unit can adopt a Pentile RGB arrangement, and the first light-emitting elements in at least one first display unit can adopt a Real RGB arrangement. This embodiment is not limited to this.

[0327] The present embodiment provides a display substrate, comprising: a substrate. The substrate comprises: a first display area and a second display area located at least on one side of the first display area. The first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array. The display island area comprises: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits comprises M first pixel circuits, at least one first pixel circuit of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1. The second display area comprises: a plurality of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits comprises M second pixel circuits, at least one second pixel circuit is connected to at least one second light-emitting element. The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area. The first pixel circuit and the second pixel circuit located in the same column are connected to the same data line.

[0328] The display substrate provided in this embodiment adopts a pixel circuit built-in method to delete the first pixel circuit and the first light-emitting element in the first display area to form a light-transmitting area, and sets the driving relationship of the first pixel circuit to the first light-emitting element to be different from the driving relationship of the second pixel circuit to the second light-emitting element. On the basis of improving the light transmittance of the first display area, the display effect of the first display area can be guaranteed, and the loss of display effect caused by deleting some light-emitting elements and pixel circuits in the first display area can be compensated.

[0329] In some exemplary embodiments, each group of first pixel circuits includes four first pixel circuits, the four first pixel circuits are connected to six first light-emitting elements, the six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light. Each group of second pixel circuits includes four second pixel circuits, the four second pixel circuits are connected to four second light-emitting elements, the four second light-emitting elements include one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

[0330] In some exemplary embodiments, an arrangement of the six first light emitting elements is different from an arrangement of the four second light emitting elements.

[0331] In some exemplary embodiments, the arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction, such as 0.45 to 0.55, and for example, may be approximately 0.5; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second direction in the second display area, such as 0.45 to 0.55, and for example, may be approximately 0.5.

[0332] The relevant descriptions about the display substrate of this embodiment can refer to the descriptions of the aforementioned embodiments, so they will not be repeated here.

[0333] Fig.40 FIG. 1 is a schematic diagram of a display device according to at least one embodiment of the present invention. Fig.40 As shown, this embodiment provides a display device, including: a display substrate 91 and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 can be located on the non-display surface side of the display substrate 91. The orthographic projection of the sensor 92 on the display substrate 91 can at least partially overlap with the first display area A1. For example, the orthographic projection of the sensor 92 on the display substrate 91 can be located within the range of the first display area A1.

[0334] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA, Personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large area of ​​wall, an information query device (such as business query equipment for e-government, banks, hospitals, power and other departments), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0335] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0336] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; The display island area includes: at least one first display unit; the at least one first display unit includes: N first light-emitting elements and M first pixel circuits, where M and N are both integers greater than 1, and M is less than N; at least one first pixel circuit among the M first pixel circuits is connected to at least two first light-emitting elements and is configured to drive the at least two first light-emitting elements to emit light; The second display area comprises: a plurality of second display units arranged in an array; at least one second display unit among the plurality of second display units comprises: M second light-emitting elements and M second pixel circuits, and the M second pixel circuits are connected to the M second light-emitting elements in a one-to-one correspondence; The arrangement of the N first light-emitting elements of the at least one first display unit is different from the arrangement of the M second light-emitting elements of the at least one second display unit.

2. The display substrate according to claim 1, characterized in that: In the first display area, the display island areas and the light-transmitting areas are alternately arranged and aligned in a first direction, and are alternately arranged and aligned in a second direction, wherein the first direction intersects the second direction.

3. The display substrate according to claim 1, characterized in that: The M first pixel circuits of the at least one first display unit and the M second pixel circuits of the at least one second display unit are aligned in a first direction or a second direction, wherein the first direction intersects the second direction.

4. The display substrate according to claim 1, characterized in that: The at least one first display unit comprises: six first light emitting elements and four first pixel circuits, wherein the four first pixel circuits are arranged in sequence along a first direction; The six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light; The two first light-emitting elements emitting the first color light are connected to the same first pixel circuit, the two first light-emitting elements emitting the third color light are connected to the same first pixel circuit, and the two first light-emitting elements emitting the second color light are connected to two first pixel circuits in a one-to-one correspondence.

5. The display substrate according to claim 4, characterized in that: The six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; In each group of first light-emitting elements, the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light are arranged in sequence along the second direction, and the first light-emitting elements emitting the third color light are located on the same side of the first light-emitting elements emitting the first color light and the first light-emitting elements emitting the second color light along the first direction; the second direction intersects with the first direction.

6. The display substrate according to claim 4, characterized in that: The six first light-emitting elements are divided into two groups of first light-emitting elements, and the two groups of first light-emitting elements are arranged in sequence along the first direction, and each group of first light-emitting elements includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and a first light-emitting element emitting a third color light; In each group of first light-emitting elements, the first light-emitting elements emitting first color light, the first light-emitting elements emitting second color light, and the first light-emitting elements emitting third color light are arranged in sequence along the first direction.

7. The display substrate according to claim 4, characterized in that: In the first display area, the connection order of the first pixel circuits and the first light-emitting elements of the first display units in the display island areas of adjacent rows is different.

8. The display substrate according to claim 7, characterized in that: In the first display area, four first pixel circuits located in the display island area of ​​the fth row may be connected in sequence to two first light-emitting elements emitting first color light, one first light-emitting element emitting second color light, two first light-emitting elements emitting third color light, and another first light-emitting element emitting second color light; The four first pixel circuits of the first display unit located in the display island area of ​​the f-1th row can be connected in sequence to two first light-emitting elements emitting the third color light, one first light-emitting element emitting the second color light, two first light-emitting elements emitting the first color light, and another first light-emitting element emitting the second color light; wherein f is an integer greater than 1.

9. The display substrate according to claim 4, characterized in that: The at least one second display unit comprises: four second light emitting elements and four second pixel circuits; the four second pixel circuits are arranged in sequence along the first direction; The four second light-emitting elements include: a second light-emitting element emitting a first color light, two second light-emitting elements emitting a second color light, and a second light-emitting element emitting a third color light; the second light-emitting element emitting the first color light, the second light-emitting element emitting the second color light, the second light-emitting element emitting the third color light, and the second light-emitting element emitting the second color light are arranged in sequence along the first direction; the second light-emitting element emitting the first color light and the second light-emitting element emitting the third color light are arranged in the same row, and the two second light-emitting elements emitting the second color light are arranged in the same row.

10. The display substrate according to any one of claims 4 to 9, characterized in that: The first color light is red light, the second color light is green light, and the third color light is blue light.

11. The display substrate according to claim 1, characterized in that: The M first pixel circuits of the first display unit in the display island area are connected to a first scan transmission segment and a second scan transmission segment extending along the first direction; the first scan transmission segment is configured to transmit a first scan signal, and the second scan transmission segment is configured to transmit a second scan signal; The first scan transmission segments in the display island regions that are located in the same row and adjacent to each other are connected via the first scan connection segment; the second scan transmission segments in the display island regions that are located in the same row and adjacent to each other are connected via the second scan connection segment; The second scanning connection segment is located at a side of the first scanning connection segment away from the substrate, and an orthographic projection of the first scanning connection segment on the substrate at least partially overlaps with an orthographic projection of the second scanning connection segment on the substrate.

12. The display substrate according to claim 11, characterized in that: The first pixel circuit of the first display unit located in the display island area of ​​the same row is also connected to a first reset control line and a first initial signal line extending along the first direction, the first initial signal line is located on a side of the first reset control line away from the substrate; the first scan connection section is located on a side of the first initial signal line away from the substrate; The orthographic projection of the first scanning connection segment on the substrate at least partially overlaps with the orthographic projection of the first initial signal line on the substrate; An orthographic projection of the first initial signal line on the substrate at least partially overlaps with an orthographic projection of the first reset control line on the substrate.

13. The display substrate according to claim 11, characterized in that: The M first pixel circuits of the first display unit in the display island area are connected to the light emitting control transmission segment extending along the first direction; the light emitting control transmission segment is configured to transmit a light emitting control signal; the light emitting control transmission segments in the display island areas adjacent to each other in the same row are connected via a light emitting control connection segment; The light-emitting control connection segment and the first scanning connection segment are located on both sides of the light-transmitting area between the adjacent display island areas in a second direction, and the second direction intersects the first direction.

14. The display substrate according to claim 13, characterized in that: The first pixel circuit of the first display unit located in the display island area of ​​the same row is also connected to a second reset control line and a second initial signal line extending along the first direction, the second initial signal line is located on a side of the second reset control line away from the substrate; the light emitting control connection section is located on a side of the second initial signal line away from the substrate; The orthographic projection of the light-emitting control connection section on the substrate at least partially overlaps with the orthographic projection of the second initial signal line on the substrate; the orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the second reset control line on the substrate.

15. The display substrate according to claim 13, characterized in that: The M first pixel circuits of the first display unit in the display island area are also connected to an initial signal transmission segment extending along the first direction; the initial signal transmission segment is configured to transmit a third initial signal; The initial signal transmission segments in adjacent display islands located in the same row are connected via the initial signal connection segments; The light-emitting control connection section is located at a side of the initial signal connection section away from the substrate; the orthographic projection of the initial signal connection section on the substrate partially overlaps with the orthographic projection of the light-emitting control connection section on the substrate.

16. The display substrate according to claim 1, characterized in that: The multiple first pixel circuits located in the display island area of ​​the kth row and the hth column and the multiple first pixel circuits located in the display island area of ​​the k+1th row and the h+1th column are centrally symmetric about the connection point between the display island area of ​​the kth row and the hth column and the display island area of ​​the k+1th row and the h+1th column; wherein k and h are both integers greater than 0.

17. The display substrate according to claim 16, characterized in that: In the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1th row located in the k-1-th row display island area share a first reset control line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1th row located in the k+1-th row display island area share a second reset control line, wherein i is an integer greater than 1, and e is an integer greater than or equal to 0.

18. The display substrate according to claim 17, characterized in that: In the first display area, the first pixel circuit of the i-th row located in the k-th row display island area and the first pixel circuit of the i-1-th row located in the k-1-th row display island area share a first initial signal line, and the first pixel circuit of the i+e-th row located in the k-th row display island area and the first pixel circuit of the i+e+1-th row located in the k+1-th row display island area share a second initial signal line.

19. The display substrate according to claim 1, characterized in that: The display island area includes two first display units, and the two first display units are arranged along a first direction or along a second direction; the first direction intersects with the second direction.

20. A display device, characterized in that: The device comprises a display substrate as claimed in any one of claims 1 to 19, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

21. A display substrate, characterized in that: include: A substrate, comprising: a first display area and a second display area located at at least one side of the first display area; the first display area comprises: a plurality of display island areas and a plurality of light-transmitting areas arranged in an array; The display island area includes: at least one group of first pixel circuits and a plurality of first light-emitting elements, each group of first pixel circuits includes M first pixel circuits, at least one first pixel circuit of the M first pixel circuits is connected to at least two first light-emitting elements; M is an integer greater than 1; The second display area includes: a plurality of groups of second pixel circuits and a plurality of second light-emitting elements, each group of second pixel circuits includes M second pixel circuits, and at least one second pixel circuit is connected to at least one second light-emitting element; The number of first light-emitting elements connected to each group of first pixel circuits is greater than the number of second light-emitting elements connected to each group of second pixel circuits; the arrangement density of the second pixel circuits in the second display area is greater than or equal to the arrangement density of the first pixel circuits in the first display area; The first pixel circuit and the second pixel circuit located in the same column are connected to the same data line.

22. The display substrate according to claim 21, characterized in that: Each group of first pixel circuits includes four first pixel circuits, and the four first pixel circuits are connected to six first light-emitting elements, and the six first light-emitting elements include: two first light-emitting elements emitting first color light, two first light-emitting elements emitting second color light, and two first light-emitting elements emitting third color light; Each group of second pixel circuits includes four second pixel circuits, which are connected to four second light-emitting elements. The four second light-emitting elements include one second light-emitting element emitting first color light, two second light-emitting elements emitting second color light, and one second light-emitting element emitting third color light.

23. The display substrate according to claim 22, characterized in that: The arrangement of the six first light-emitting elements is different from the arrangement of the four second light-emitting elements.

24. The display substrate according to claim 21, characterized in that: The arrangement density of the first pixel circuits in the first display area in the first direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the first direction; the arrangement density of the first pixel circuits in the first display area in the second direction is 0.4 to 0.6 of the arrangement density of the second pixel circuits in the second display area in the second direction; the first direction intersects the second direction.

Images