Integrated circuit assembly

Abstract

The utility model discloses an integrated circuit assembly, which comprises a first substrate provided with a substrate bonding pad on the surface, a semiconductor substrate arranged on the first substrate, a connecting piece connected with the substrate bonding pad of the first substrate and the bottom surface of the semiconductor substrate, and a chip arranged on the semiconductor substrate, the semiconductor substrate comprises an insulating layer arranged at the lower part of the chip and a supporting substrate positioned at the lower part of the insulating layer; the supporting substrate comprises a plurality of honeycomb structures, and a conical gap is formed between every two adjacent honeycomb structures so as to form a conical through hole. According to the scheme, the supporting substrate comprises the multiple honeycomb structures, the conical gaps are formed between every two adjacent honeycomb structures, the conical gaps are filled with the heat dissipation materials, meanwhile, the hole diameters of the conical gaps are limited, on one hand, the original ultra-thin technology is guaranteed, and on the other hand, the heat dissipation performance is improved; in addition, the toughness and firmness of the supporting substrate are greatly improved due to the arrangement of the conical gap, and the productivity is further improved.

Description

Technical Field

[0001] The utility model relates to a microelectronic packaging technology, in particular to an integrated circuit component with high-efficiency heat dissipation. Background Art

[0002] With the development of high-speed, high-density, and high-performance microelectronic chips, heat management has become a critical issue in microsystem packaging. In large-scale integrated circuit chips manufactured on semiconductor wafers, electronic signals are carried by electric current through conductors and transistors. The energy carried by the current in the integrated circuit chip is partially dissipated as heat along the path of the current through the integrated circuit. The heat P generated in the integrated circuit is the sum of the dynamic power PD and the static power PS:

[0003] P=P D +P S =ACV2f+VI leak ;

[0004] Where A is the gate activity factor, C is the total capacitive load of all gates, V2 is the peak-to-peak supply voltage swing, f is the frequency, and I leak Is the leakage current. Static power term PS = VI leak is due to the leakage current I leak The static power dissipated. The dynamic power term PD = ACV2f is the dynamic power dissipated from the charging and dissipation of the capacitive load of the integrated circuit.

[0005] Another characteristic of integrated circuit chips is uneven temperature distribution across the chip. As more and more functional blocks are integrated into a single chip in a system-on-chip (SOC) design, the higher power density of these blocks creates uneven temperature distribution and leads to "hot spots" or "hot spots" on the IC chip. These hot spots can cause temperature differences across the chip ranging from approximately 5°C to approximately 30°C.

[0006] To this end, the applicant previously applied for an invention patent with publication number CN108321131A, which discloses an integrated circuit with a high-efficiency heat dissipation structure, comprising: a first substrate having a substrate pad on its surface, a semiconductor substrate disposed on the first substrate, a connector connecting the substrate pad of the first substrate and the bottom surface of the semiconductor substrate, and a chip disposed on the semiconductor substrate, wherein the semiconductor substrate comprises an insulating layer disposed below the chip and a supporting substrate disposed below the insulating layer; the supporting substrate is provided with a plurality of through-holes arranged in an array, each through-hole being staggered and interconnected, so that the supporting substrate forms a honeycomb structure. This application innovatively makes the supporting substrate of the semiconductor substrate into a honeycomb structure, in which the through-holes on the honeycomb structure are interconnected, and can quickly transfer the heat generated by the chip located on the upper portion of the semiconductor substrate to the edge, thereby achieving an excellent heat dissipation effect. In actual applications, when using integrated circuits with this efficient heat dissipation structure to package electronic devices, multiple chips placed on a semiconductor substrate need to be bonded or flip-chip soldered to the first substrate at the bottom, and sometimes multiple chips need to be connected to each other. However, since the chips are relatively thin (generally 30 microns to 90 microns) and prone to warping, in actual applications, the connections between the chips and the first substrate cannot be guaranteed to be firm, which may lead to significant losses in production. Utility Model Content

[0007] Therefore, in response to the above-mentioned problems, the present invention proposes an integrated circuit component, which improves the integrated circuit with a high-efficiency heat dissipation structure previously applied for by the applicant. The supporting substrates of the honeycomb structure are arranged at intervals, and the gaps between adjacent supporting substrates are used as through holes. At the same time, the structure of the through holes is optimized to ensure the stability of the connection between chips and between the chips and the first substrate on the basis of improving the heat transfer efficiency of the entire component.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is an integrated circuit component, comprising: a first substrate having a substrate pad on its surface, a semiconductor substrate disposed on the first substrate, a connector connecting the substrate pad on the first substrate and the bottom surface of the semiconductor substrate, and a chip disposed on the semiconductor substrate, wherein the semiconductor substrate comprises an insulating layer disposed below the chip and a supporting substrate located below the insulating layer; wherein the supporting substrate comprises a plurality of honeycomb structures, with tapered gaps between adjacent honeycomb structures to form tapered through-holes;

[0009] Each honeycomb structure on the supporting substrate is specifically formed by providing a plurality of through holes arranged in an array on the supporting substrate, and each through hole is staggered and interconnected;

[0010] The support substrate is divided into a plurality of dodecahedral structures by through-holes, and the cross section of the semiconductor substrate is composed of a plurality of pentagons arranged in an array.

[0011] Furthermore, the upper aperture of the tapered through hole is larger than twice (within 3 times) the aperture of the through hole, and the lower aperture of the tapered through hole is larger than the maximum aperture of the through hole.

[0012] The through holes on the honeycomb structure are interconnected, which can quickly transfer the heat generated by the chip located on the upper part of the semiconductor substrate to the edge, thereby achieving an excellent heat dissipation effect. At the same time, the tapered through holes and the aperture settings (preferably 2.5 times) set between adjacent honeycomb structures make the connection between the chips and the chip and the first substrate more secure.

[0013] In addition, after actual experimental tests, the conical perforation serves as a small edge for heat transfer. If it is hollow, the air between its upper and lower interfaces will hinder heat conduction, thereby reducing the heat dissipation efficiency. Therefore, as a preferred solution, the conical perforation is filled with heat dissipation material.

[0014] As a further improvement, the inner wall of the tapered perforation has a coating layer. The coating layer may include copper, aluminum, and / or other conductive materials. Furthermore, according to prior art coating processes, the thickness of the inner wall of the tapered perforation may be uniform from top to bottom, or may gradually decrease from top to bottom. When the coating layer thickness of the inner wall of the tapered perforation gradually decreases from top to bottom, the difference between the top and middle thicknesses does not exceed 10%, and the difference between the middle and bottom thicknesses does not exceed 10%. The manufacturing process of the tapered perforation is prior art and will not be further described here.

[0015] As a further improved process, to ensure the firmness of the entire substrate, the conical through-holes are filled with two heat dissipation materials and divided into upper and lower layers according to the filling materials. The upper and lower layers of each conical through-hole are roughly parallel.

[0016] The present application has the following advantages through the above-mentioned solution: 1. The supporting substrate includes a plurality of honeycomb structures, and each honeycomb structure can be mass-produced, thereby improving production efficiency. 2. A tapered gap is provided between two adjacent honeycomb structures, and the tapered gap is filled with a heat dissipation material. At the same time, the aperture of the tapered gap is limited. On the one hand, this solution ensures the original ultra-thin process. On the other hand, the provision of the tapered gap greatly increases the toughness and firmness of the supporting substrate, further improving productivity. 3. In addition, the tapered perforation can be expanded in practical applications. According to actual needs, the perforation can be directly implemented using copper, aluminum and / or other conductive materials, or the tapered perforation can be performed first and then coated with copper, aluminum and / or other conductive materials, thereby meeting the needs of different occasions. 4. To further improve productivity, the heat dissipation material in the tapered perforation can be filled with two different materials. The upper filling material and the lower filling material can focus on different properties. For example, the upper filling material is more tough while focusing on heat dissipation, while the lower filling material is more solid while focusing on heat dissipation. The above-mentioned process can further improve the reliability and productivity of semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 This is a side view of an IC device including a TSV chip on a substrate in an embodiment of the present invention;

[0018] Figure 2 This is a three-dimensional enlarged schematic diagram of a supporting substrate of a semiconductor substrate in an embodiment of the present utility model;

[0019] Figure 3 for Figure 2 FIG. 1 is an enlarged top view of a supporting substrate of a semiconductor substrate in FIG. DETAILED DESCRIPTION

[0020] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.

[0021] In the description of this utility model, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections; direct connections, indirect connections through an intermediate medium, and internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in this utility model based on the specific circumstances.

[0022] The present application is a further improvement of an integrated circuit with a high-efficiency heat dissipation structure disclosed in a previously applied utility model patent with publication number CN108321131A. In the actual production process of the structure of the prior application, the connection between chips and between the chip and the first substrate cannot be guaranteed to be firm, which greatly affects the productivity. Therefore, the present application provides an improved integrated circuit component, which adds conical through-holes on the basis of the honeycomb structure.

[0023] See also Figure 1 The integrated circuit assembly includes: a first substrate 100 having a substrate pad disposed on its surface; a semiconductor substrate 200 disposed on the first substrate 100; connectors 300 connecting the substrate pads of the first substrate 100 and the bottom surface of the semiconductor substrate 200; and a chip disposed on the semiconductor substrate 200. The first substrate 100 may include various other substrates, such as an organic substrate, a ceramic substrate, a silicon substrate, or a silicon interposer. In this embodiment, the first substrate 100 is shown as a printed circuit board (PCB) substrate having a ball grid array (BGA) 101 on its bottom. The first substrate 100 has substrate pads 102 on its top. The substrate pads 102 are electrically connected to the semiconductor substrate 200 and the chip thereon via connectors 300. The semiconductor substrate 200 may include various substrates, such as a silicon-containing substrate (e.g., a bulk silicon substrate), silicon germanium, silicon carbide, GaN, or a silicon-on-insulator (SOI) substrate.

[0024] The semiconductor substrate 200 includes an insulating layer 210 disposed at the bottom of the chip and a supporting substrate 220 located at the bottom of the insulating layer 210; Figure 2 and Figure 3 The supporting substrate 220 includes a plurality of honeycomb structures, with tapered gaps between adjacent honeycomb structures to form tapered through-holes 230. Each honeycomb structure on the supporting substrate is formed by a plurality of through-holes 221 arranged in an array on the supporting substrate. The through-holes 221 are staggered and interconnected. The upper aperture diameter d1 of the tapered through-hole 230 is greater than twice (but within three times) the aperture diameter of the through-hole, and the lower aperture diameter d2 of the tapered through-hole is greater than the maximum aperture diameter of the through-hole.

[0025] In this embodiment, considering the use of the support substrate 220 as a support chip and the convenience of production, as a consideration of the preparation process - the honeycomb structure of the dodecahedron is easier to grow, the support substrate 220 introduced in this embodiment is divided into multiple dodecahedron structures (or dodecahedron-like structures) by the through-holes 221, and the cross-section of the support substrate 220 is composed of multiple arrayed pentagons. Among them, the dodecahedron structure can be a regular dodecahedron (composed of 12 regular pentagons) or a non-regular dodecahedron realized by non-regular pentagons. Among them, the dodecahedron structure in this embodiment is a regular dodecahedron, or a quasi-regular dodecahedron (close to a regular dodecahedron). Figure 2 The enlarged perspective view of the supporting substrate of the semiconductor substrate is shown, wherein a plurality of dodecahedron structures are arranged in an array, and the honeycomb structure is divided into several dodecahedron structures by the conical through-holes 230. Figure 3 As can be seen from the top view of the enlarged schematic diagram, there are through holes 221 between adjacent dodecahedron structures and tapered through holes 230 between adjacent honeycomb structures. As can be seen from the figure, the through holes 221 are interconnected, so that the heat in the center can be quickly dispersed to the surrounding side.

[0026] Current advanced packaging technologies require continuous thinning of chip thickness. Backside thinning of the semiconductor substrate 200 of a fabricated device is a crucial step in the packaging manufacturing process. Thinning improves heat dissipation efficiency, mechanical and electrical properties, reduces chip packaging volume, and reduces dicing processing. Taking silicon substrates as an example, a 200mm diameter silicon substrate for a fabricated device can currently be thinned to 0.12-0.15mm. The effective thickness of the circuit layer on a silicon substrate is generally 5-10μm. To ensure functionality and a certain support thickness, the maximum thickness for silicon substrate thinning is 20-30μm. Currently, the average thickness of a 300mm diameter silicon substrate on the market is 775μm, and the average thickness of a 200mm diameter silicon substrate is 725μm. Such thick substrates are required to ensure sufficient strength during chip manufacturing, testing, and transportation. Therefore, after the circuit layer is fabricated, the backside of the silicon substrate needs to be thinned. The thinner the substrate, the greater its flexibility and the less stress caused by external impact. The backside thinning process for semiconductor substrate 200 typically involves complex processes such as ultra-precision grinding, lapping, polishing, and etching. However, using the structure of the present invention, the supporting substrate 220 of semiconductor substrate 200 is directly grown into multiple honeycomb structures, with tapered through-holes 230 between adjacent honeycomb structures. An insulating layer 210 is then formed on the surface of the supporting substrate 220 to obtain the entire semiconductor substrate 200. Therefore, the structure of the present invention can significantly reduce the thickness of semiconductor substrate 200 and eliminate the need for complex backside thinning processes, significantly reducing the difficulty of producing ultra-thin semiconductor substrates 200. Furthermore, the honeycomb structure of semiconductor substrate 200 further enhances its overall flexibility, significantly reduces stress caused by external impact, and enhances its overall strength.

[0027] The through holes on the honeycomb structure are interconnected, which can quickly transfer the heat generated by the chip located on the upper part of the semiconductor substrate to the edge, thereby achieving an excellent heat dissipation effect. At the same time, the tapered through holes and the aperture settings (preferably 2.5 times) set between adjacent honeycomb structures make the connection between the chips and the chip and the first substrate more secure.

[0028] As an optional solution, the conical perforation is made of copper, aluminum and / or other conductive materials; or, after the conical perforation is formed without conductive materials, its inner wall is provided with a coating layer, and the material of the coating layer may include copper, aluminum and / or other conductive materials. In addition, according to the coating process of the prior art, the thickness of the coating layer on the inner wall of the conical perforation is uniform from top to bottom, or it may gradually decrease from top to bottom. When the thickness of the coating layer of the conical perforation gradually decreases from top to bottom, the difference between the top thickness and the middle thickness does not exceed 10%, and the difference between the middle thickness and the bottom thickness does not exceed 10%. The manufacturing process of the conical perforation is a prior art, so it will not be described here.

[0029] In addition, through actual experimental tests, it was found that the conical perforation, as a small edge for heat transfer, would hinder heat conduction due to the air between its upper and lower interfaces if it were hollow, thereby reducing the heat dissipation efficiency. Therefore, the conical perforation, like the through-hole, is filled with heat dissipation material.

[0030] As a further improvement, to ensure the robustness of the entire substrate, the tapered vias are filled with two types of heat dissipation materials. These materials are divided into upper and lower layers, with the upper and lower layers of each tapered via being roughly parallel. In actual fabrication, the upper and lower filler materials can prioritize different properties. For example, the upper filler material can be more resilient while maintaining heat dissipation, while the lower filler material can be more robust while maintaining heat dissipation. This process can further improve the reliability and productivity of semiconductor devices.

[0031] The heat dissipation material can be a material with a high heat dissipation coefficient known in the art, or it can be a heat dissipation material of a custom design. In the present invention, a composite heat dissipation material designed by the applicant is employed. This composite heat dissipation material has been disclosed in a prior application. The composition of the filler material in the upper and lower layers can be adjusted based on their respective properties, and will not be described in detail here.

[0032] Through the above-mentioned scheme, the present application makes the supporting substrate include several honeycomb structures, each honeycomb structure can be produced on a large scale, and a conical gap is set between two adjacent honeycomb structures, and the conical gap is filled with heat dissipation material. At the same time, the aperture of the conical gap is limited. On the one hand, it not only ensures the original ultra-thin process, but also greatly increases the toughness and firmness of the supporting substrate due to the setting of the conical gap, further improves productivity, and has good practicality.

[0033] Although the present invention has been specifically shown and described in conjunction with the preferred embodiments, those skilled in the art should understand that various changes can be made to the form and details of the present invention without departing from the spirit and scope of the present invention as defined by the appended claims, and all of these changes are within the scope of protection of the present invention.

Claims

1. An integrated circuit component, comprising a first substrate having a substrate pad on its surface, a semiconductor substrate disposed on the first substrate, a connector connecting the substrate pad of the first substrate and the bottom surface of the semiconductor substrate, and a chip disposed on the semiconductor substrate, wherein the semiconductor substrate comprises an insulating layer disposed under the chip and a supporting substrate disposed under the insulating layer; characterized in that: The support substrate includes a plurality of honeycomb structures, and there are conical gaps between adjacent honeycomb structures to form conical through-holes; The honeycomb structure is specifically formed by providing a plurality of through holes arranged in an array on the support substrate, wherein the through holes are staggered and interconnected; The support substrate is divided into a plurality of dodecahedral structures by through-holes, and the cross section of the semiconductor substrate is composed of a plurality of pentagons arranged in an array.

2. The integrated circuit assembly according to claim 1, wherein: The upper aperture of the tapered through hole is larger than twice the aperture of the through hole, and the lower aperture of the tapered through hole is larger than the maximum aperture of the through hole.

3. The integrated circuit assembly according to claim 1 or 2, characterized in that: The inner wall of the tapered through hole has a coating layer.

4. The integrated circuit assembly according to claim 3, characterized in that: The thickness of the coating layer of the tapered perforation is uniform from top to bottom, or can be gradually reduced from top to bottom.

5. The integrated circuit assembly according to claim 3, wherein: The difference between the top thickness and the middle thickness of the coating layer of the tapered perforation does not exceed 10%, and the difference between the middle thickness and the bottom thickness does not exceed 10%.

6. The integrated circuit assembly according to claim 1, wherein: The conical through hole is filled with two kinds of heat dissipation materials and is divided into an upper layer and a lower layer according to the filling materials.

7. The integrated circuit assembly according to claim 1, wherein: The dodecahedron structure is a regular dodecahedron.

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