Transistor and electric equipment

Abstract

The utility model discloses a transistor and electric equipment, the transistor comprises a first P-type well layer, a first N + source layer and a grid layer, the first P-type well layer comprises a first surface, and a groove is formed inwards from the first surface; the first N + source layer is accommodated in the groove, and the first N + source layer comprises a second surface facing the same direction as the first surface; the gate layer is disposed on the first surface and the second surface. The transistor can solve the problem of poor output capability.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductor devices, in particular to a transistor and an electrical device. Background Art

[0002] As people pay more and more attention to environmental protection and low carbon, the pace of development of new energy vehicles has also accelerated significantly. The integration of automobiles with related technologies in the fields of energy, transportation, information and communications has accelerated, and electrification, networking and intelligence have become the development trend of the automobile industry.

[0003] MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a semiconductor device widely used for switching purposes and amplification of electronic signals in electronic devices. The size of MOSFET is very small and can be designed and manufactured in a single chip, which can be either a core or an integrated circuit. MOSFET is a multi-layer structure, and the double trench structure in the prior art cannot effectively shield the electric field under the gate dielectric layer, or in order to shield the electric field under the gate layer, the introduction of the P+ shielding layer inevitably introduces an additional JFET structure, which limits the flow path width of electrons from the channel to the N-type epitaxial layer and increases the device on-resistance; and most of the existing structures require careful adjustment between the gate-drain capacitance, switching loss and on-resistance, which cannot most effectively reduce the switching loss, and the shielding layer cannot be effectively grounded, which is also not conducive to the switching characteristics and high-frequency applications of the device. In summary, the performance of the existing MOSFET is still not ideal and the output capacity is poor, and it is key to provide a MOS transistor with high output capacity. Utility Model Content

[0004] The utility model aims to provide a transistor and an electrical device to solve the problem of poor output capability of the transistor.

[0005] In order to achieve the purpose of the utility model, the utility model provides the following technical solutions:

[0006] In a first aspect, the utility model provides a transistor, comprising a first P-type well layer, a first N+ source layer and a gate layer, wherein the first P-type well layer comprises a first surface, a groove is formed inward from the first surface; the first N+ source layer is accommodated in the groove, and the first N+ source layer comprises a second surface having the same orientation as the first surface; the gate layer is arranged on the first surface and the second surface.

[0007] In one embodiment, the gate layer includes a first gate layer and a second gate layer, and the first gate layer and the second gate layer are spaced apart.

[0008] In one embodiment, a first spacing groove is formed between the first gate layer and the second gate layer, and the transistor includes a source metal layer, wherein the source metal layer is arranged on a side of the gate layer facing away from the first N+ source layer, and at least a portion of the source metal layer extends into the first spacing groove.

[0009] In one embodiment, the source metal layer extending into the spacing groove is connected to the second surface.

[0010] In one embodiment, the first P-type well layer includes a P-type well layer 1 and a P-type well layer 2, the P-type well layer 1 and the P-type well layer 2 are arranged at intervals, the P-type well layer 1 forms a first sub-groove, and the P-type well layer 2 forms a second sub-groove, the first N+ source layer includes an N+ source layer 1 and an N+ source layer 2, the N+ source layer 1 is accommodated in the first sub-groove, and the N+ source layer 2 is accommodated in the second sub-groove, the first gate layer is arranged on the P-type well layer 1, and the second gate layer is arranged on the P-type well layer 2.

[0011] In one embodiment, the transistor also includes a P+ type shielding layer, the first P-type well layer is connected to the P+ type shielding layer, the first surface is facing away from the P+ type shielding layer, a second spacing groove is between the P-type well layer one and the P-type well layer two, the first spacing groove and the second spacing groove are connected, at least a portion of the source metal layer extends into the second spacing groove and is connected to the P+ type shielding layer, or at least a portion of the P+ type shielding layer extends into the second spacing groove and is connected to the source metal layer.

[0012] In one embodiment, the transistor also includes an N-type epitaxial layer and an N+ type extension layer, the N-type epitaxial layer includes an injection surface, and an injection groove is formed inward from the injection surface; the N+ type extension layer is connected to the inner wall of the injection groove; the first P-type well layer and the P+ type shielding layer are accommodated in the injection groove, and the P+ type shielding layer is connected to the side of the N+ type extension layer facing away from the N-type epitaxial layer.

[0013] In one embodiment, the sum of the thicknesses of the P+ type shielding layer, the first N+ source layer and the first P type well layer is less than the depth of the implantation groove.

[0014] In one implementation, the width of the first P-type well layer is less than or equal to the width of the gate layer, and / or the width of the P+-type shielding layer is greater than or equal to the width of the gate layer.

[0015] In a second aspect, the utility model further provides an electrical device, wherein the electrical device comprises the transistor as described in any one of the first aspects.

[0016] The utility model introduces a new first P-type well layer and a first N+ source layer below the gate layer, and utilizes the first P-type well layer and the first N+ source layer to contact the source side of the transistor, thereby introducing a new lateral channel, and further improving the output capacity of the transistor; and the first P-type well layer and the first N+ source layer structure below the gate layer form a new lateral channel, which fully utilizes the volume of the device and is beneficial to improving the output capacity of the device; and, by introducing the first P-type well layer, the electric field strength and gate-drain capacitance in the gate layer can be effectively reduced, thereby improving the voltage resistance and operating frequency of the device, and improving the overall electrical characteristics and reliability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the implementation methods of the utility model or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a schematic diagram of a cross-sectional structure of a transistor according to an embodiment;

[0019] Figure 2 is a schematic diagram of a cross-sectional structure of a transistor according to another embodiment;

[0020] Figure 3 is a schematic diagram of a cross-sectional structure of a transistor according to another embodiment.

[0021] Explanation of the accompanying drawings: 1-drain metal layer, 2-N+ type substrate layer, 3-N-type epitaxial layer, 4-N+ ​​type extension layer, 5-P+ type shielding layer, 6-first P-type well layer, 7-first N+ source layer, 8-first dielectric layer, 9-second dielectric layer, 10-third dielectric layer, 11-polysilicon gate, 12-second P-type well layer, 13-P+ contact layer, 14-second N+ source layer, 15-fourth dielectric layer, 16-source metal layer. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0023] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there can be a central component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there can be a central component at the same time.

[0024] Unless otherwise defined, all technical and scientific terms used in this utility model have the same meaning as those commonly understood by technicians in the technical field of this utility model. The terms used in the specification of this utility model are only for the purpose of describing specific embodiments and are not intended to limit this utility model. The term "and / or" used in this utility model includes any and all combinations of one or more related listed items.

[0025] In conjunction with the accompanying drawings, some embodiments of the present invention are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0026] The utility model provides a transistor, specifically a SiC MOSFET device structure with a novel trench type. MOSFET is a semiconductor device widely used for switching purposes and amplification of electronic signals in electronic devices. The size of MOSFET is very small and can be designed and manufactured in a single chip, which can be both a core and an integrated circuit.

[0027] In one implementation, please refer to Figure 1 The transistor includes a drain metal layer 1 and an N+ type substrate layer 2. The drain metal layer 1 is the bottom layer of the transistor, and the N+ type substrate layer 2 is connected to the drain metal layer 1. The drain metal layer 1 and the N+ type substrate layer 2 are in ohmic contact. In this embodiment, the material of the drain metal layer 1 can be an existing common metal type, which is not described here. The drain electrode of the transistor can be formed by the drain metal layer 1 on the back of the transistor.

[0028] In one implementation, please refer to Figure 1 The transistor includes an N-type epitaxial layer 3 and an N+ type extension layer 4. The N-type epitaxial layer 3 includes an injection surface, and an injection groove is formed inward from the injection surface; the N+ type extension layer 4 is connected to the inner wall of the injection groove.

[0029] Specifically, the N-type epitaxial layer 3 is connected to the N+ type substrate layer 2 and is located on the side of the N+ type substrate layer 2 facing away from the drain metal layer 1. The side of the N-type epitaxial layer 3 facing away from the N+ type substrate layer 2 is the injection surface. The N+ type extension layer 4 is embedded in the N-type epitaxial layer 3 from the injection surface.

[0030] It should be explained that both the N+ type extension layer 4 and the N- type epitaxial layer 3 are N-type semiconductor layers, so the difference between the N+ type extension layer 4 and the N- type epitaxial layer 3 lies in the different concentrations or types of doped elements; in the transistor, the N+ type extension layer 4 is formed by injecting different elements (including concentrations and types) into the original N- type epitaxial layer 3.

[0031] Therefore, the specific shape of the injection groove cannot be observed on the N-type epitaxial layer 3, and the inner wall of the injection groove is the interface connecting the N+ type extension layer 4 and the N-type epitaxial layer 3. Figure 1 As shown, in the cross-sectional structure of the transistor, since the N+ type extension layer 4 is obtained by injecting elements from the injection surface, the N+ type extension layer 4 is similar to being embedded in the N- type epitaxial layer 3. If only the N- type epitaxial layer 3 is observed, a hierarchical structure with grooves will be obtained.

[0032] In one implementation, please refer to Figure 1 The transistor further includes a P+ type shielding layer 5 , which is received in the implantation groove and connected to a side of the N+ type extension layer 4 facing away from the N- type epitaxial layer 3 .

[0033] Specifically, the N+ type extension layer 4 covers the inner wall of the injection groove, and the P+ type shielding layer 5 is located in the injection groove and connected to the N+ type extension layer 4. Thus, the N-type epitaxial layer 3, the N+ type extension layer 4, and the P+ type shielding layer 5 form a three-layer nested structure; that is, the periphery of the P+ type shielding layer 5 is the N+ type extension layer 4, and the periphery of the N+ type extension layer 4 is the N-type epitaxial layer 3.

[0034] It needs to be explained that the P+ type shielding layer 5 is a P-type semiconductor layer, so the difference between the P+ type shielding layer 5 and the N-type epitaxial layer 3 lies in the different types of doped elements; in the transistor, the P+ type shielding layer 5 is formed by injecting different types of elements into the original N-type epitaxial layer 3.

[0035] So, if Figure 1 As shown in the cross-sectional structure of the transistor, since both the N+ type extension layer 4 and the P+ type shielding layer 5 are obtained by injecting elements from the injection surface, the N+ type extension layer 4 is similar to being embedded in the N-type epitaxial layer 3, and the P+ type shielding layer 5 is similar to being embedded in the N+ type extension layer 4. In this embodiment, Figure 1 As shown, in the cross section of the transistor, the N+ type extension layer 4 is similar to a "U"-shaped half-enclosed structure, and the P+ type shielding layer 5 is contained in the "U"-shaped N+ type extension layer 4. A U-shaped highly doped N+ type extension layer 4 is surrounded by the P+ type shielding layer 5. The doping concentration of the N+ type extension layer 4 is at least 5 times that of the drift region.

[0036] The utility model connects an N+ type extension layer 4 to the inner wall of the injection groove of the N-type epitaxial layer 3, and uses the N+ type extension layer 4 to wrap the P+ type shielding layer 5, so that the N+ type extension layer 4 forms a "U"-shaped wrapping structure, and the gate layer is connected to the other exposed surface of the P+ type shielding layer 5; the combination of the N+ type extension layer 4 and the P+ type shielding layer 5 can effectively shield the electric field under the gate layer and improve the voltage resistance of the transistor; at the same time, the N+ type extension layer 4 can effectively deplete the electric field and reduce the conduction loss of the transistor; the current in the transistor is transmitted along the N+ type extension layer 4, thereby effectively reducing the on-resistance of the device.

[0037] In one implementation, please refer to Figure 1 The transistor includes a first P-type well layer 6, a first N+ source layer 7 and a gate layer, wherein the first P-type well layer 6 includes a first surface, and a groove is formed inward from the first surface; the first N+ source layer 7 is accommodated in the groove, and the first N+ source layer 7 includes a second surface having the same orientation as the first surface; the gate layer is arranged on the first surface and the second surface.

[0038] Specifically, the first P-type well layer 6 is connected to the P+ type shielding layer 5, and the first surface faces away from the P+ type shielding layer 5. The first P-type well layer 6, the first N+ source layer 7 and the P+ type shielding layer 5 are all contained in the injection groove. The first P-type well layer 6 is similar to a "U"-shaped half-enclosed structure, and the first N+ source layer 7 is contained in the "U"-shaped first P-type well layer 6.

[0039] The utility model introduces a new first P-type well layer 6 and a first N+ source layer 7 below the gate layer. The first P-type well layer 6 and the first N+ source layer 7 can be in contact with the side or front side of the source of the transistor, thereby introducing a new lateral channel to further improve the output capacity of the transistor; and the first P-type well layer 6 and the first N+ source layer 7 structure below the gate layer form a new lateral channel, which fully utilizes the volume of the device and is beneficial to improving the output capacity of the device; and, by introducing the first P-type well layer 6, the electric field strength and gate-drain capacitance in the gate layer can be effectively reduced, thereby improving the voltage resistance and operating frequency of the device, and improving the overall electrical characteristics and reliability of the device.

[0040] In one implementation, please refer to Figure 1 The transistor also includes a second P-type well layer 12, a P+ contact layer 13 and a second N+ source layer 14. The second P-type well layer 12 is arranged on the injection surface, the P+ contact layer 13 and the second N+ source layer 14 are arranged on the side of the second P-type well layer 12 facing away from the injection surface, and the P+ contact layer 13 is arranged on the periphery of the second N+ source layer 14; the second N+ source layer 14, the second P-type well layer 12 and the P+ shielding layer 5 jointly enclose the gate trench, and the gate layer is accommodated in the gate trench.

[0041] Specifically, the second P-type well layer 12 is connected to the N-type epitaxial layer 3, and the P+ contact layer 13 and the second N+ source layer 14 are both connected to the second P-type well layer 12. The top surface of the second N+ source layer 14 is recessed downward, and the second N+ source layer 14 and the second P-type well layer 12 are sequentially penetrated to form a gate trench, the bottom wall of the gate trench is the P+ type shielding layer 5, the first P-type well layer 6, the first N+ source layer 7 and the gate layer are accommodated in the gate trench, so that the first P-type well layer 6 is connected to the P+ type shielding layer 5. Therefore, the periphery of the gate layer is connected to the second N+ source layer 14 and the second P-type well layer 12.

[0042] It should be explained that the second P-type well layer 12, the P+ contact layer 13 and the second N+ source layer 14 can all be obtained by implanting different elements, and the gate groove can be prepared before the second P-type well layer 12, the P+ contact layer 13 and the second N+ source layer 14 are formed. For example, the N-type epitaxial layer 3 is prepared in advance, and then the gate groove is etched on the N-type epitaxial layer 3, and then the second P-type well layer 12, the P+ contact layer 13 and the second N+ source layer 14 are sequentially prepared by local ion implantation.

[0043] It can be understood that the second N+ source layer 14 and the P+ contact layer 13 are located above the second P-type well layer 12, and the second N+ source layer 14 and the P+ contact layer 13 are surrounded by the second P-type well layer 12, the second N+ source layer 14 and the P+ contact layer 13 are in contact with each other, and are used to contact the source metal.

[0044] In one embodiment, the depth of the gate trench is 1 μm to 2.5 μm. Specifically, the depth of the gate trench can be 1 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm, 2 μm, 2.2 μm, 2.4 μm, 2.5 μm. It can be understood that the depth of the gate trench is greater than the depth of the second P-type well layer 12 (i.e., penetrates the second P-type well layer 12).

[0045] In one embodiment, the P+ type shielding layer 5 includes a third surface, the third surface is oriented in the same direction as the first surface, and in the thickness direction of the P+ type shielding layer 5 , the N+ type extension layer 4 protrudes from the third surface, and the gate layer contacts the N+ type extension layer 4 .

[0046] Specifically, the third surface of the P+ type shielding layer 5 is the bottom surface of the above-mentioned middle gate trench. In the thickness direction of the transistor, the height of the third surface is lower than the height of the injection surface. And based on the above-mentioned embodiment, the N+ type extension layer 4 is obtained by injecting elements on the injection surface, and the highest point of the N+ type extension layer 4 is also located at the injection surface, that is, the N+ type extension layer 4 protrudes from the third surface.

[0047] Since the N+ type extension layer 4 is higher than the P+ type shielding layer 5, the outer peripheral wall of the gate layer is also connected to the N+ type extension layer 4. That is, on the basis of the above embodiment, the second N+ source layer 14, the second P type well layer 12, the N+ type extension layer 4, and the P+ type shielding layer 5 jointly enclose the gate trench. Therefore, the side wall of the gate layer is connected to the second N+ source layer 14, the second P type well layer 12 and the N+ type extension layer 4, and the bottom wall of the gate layer is connected to the first N+ source layer 7 and the first P type well layer 6.

[0048] By setting the height and width of the N+ type extension layer 4 to be greater than the P+ type shielding layer 5 and the bottom of the gate layer being located in the N+ type extension layer 4 , the on-resistance of the transistor can be effectively reduced.

[0049] In one implementation, please refer to Figure 1 The gate layer includes a polysilicon gate 11 and a dielectric layer wrapped around the polysilicon gate 11, and the dielectric layer is connected to the first surface and the second surface.

[0050] In one embodiment, the outer periphery of the dielectric layer has a chamfer, and the chamfer is a right-angle chamfer or a rounded chamfer.

[0051] Specifically, the dielectric layer has a bottom surface and a side surface, wherein the bottom surface is connected to the first N+ source layer 7 and the first P-type well layer 6, and the side surface is connected to the second N+ source layer 14, the second P-type well layer 12 and the N+ type expansion layer 4. There is a chamfer between the bottom surface and the side surface, and the type of the chamfer includes a right-angle chamfer or a rounded chamfer. It needs to be explained that the right-angle chamfer and the rounded chamfer are different chamfer types, and the rounded chamfer has a larger chamfer arc.

[0052] In one embodiment, the cross-sectional shape of the gate is a quadrilateral or a fan-shaped gate. Of course, the gate shape is one of a fin gate, a V-shaped gate, and a strip gate, and there is no specific limitation.

[0053] In one implementation, please refer to Figure 1 The dielectric layer includes a first dielectric layer 8, a second dielectric layer 9, a third dielectric layer 10 and a fourth dielectric layer 15 which are connected in sequence in a ring shape around the polysilicon gate 11, wherein the first dielectric layer 8 and the fourth dielectric layer 15 are arranged opposite to each other in the thickness direction of the gate layer.

[0054] Specifically, the dielectric layer may be a quadrilateral annular layer structure (viewed in cross section), wherein the first dielectric layer 8 connects one side and the second side; in the thickness direction of the gate layer, the first dielectric layer 8 is a polysilicon gate 11, and the fourth dielectric layer 15 is on the polysilicon gate 11.

[0055] The left and right sides of the polysilicon gate 11 are the second dielectric layer 9 and the third dielectric layer 10. In a specific embodiment, the second dielectric layer 9 and the third dielectric layer 10 are connected to the second N+ source layer 14, the second P-type well layer 12 and the N+ type extension layer 4. The right side of the polysilicon gate 11 is the second dielectric layer 9, and the left side of the polysilicon is the third dielectric layer 10.

[0056] In one implementation, please refer to Figure 1 , the thickness and material of the first dielectric layer 8, the second dielectric layer 9, the third dielectric layer 10, and the fourth dielectric layer 15 may not be all the same. Specifically, each dielectric layer may be composed of a single dielectric layer material or a multi-layer composite dielectric material, and the thickness of the dielectric layer in different regions may be different. The dielectric layer may be prepared by a thermal oxidation process and a deposition process. Of course, in other embodiments, the dielectric layer may adopt a composite dielectric layer structure, such as: Al2O3 / SiO2.

[0057] In one embodiment, the gate layer includes a first gate layer and a second gate layer, and the first gate layer and the second gate layer are spaced apart.

[0058] Specifically, there are two gate layers, the two gate layers are symmetrical and spaced apart, and the symmetry planes of the two gate layers are parallel to the thickness direction of the gate layers. Figure 1 As shown, in the cross section of the transistor, the two gate layers are arranged on the left and right. Moreover, the two gate layers are arranged symmetrically, and the symmetry plane is parallel to the thickness direction of the gate layer; it should be explained that the symmetry plane does not appear in the transistor, and the symmetry plane provided above is set for the convenience of describing the positional relationship between the two gate layers.

[0059] It can be understood that based on the above embodiment, two gate layers are arranged in the gate trench, each gate layer includes a polysilicon gate 11 and a dielectric layer, and the arrangement of the dielectric layer and the polysilicon gate 11 can refer to the above embodiment, and the details are not repeated here.

[0060] The utility model adopts a separated gate structure to effectively reduce the contact area between the gate and the drain, effectively reduce the gate-drain capacitance of the device, and thus reduce the switching loss.

[0061] In one implementation, please refer to Figure 2 and Figure 3 There is a first spacing groove between the two gate layers. The transistor includes a source metal layer 16. The source metal layer 16 is arranged on a side of the gate layer facing away from the first N+ source layer 7. At least a portion of the source metal layer 16 extends into the first spacing groove.

[0062] Specifically, the source metal layer 16 and the drain metal layer 1 are arranged opposite to each other, and the source metal layer 16 is located on the top surface of the transistor. Based on the above embodiment, the two gate layers are arranged in intervals, and the interval between the two gate layers is set as a first interval groove. The interval groove can be an extension of the source metal layer 16, and optionally, a thickened metal is deposited on the gate layer (forming the source metal layer 16).

[0063] It can be understood that the material portion in the first spacing groove is the same as the material of the corresponding level extension portion. For example, the spacing groove is an extension portion of the source metal layer 16, so the material in the spacing groove is the same as the material of the source metal layer 16. Therefore, by setting two gate layers and setting a source contact area between the dielectric layers of the two gate layers, the source metal layer 16 and the P+ type shielding layer 5 can be turned on.

[0064] Based on the above implementation, the dielectric layers in the two gate layers contact different levels. Figure 2 As shown, the left side may be the first gate layer and the right side may be the second gate layer; wherein the second dielectric layer 9 in the first gate layer is located on the left side and is connected to the second N+ source layer 14, the second P-type well layer 12 and the P+ type shielding layer 5, and the third dielectric layer 10 is located on the right side and is connected to the source metal layer 16; the second dielectric layer 9 in the second gate layer is located on the right side and is connected to the N+ source layer, the P-type well layer and the P+ type shielding layer 5, and the third dielectric layer 10 is located on the left side and is connected to the source metal layer 16.

[0065] The utility model adopts a separated gate structure to effectively reduce the contact area between the polysilicon gate 11 and the drain metal layer 1, effectively reducing the gate-drain capacitance of the transistor and thus reducing the switching loss; and the utility model adopts a separated gate structure scheme, the source metal layer 16 is directly connected to the P+ type shielding layer 5 below the gate layer through the spacing groove between the two gate layers, effectively ensuring the shielding effect of the P+ type shielding layer 5, reducing the capacitance between the gate and the drain and avoiding charge storage in the shielding layer, thereby optimizing the switching performance of the device, reducing the electric field strength faced by the dielectric layer and the switching loss of the transistor.

[0066] In one implementation, please refer to Figure 2 and Figure 3 , the source metal layer 16 extending into the spacing groove is connected to the second surface.

[0067] Specifically, based on the above embodiment, the source metal in the spacing groove is connected to the first N+ source layer 7 , and is connected to the first P-type well layer 6 through a combination of the first N+ source layer 7 and the first P-type well layer 6 .

[0068] In one implementation, please refer to Figure 2 and Figure 3The first P-type well layer 6 includes a P-type well layer 1 and a P-type well layer 2, the P-type well layer 1 and the P-type well layer 2 are arranged at intervals, the P-type well layer 1 forms a first sub-groove, and the P-type well layer 2 forms a second sub-groove, the first N+ source layer 7 includes an N+ source layer 1 and an N+ source layer 2, the N+ source layer 1 is accommodated in the first sub-groove, and the N+ source layer 2 is accommodated in the second sub-groove, the first gate layer is arranged on the P-type well layer 1, and the second gate layer is arranged on the P-type well layer 2.

[0069] Specifically, the first P-type well layer 6 includes a symmetrically arranged P-type well layer 1 and a P-type well layer 2, such as Figure 2 and Figure 3 As shown, the cross-sectional shapes of the P-type well layer 1 and the P-type well layer 2 are both "L" shaped, and the grooves in the above embodiment include two, namely the first sub-groove and the second sub-groove. The first N+ source layer 7 includes a symmetrically arranged N+ source layer 1 and an N+ source layer 2, wherein the N+ source layer 1 is accommodated in the first sub-groove and the N+ source layer 2 is accommodated in the second sub-groove.

[0070] In one implementation, please refer to Figure 2 and Figure 3 There is a second spacing groove between the P-type well layer 1 and the P-type well layer 2, the first spacing groove is connected to the second spacing groove, and at least a portion of the source metal layer 16 extends into the second spacing groove and is connected to the P+ type shielding layer 5.

[0071] Specifically, the P-type well layer 1 and the N+ source layer 1 together constitute the combination 1, the P-type well layer 2 and the N+ source layer 2 together constitute the combination 2, and there is a spacing distance between the combination 1 and the combination 2, and the spacing distance is the second spacing groove. It can be understood that the second spacing groove can be an extension of the first spacing groove, and the P+ type shielding layer 5 (third surface) is exposed through the second spacing groove. The source metal extends into the second spacing groove and is connected to the P+ type shielding layer 5 (third surface).

[0072] In one implementation, please refer to Figure 3 At least a portion of the P+ type shielding layer 5 extends into the second spacing groove and is connected to the source metal layer 16 .

[0073] Specifically, based on the above implementation, at least a portion of the P+ type shielding layer 5 may extend into the second isolation groove and then be connected to the source metal in the first isolation groove.

[0074] The utility model adopts a separated gate structure, and the source metal can be directly connected to the P+ type shielding layer 5 under the gate through the first spacing groove and the second spacing groove, which effectively ensures the shielding effect of the shielding layer and further reduces the capacitance between the gate and the drain, thereby reducing the electric field strength faced by the gate dielectric layer and the switching loss of the device.

[0075] In one embodiment, the sum of the thicknesses of the P+ type shielding layer 5, the first N+ source layer 7 and the first P type well layer 6 is less than the depth of the implantation groove. Figure 1 As shown, the thickness of the P+ type shielding layer 5, the first N+ source layer 7 and the first P type well layer 6 is the dimension in the longitudinal direction (Y direction in the figure) of the transistor.

[0076] In one embodiment, the width of the first P-type well layer 6 is less than or equal to the width of the gate layer, and / or the width of the P+ type shielding layer 5 is greater than or equal to the width of the gate layer. Figure 1 As shown, the width of the first P-type well layer 6 is the dimension of the transistor in the lateral direction (X direction in the figure).

[0077] In one embodiment, the concentration of the doping element in the P+ type shielding layer 5 is higher than the concentration of the doping element in the N+ type extension layer 4 .

[0078] In one embodiment, the doping element in the P+ type shielding layer 5 is aluminum or boron. By arranging a highly doped P+ type shielding layer 5 below the gate layer, and the doping element is aluminum or boron, the P+ type shielding layer 5 is directly connected to the source metal layer 16. Of course, in other embodiments, the connection method can be achieved through different processes and technologies, such as direct metal connection and P+ doping connection.

[0079] In one embodiment, a specific method for manufacturing a transistor includes the following steps:

[0080] Step S1, growing an N-type epitaxial layer with a low doping concentration on an N+ type SiC substrate.

[0081] Step S2, using local ion implantation, by changing the type, dosage and energy of the implanted ions, a P+ type shielding layer (Al or B) and an N+ type extension layer (N or P) with different doping concentrations and types are prepared in the N-type epitaxial layer.

[0082] Step S3, using local ion implantation, by changing the type, dosage and energy of the implanted ions, a first N+ source layer and a first P-type well layer with different doping concentrations and types are prepared in the N-type epitaxial layer (above the P+ type shielding layer).

[0083] Step S4, etching a gate trench in the N+ type extension layer and above (or in the upper part of) the P+ type shielding layer by using a local etching method.

[0084] Step S5, using local ion implantation, by changing the type, dosage and energy of implanted ions, a P-type well layer, a P+ contact layer and an N+ source layer with different doping concentrations and positions are prepared in the N-type epitaxial layer.

[0085] Step S6, preparing a dielectric layer by using a thermal oxidation process and a dielectric layer deposition process, and preparing a polysilicon gate by using a local etching process and a polysilicon precipitation process.

[0086] Step S7, depositing an isolation dielectric layer above the polysilicon gate and patterning it.

[0087] Step S8, using a local etching process to form a spacing groove between the two gate layers.

[0088] Step S9, preparing source ohmic contact and depositing thickened metal.

[0089] Step S10, preparing drain contacts and depositing thickened metal.

[0090] The N+ type SiC substrate in step S1 is the N+ type substrate layer in the above embodiment. In other embodiments, a portion of the P+ contact area can be retained by a local etching process in step S4. The dielectric layer in step S6 includes a first dielectric layer, a second dielectric layer and a third dielectric layer.

[0091] The utility model can prepare a transistor through the above preparation method, and the transistor is a new trench-type SiC MOSFET device structure. Figure 1 As shown, the transistor includes, from bottom to top, a drain metal layer, an N+ substrate layer, an N-type epitaxial layer, an N+ extension layer, a P+ shielding layer, a first P-type well layer, a first N+ source layer, a gate layer (including a polysilicon gate and a dielectric layer), a second P-type well layer, a P+ contact layer, a second N+ source layer, a gate oxide layer, and a source metal layer. The transistor has a separated gate structure, and the transistor is symmetrical about the central axis.

[0092] The utility model reduces the contact area of ​​the gate and drain through the separated gate structure and effectively realizes the grounding of the P+ type shielding layer (it may not be grounded in some examples), reduces the gate-drain capacitance and the switching loss of the device, and improves the switching performance of the device. In addition, the introduction of the P+ type shielding layer effectively reduces the electric field strength faced by the gate dielectric layer and improves the robustness of the device. The surrounding U-shaped N+ type expansion layer can effectively deplete the electric field and further optimize the on-resistance of the device. In addition, by introducing a new first N+ source layer and a first P-type well layer in contact with the side of the source (it can also be in front contact), a new lateral channel is introduced to further improve the output capacity of the device.

[0093] In one embodiment, the utility model further provides an electric device, the electric device includes the transistor in the above embodiment, or the electric device includes a transistor obtained by the manufacturing method of the transistor in the above embodiment. Optionally, the electric device can be a terminal device such as a battery pack, a new energy vehicle, and an energy storage cabinet.

[0094] In the description of the embodiments of the present invention, it should be noted that the orientation or positional relationship of terms such as "center", "up", "down", "left", "right", "vertical", "horizontal", "inside" and "outside" are based on the orientation or positional relationship of the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0095] The above disclosure is only a preferred embodiment of the present invention, and certainly cannot be used to limit the scope of rights of the present invention. Ordinary technicians in this field can understand that all or part of the processes of the above embodiment and equivalent changes made according to the claims of the present invention still fall within the scope covered by the present invention.

Claims

1. A transistor, characterized in that: include: A first P-type well layer includes a first surface, and a groove is formed inwardly from the first surface; A first N+ source layer is received in the groove, wherein the first N+ source layer includes a second surface facing the same direction as the first surface; The gate layer is disposed on the first surface and the second surface.

2. The transistor according to claim 1, characterized in that The gate layer includes a first gate layer and a second gate layer, and the first gate layer and the second gate layer are arranged at an interval.

3. The transistor according to claim 2, characterized in that A first spacing groove is formed between the first gate layer and the second gate layer. The transistor comprises a source metal layer, which is arranged on a side of the gate layer facing away from the first N+ source layer. At least a portion of the source metal layer extends into the first spacing groove.

4. The transistor according to claim 3, characterized in that The source metal layer extending into the spacing groove is connected to the second surface.

5. The transistor according to claim 3, characterized in that The first P-type well layer includes a P-type well layer 1 and a P-type well layer 2, the P-type well layer 1 and the P-type well layer 2 are arranged at intervals, the P-type well layer 1 forms a first sub-groove, and the P-type well layer 2 forms a second sub-groove, the first N+ source layer includes an N+ source layer 1 and an N+ source layer 2, the N+ source layer 1 is accommodated in the first sub-groove, and the N+ source layer 2 is accommodated in the second sub-groove, the first gate layer is arranged on the P-type well layer 1, and the second gate layer is arranged on the P-type well layer 2.

6. The transistor according to claim 5, characterized in that The transistor also includes a P+ type shielding layer, the first P type well layer is connected to the P+ type shielding layer, the first surface is facing away from the P+ type shielding layer, a second spacing groove is formed between the P type well layer 1 and the P type well layer 2, the first spacing groove and the second spacing groove are connected, at least a portion of the source metal layer extends into the second spacing groove and is connected to the P+ type shielding layer, or at least a portion of the P+ type shielding layer extends into the second spacing groove and is connected to the source metal layer.

7. The transistor according to claim 6, characterized in that The transistor also includes an N-type epitaxial layer and an N+ type extension layer, the N-type epitaxial layer includes an injection surface, and an injection groove is formed inward from the injection surface; the N+ type extension layer is connected to the inner wall of the injection groove; the first P-type well layer and the P+ type shielding layer are accommodated in the injection groove, and the P+ type shielding layer is connected to the side of the N+ type extension layer facing away from the N-type epitaxial layer.

8. The transistor according to claim 7, characterized in that The sum of the thicknesses of the P+ type shielding layer, the first N+ source layer and the first P type well layer is less than the depth of the implantation groove.

9. The transistor according to claim 6, characterized in that The width of the first P-type well layer is less than or equal to the width of the gate layer, and / or the width of the P+-type shielding layer is greater than or equal to the width of the gate layer.

10. An electrical device, characterized in that: The electrical device comprises the transistor as claimed in any one of claims 1-9.

Images