Gate drive circuit, array substrate and electronic equipment

Abstract

The utility model provides a gate drive circuit, an array substrate and electronic equipment. The circuit comprises a first output module and a first voltage stabilizing module. The first output module is electrically connected with a second node, the output end of the gate drive circuit and a first level line. The first voltage stabilizing module is electrically connected with the first level line and the output end of the gate drive circuit. The first output module is used for responding to a level signal of a second node and writing the level signal provided by the first level line into the output end of the gate drive circuit; and the first voltage stabilizing module is used for writing a level signal provided by the first level line into the output end of the gate driving circuit when the first voltage stabilizing module is switched to a conducting state. According to the embodiment, the first voltage stabilizing module can be used for intensifying the output of the level signal output by the gate driving circuit, display abnormity caused by abnormity of the level signal output by the gate driving circuit is avoided, and the purpose of improving the display reliability is achieved.

Description

Technical Field

[0001] The present disclosure relates to the display field, and in particular to a gate driving circuit, an array substrate and an electronic device. Background Art

[0002] The existing gate driver on array (GOA) outputs a scanning signal for each row in a row scanning manner, so as to display an image in a scanning manner in a certain direction (eg, from top to bottom).

[0003] Under high temperature conditions, the threshold voltage of the switching device in the GOA circuit will shift, causing the GOA to output abnormal scanning signals, which in turn causes display abnormalities. Utility Model Content

[0004] The present disclosure provides a gate driving circuit, an array substrate and an electronic device to solve the above technical problems.

[0005] According to a first aspect of the present disclosure, there is provided a gate driving circuit, comprising: a first output module and a first voltage stabilizing module; the first output module is electrically connected to a second node, an output end of the gate driving circuit and a first level line respectively; the first voltage stabilizing module is electrically connected to the first level line and the output end of the gate driving circuit respectively;

[0006] The first output module is used for writing the level signal provided by the first level line into the output end of the gate driving circuit in response to the level signal of the second node;

[0007] The first voltage stabilizing module is used for writing the level signal provided by the first level line into the output end of the gate driving circuit when switching to the on state.

[0008] Optionally, the first voltage stabilizing module includes a first switching device; a first end of the first switching device is electrically connected to the output end, a second end of the first switching device is electrically connected to the first level line, and a control end of the first switching device is electrically connected to a clock control line.

[0009] Optionally, the first output module includes a second switching device; a first end of the second switching device is electrically connected to the output end, a second end of the second switching device is electrically connected to the first level line, and a control end of the second switching device is electrically connected to a second node.

[0010] Optionally, it further includes a second output module; the second output module is electrically connected to the seventh node, the second level line and the output end of the gate driving circuit respectively;

[0011] The second output module is used for writing the level signal provided by the second level line into the output end of the gate driving circuit in response to the level signal of the seventh node.

[0012] Optionally, the second output module includes a third switching device and a first capacitor; the first end of the third switching device is electrically connected to the second level line, the second end of the third switching device is electrically connected to the output end of the gate drive circuit, and the control end of the third switching device is electrically connected to the seventh node; the first end of the first capacitor is electrically connected to the seventh node, and the second end of the first capacitor is electrically connected to the second level line.

[0013] Optionally, a clock control module is included, and the clock control module is respectively connected to the clock control line, the second level line, the sixth node and the seventh node;

[0014] The clock control module is used to connect or disconnect the electrical connection between the sixth node and the seventh node in response to the level signal of the clock control line and the level signal of the second level line.

[0015] Optionally, the clock control module includes a fourth switch device;

[0016] A first terminal of the fourth switch device is electrically connected to the sixth node, a second terminal of the fourth switch device is electrically connected to the seventh node, and a control terminal of the fourth switch device is electrically connected to the clock control line.

[0017] Optionally, it further comprises: a first writing module; the first writing module is electrically connected to the second level line, the sixth node and the first node respectively;

[0018] The first writing module is used for writing the level signal of the second level line into the sixth node in response to the level signal of the first node.

[0019] Optionally, the first writing module includes a sixth switching device; a first end of the sixth switching device is electrically connected to the sixth node, a second end of the sixth switching device is electrically connected to the second level line, and a control end of the sixth switching device is electrically connected to the first node.

[0020] Optionally, it further comprises: a first path switch module; the first path switch module is electrically connected to the fourth node, the sixth node and the first clock line respectively;

[0021] The first path switch module is used for writing the level signal of the first clock line into the sixth node in response to the level signal of the fourth node.

[0022] Optionally, the first path switch module includes an eighth switch device, a seventh switch device and a second capacitor;

[0023] The first end of the eighth switch device is electrically connected to the fifth node, the second end of the eighth switch device is electrically connected to the first clock line, and the control end of the eighth switch device is electrically connected to the fourth node;

[0024] A first terminal of the seventh switch device is electrically connected to the fifth node, a second terminal of the seventh switch device is electrically connected to the sixth node, and a control terminal of the seventh switch device is electrically connected to the first clock line;

[0025] A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node.

[0026] Optionally, it further comprises: a second writing module; the second writing module is electrically connected to the first node, the third node and the second clock line respectively;

[0027] The second writing module is used for writing the level signal of the second clock line into the third node in response to the level signal of the first node.

[0028] Optionally, the second writing module includes a ninth switching device; a first end of the ninth switching device is electrically connected to the third node, a second end of the ninth switching device is electrically connected to the second clock line, and a control end of the ninth switching device is electrically connected to the first node.

[0029] Optionally, it further comprises: a third writing module; the third writing module is electrically connected to the first level line, the third node and the second clock line respectively;

[0030] The third writing module is used for writing the level signal of the first level line into the third node in response to the level signal of the second clock line.

[0031] Optionally, the third writing module includes a tenth switching device; a first end of the tenth switching device is electrically connected to the first level line, a second end of the tenth switching device is electrically connected to the third node, and a control end of the tenth switching device is electrically connected to the second clock line.

[0032] Optionally, it further comprises: a second path switch module; the second path switch module is electrically connected to the first level line, the third node and the fourth node respectively;

[0033] The second path switch module is used for electrically connecting the third node and the fourth node in response to the level signal of the first level line.

[0034] Optionally, the second path switch module includes a fifteenth switch device; a first end of the fifteenth switch device is electrically connected to the third node, a second end of the fifteenth switch device is electrically connected to the fourth node, and a control end of the fifteenth switch device is electrically connected to the first level line.

[0035] Optionally, it further comprises: a third path switch module; the third path switch module is electrically connected to the third node, the second node, the eighth node, the second level line and the first clock line respectively;

[0036] The third path switch module is used for writing the level signal of the eighth node into the second node in response to the level signals of the third node and the eighth node.

[0037] Optionally, the third path switch module includes a third capacitor, an eleventh switch device, a twelfth switch device and a thirteenth switch device;

[0038] The first end of the eleventh switch device is electrically connected to the first clock line, the second end of the eleventh switch device is electrically connected to the first end of the third capacitor, and the control end of the eleventh switch device is electrically connected to the second end of the third capacitor;

[0039] The first end of the twelfth switch device is electrically connected to the first level line, the second end of the twelfth switch device is electrically connected to the first end of the third capacitor, and the control end of the twelfth switch device is electrically connected to the third node;

[0040] The first end of the thirteenth switch device is electrically connected to the second end of the third capacitor and the eighth node respectively, the second end of the thirteenth switch device is electrically connected to the second node, and the control end of the thirteenth switch device is electrically connected to the second end of the third capacitor.

[0041] Optionally, it further includes: a fourth writing module; the fourth writing module is electrically connected to the second clock line, the first level line, the trigger signal line and the eighth node respectively;

[0042] The fourth writing module is used for writing the level signal of the trigger signal line into the eighth node in response to the level signals of the second clock line and the first level line.

[0043] Optionally, the fourth writing module includes a fourteenth switching device and a sixteenth switching device;

[0044] The first end of the fourteenth switch device is electrically connected to the trigger signal line, the second end of the fourteenth switch device is electrically connected to the first end of the sixteenth switch device, and the control end of the fourteenth switch device is electrically connected to the second clock line;

[0045] A second terminal of the sixteenth switch device is electrically connected to the eighth node, and a control terminal of the sixteenth switch device is electrically connected to the first level line.

[0046] Optionally, it further comprises: a fifth writing module; the fifth writing module is electrically connected to the first node, the second node and the first level line respectively;

[0047] The fifth writing module is used for writing the level signal of the first node into the second node in response to the level signal of the first level line.

[0048] Optionally, the fifth writing module includes a seventeenth switching device; the first end of the seventeenth switching device is electrically connected to the first node, the second end of the seventeenth switching device is electrically connected to the second node, and the control end of the seventeenth switching device is electrically connected to the first level line.

[0049] Optionally, it further comprises: a sixth writing module; the sixth writing module is electrically connected to the first node, the trigger signal line and the second clock signal line respectively;

[0050] The sixth writing module is used for writing the level signal of the trigger signal line into the first node in response to the level signal of the second clock signal line.

[0051] Optionally, the sixth writing module includes an eighteenth switching device; the first end of the eighteenth switching device is electrically connected to the trigger signal line, the second end of the eighteenth switching device is electrically connected to the first node, and the control end of the eighteenth switching device is electrically connected to the second clock signal line.

[0052] According to a second aspect of the present disclosure, an array substrate is provided, comprising a silicon substrate and a plurality of gate driving circuits as described in any one of the first aspects arranged on the silicon substrate; the driving output end of each stage of the gate driving circuit is electrically connected to the input end of the first input module of the next stage of the gate driving circuit.

[0053] According to a third aspect of the present disclosure, an electronic device is provided, comprising the array substrate as described in the second aspect, a plurality of rows of pixels and a data driving circuit;

[0054] Each pixel of the array substrate is electrically connected to the data driving circuit through a data signal line; each pixel of the array substrate is electrically connected to the gate driving circuit through a scanning signal line.

[0055] The technical solution provided by the embodiments of the present disclosure may have the following beneficial effects:

[0056] In this embodiment, the gate driving circuit includes a first output module and a first voltage stabilizing module; the first output module is electrically connected to the second node, the output end of the gate driving circuit and the first level line respectively; the first voltage stabilizing module is electrically connected to the first level line and the output end of the gate driving circuit respectively; the first output module is used to write the level signal provided by the first level line to the output end of the gate driving circuit in response to the level signal of the second node; the first voltage stabilizing module is used to write the level signal provided by the first level line to the output end of the gate driving circuit when switching to the on state. In this way, this embodiment can use the first voltage stabilizing module to strengthen the level signal (of the first level line) output by the first output module, avoid abnormal display caused by abnormal level signal output by the gate driving circuit, and achieve the purpose of improving display reliability.

[0057] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 The block diagram is a gate driving circuit according to an embodiment of the present disclosure.

[0059] Figure 2 to Figure 13 The present invention is a circuit diagram of a gate driving circuit according to an embodiment of the present invention.

[0060] Fig.14 This is a timing diagram of a gate driving circuit according to an embodiment of the present disclosure.

[0061] Fig.15 FIG. 4 is a circuit diagram of another gate driving circuit according to an embodiment of the present disclosure.

[0062] Fig.16 for Fig.15 The timing diagram of the gate driving circuit in stages S1 to S9 is shown. DETAILED DESCRIPTION

[0063] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. Instead, they are merely examples of devices consistent with some aspects of the present disclosure as detailed in the appended claims.

[0064] The present disclosure provides an electronic device, which may include but is not limited to mobile phones, computers, tablets, e-books, watches, stereoscopic display screens, integrated conference machines, electronic whiteboards and other devices with display functions. The electronic device includes an array substrate, a plurality of rows of pixels arranged on the array substrate, and a data driving circuit; each pixel of the array substrate is electrically connected to the data driving circuit through a data line; each pixel of the array substrate is electrically connected to the gate driving circuit through a scanning line. In this way, the gate driving circuit can scan the pixels in the direction of rows or columns, and the data driving circuit writes the pixel data into the corresponding pixels to achieve the effect of displaying an image.

[0065] The present disclosure provides a gate drive circuit suitable for the above electronic device. Figure 1 FIG. 1 is a block diagram of a gate driving circuit according to an embodiment of the present disclosure. Figure 1 The gate driving circuit 10 includes: a first output module 11 and a first voltage stabilizing module 12. The first output module 11 is electrically connected to the second node N2, the output terminal Out of the gate driving circuit 10 and the first level line VGL respectively; the first voltage stabilizing module 12 is electrically connected to the first level line VGL and the output terminal Out of the gate driving circuit 10 respectively.

[0066] The first output module 11 is used for writing the level signal provided by the first level line VGL into the output terminal Out of the gate driving circuit in response to the level signal of the second node N2.

[0067] The first voltage stabilizing module 12 is used for writing the level signal provided by the first level line VGL into the output terminal Out of the gate driving circuit 10 when switched to the on state.

[0068] In one embodiment, see Figure 2 The first voltage stabilizing module 12 includes a first switch device M1. A first end of the first switch device M1 is electrically connected to the output end Out of the gate driving circuit 10, a second end of the first switch device M1 is electrically connected to the first level line VGL, and a control end of the first switch device M1 is electrically connected to the clock control line Control.

[0069] It should be noted that the first switch device M1 can be implemented by an N-type MOS tube or a P-type MOS tube, and similarly, the switch devices of other subsequent modules can be implemented by an N-type MOS tube or a P-type MOS tube. In one example, the first switch device M1 is implemented by a P-type MOS tube, and the switch devices of other subsequent modules are also implemented by a P-type MOS tube to facilitate the description of the scheme, but it does not constitute a limitation on the scheme of the present disclosure.

[0070] The working principle of the first voltage stabilizing module 12 is as follows: when the level signal of the clock control line Control is a low level signal, the first switch device M1 switches to the on state, and at this time, the level signal of the first level line VGL can be written into the output terminal Out of the gate drive circuit 10, that is, the output terminal Out of the gate drive circuit 10 can output a low level signal. When the level signal of the clock control line Control is a high level signal, the first switch device M1 switches to the off state, and at this time, the level signal of the first level line VGL cannot be written into the output terminal Out of the gate drive circuit 10.

[0071] In one embodiment, see Figure 2 , the first output module 11 includes a second switch device M2. The first end of the second switch device M2 is electrically connected to the output terminal Out of the gate drive circuit 10, the second end of the second switch device M2 is electrically connected to the first level line VGL, and the control end of the second switch device M2 is electrically connected to the second node N2. In this way, when the level signal at the second node N2 is a low level signal, the second switch device M2 is switched to the on state, at which time the level signal of the first level line VGL can be written into the output terminal Out of the gate drive circuit 10; when the level signal at the second node N2 is a high level signal, the second switch device M2 is switched to the off state, at which time the level signal of the first level line VGL cannot be written into the output terminal Out of the gate drive circuit 10.

[0072] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a second output module 13. The second output module 13 is electrically connected to the seventh node N7, the second level line VGH and the output terminal Out of the gate driving circuit 10 respectively. The second output module 13 is used to write the level signal provided by the second level line VGH to the output terminal Out of the gate driving circuit 10 in response to the level signal of the seventh node N7.

[0073] In one embodiment, see Figure 3, the second output module 13 includes a third switch device M3 and a first capacitor C1. The first end of the third switch device M3 is electrically connected to the second level line VGH, the second end of the third switch device M3 is electrically connected to the output end Out of the gate drive circuit 10, and the control end of the third switch device M3 is electrically connected to the seventh node N7; the first end of the first capacitor C1 is electrically connected to the seventh node N7, and the second end of the first capacitor C1 is electrically connected to the second level line VGH. In this way, when the level signal at the second node N7 is a low level signal, the third switch device M3 switches to the on state, and the level signal of the second level line VGH can be written into the output end Out of the gate drive circuit 10, that is, the output end Out of the gate drive circuit 10 outputs a high level signal; when the level signal at the second node N7 is a high level signal, the third switch device M3 switches to the off state, and the level signal of the second level line VGH cannot be written into the output end Out of the gate drive circuit 10.

[0074] It should be noted that the first capacitor C1 can maintain the level signal at the seventh node N7, so that the third switch device M3 remains in the on state or the off state.

[0075] It should also be noted that the first output module 11 and the second output module 13 cooperate with each other to achieve the effect that the output terminal Out of the gate driving circuit 10 outputs a high level signal or a low level signal.

[0076] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a clock control module 14. The clock control module 14 is respectively connected to the clock control line Control, the second level line VGH, the sixth node N6 and the seventh node N7. The clock control module 14 is used to connect or disconnect the electrical connection between the sixth node N6 and the seventh node N7 in response to the level signal of the clock control line Control and the level signal of the second level line VGH.

[0077] In one embodiment, see Figure 4 , the clock control module 14 includes a fourth switch device M4. The first end of the fourth switch device M4 is electrically connected to the sixth node N6, the second end of the fourth switch device M4 is electrically connected to the seventh node N7, and the control end of the fourth switch device M4 is electrically connected to the clock control line Control. In this embodiment, the fourth switch device M4 is implemented by an N-type MOS tube. In this way, when the clock control line Control provides a high-level signal, the fourth switch device M4 switches to a conducting state, and the sixth node N6 and the seventh node N7 switch to a connected state. When the clock control line Control provides a low-level signal, the fourth switch device M4 switches to a disconnected state, and the sixth node N6 and the seventh node N7 switch to a disconnected state.

[0078] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a first writing module 15; the first writing module 15 is electrically connected to the second level line VGH, the sixth node N6 and the first node N1 respectively. The first writing module 15 is used to write the level signal of the second level line VGH into the sixth node N6 in response to the level signal of the first node N1.

[0079] In one embodiment, see Figure 5 , the first writing module 15 includes a sixth switch device M6. A first end of the sixth switch device M6 is electrically connected to the sixth node N6, a second end of the sixth switch device M6 is electrically connected to the second level line VGH, and a control end of the sixth switch device M6 is electrically connected to the first node N1. When the level signal at the first node N1 is a low level signal, the sixth switch device M6 switches to a conducting state, and a high level signal of the second level line VGH can be written to the sixth node N6; when the level signal at the first node N1 is a high level signal, the sixth switch device M6 switches to a disconnected state, and the high level signal of the second level line VGH cannot be written to the sixth node N6.

[0080] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a first path switch module 16. The first path switch module 16 is electrically connected to the fourth node N4, the sixth node N6 and the first clock line XCK respectively. The first path switch module 16 is used to write the level signal of the first clock line XCK into the sixth node N6 in response to the level signal of the fourth node N6.

[0081] In one embodiment, see Figure 6 The first path switch module 16 includes an eighth switch device M8, a seventh switch device M7 and a second capacitor C2. A first end of the eighth switch device M8 is electrically connected to the fifth node N5, a second end of the eighth switch device M8 is electrically connected to the first clock line XCK, and a control end of the eighth switch device M8 is electrically connected to the fourth node N4. A first end of the seventh switch device M7 is electrically connected to the fifth node N5, a second end of the seventh switch device N7 is electrically connected to the sixth node N6, and a control end of the seventh switch device M7 is electrically connected to the first clock line XCK; a first end of the second capacitor C2 is electrically connected to the fourth node N4, and a second end of the second capacitor C2 is electrically connected to the fifth node N5.

[0082] When the level signal at the fourth node N4 is a low level signal, the eighth switch device M8 switches to the on state, and the level signal of the first clock line XCK can be written to the fifth node N5. When the level signal at the fourth node N4 is a high level signal, the eighth switch device M8 switches to the off state, and the level signal of the first clock line XCK cannot be written to the fifth node N5.

[0083] When the level signal of the first clock line XCK is a low level signal, the seventh switch device M7 switches to the on state, and the level signal of the fifth node N5 can be output to the sixth node N6. When the level signal of the first clock line XCK is a high level signal, the seventh switch device M7 switches to the off state, and the level signal of the fifth node N5 cannot be output to the sixth node N6.

[0084] It should be noted that the second node can maintain the level signal at the fourth node N4, thereby controlling the eighth switching device M8 to maintain the on state or the off state.

[0085] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a second writing module 17. The second writing module 17 is electrically connected to the first node N1, the third node N3 and the second clock line CK respectively. The second writing module 17 is used to write the level signal of the second clock line CK into the third node N3 in response to the level signal of the first node N1.

[0086] In one embodiment, see Figure 7 , the second writing module 17 includes a ninth switch device M9; a first end of the ninth switch device M9 is electrically connected to the third node N3, a second end of the ninth switch device M9 is electrically connected to the second clock line CK, and a control end of the ninth switch device M9 is electrically connected to the first node N1. When the level signal at the first node N1 is a low level signal, the ninth switch device M9 switches to a conducting state, and the level signal of the second clock line CK can be written to the third node N3; when the level signal at the first node N1 is a high level signal, the ninth switch device M9 switches to a disconnected state, and the level signal of the second clock line CK cannot be written to the third node N3.

[0087] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a second path switch module 18. The second path switch module 18 is electrically connected to the first level line VGL, the third node N3 and the fourth node N4 respectively. The second path switch module 18 is used to electrically connect the third node N3 and the fourth node N4 in response to the level signal of the first level line VGL.

[0088] In one embodiment, see Figure 8 , the second path switch module 18 includes a fifteenth switch device M15; a first end of the fifteenth switch device M15 is electrically connected to the third node N3, a second end of the fifteenth switch device M15 is electrically connected to the fourth node N4, and a control end of the fifteenth switch device M15 is electrically connected to the first level line VGL. Since the first level line VGL provides a low level signal, the fifteenth switch device M15 remains in a conducting state, thereby writing the level signal of the third node N3 into the fourth node N4.

[0089] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a third writing module 19. The third writing module 19 is electrically connected to the first level line VGL, the third node N3 and the second clock line CK respectively. The third writing module 19 is used to write the level signal of the first level VGL into the third node N3 in response to the level signal of the second clock line CK.

[0090] In one embodiment, see Fig. 9 , the third writing module 19 includes a tenth switch device M10; a first end of the tenth switch device M10 is electrically connected to the first level line VGL, a second end of the tenth switch device M10 is electrically connected to the third node N3, and a control end of the tenth switch device M10 is electrically connected to the second clock line CK. When the second clock line CK provides a low-level signal, the tenth switch device M10 switches to a conducting state, and the low-level signal of the first level line VGL can be written into the third node N3. When the second clock line CK provides a high-level signal, the tenth switch device M10 switches to a disconnected state, and the low-level signal of the first level line VGL cannot be written into the third node N3.

[0091] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a third path switch module 20. The third path switch module 20 is electrically connected to the third node N3, the second node N2, the eighth node N8, the second level line VGH and the first clock line XCK respectively; the third path switch module 20 is used to write the level signal of the eighth node N8 into the second node N2 in response to the level signals of the third node N3 and the eighth node N8.

[0092] In one embodiment, see Fig.10 The third path switch module 20 includes a third capacitor C3, an eleventh switch device M11, a twelfth switch device M12 and a thirteenth switch device M14. A first end of the eleventh switch device M11 is electrically connected to the first clock line XCK, a second end of the eleventh switch device M11 is electrically connected to a first end of the third capacitor C3, and a control end of the eleventh switch device M11 is electrically connected to a second end of the third capacitor C3; a first end of the twelfth switch device M12 is electrically connected to a first level line VGL, a second end of the twelfth switch device M12 is electrically connected to a first end of the third capacitor C3, and a control end of the twelfth switch device M12 is electrically connected to a third node N3; a first end of the thirteenth switch device M13 is electrically connected to a second end of the third capacitor C3 and an eighth node N8, respectively, a second end of the thirteenth switch device M13 is electrically connected to a second node N2, and a control end of the thirteenth switch device M13 is electrically connected to a second end of the third capacitor C3.

[0093] When the level signal at the third node N3 is a low level signal, the twelfth switch device M12 switches to the on state, and the high level signal of the second level line VGH can be written into the third capacitor and the eighth node, and the thirteenth switch device M13 switches to the off state; when the level signal at the third node N3 is a high level signal, the twelfth switch device M12 switches to the off state, and the high level signal of the second level line VGH cannot be written into the third capacitor.

[0094] When the level signal at the eighth node N8 is a low level signal, the eleventh switch device M11 switches to the on state, and the level signal of the first clock line XCK can be written into the third capacitor C3 and the eighth node N8. At this time, the thirteenth switch device M13 switches to the on state, and the level signal at the eighth node N8 can be output to the second node N2.

[0095] In one embodiment, see Figure 1 The gate driving circuit 10 further includes a fourth writing module 21. The fourth writing module 21 is electrically connected to the second clock line CK, the first level line VGL, the trigger signal line STV and the eighth node N8 respectively; the fourth writing module 21 is used to write the level signal of the trigger signal line STV into the eighth node N8 in response to the level signals of the second clock line CK and the first level line VGL.

[0096] In one embodiment, see Fig.11 , the fourth writing module 21 includes a fourteenth switch device M14 and a sixteenth switch device M16. The first end of the fourteenth switch device M14 is electrically connected to the trigger signal line STV, the second end of the fourteenth switch device M14 is electrically connected to the first end of the sixteenth switch device M16, and the control end of the fourteenth switch device M14 is electrically connected to the second clock line CK; the second end of the sixteenth switch device M16 is electrically connected to the eighth node N8, and the control end of the sixteenth switch device M16 is electrically connected to the first level line VGL. When the second clock line CK provides a low level signal, the fourteenth switch device M14 switches to the on state and outputs the level signal of the trigger signal line STV to the sixteenth switch device M16; when the second clock line CK provides a high level signal, the fourteenth switch device M14 switches to the off state and cannot output the level signal of the trigger signal line STV to the sixteenth switch device M16. The first level line VGL provides a low level signal, and the sixteenth switch device M16 remains in the on state.

[0097] In one embodiment, see Figure 1The gate driving circuit 10 further includes a fifth writing module 22. The fifth writing module 22 is electrically connected to the first node N1, the second node N2 and the first level line VGL respectively; the fifth writing module 22 is used to write the level signal of the first node N1 into the second node N2 in response to the level signal of the first level line VGL.

[0098] In one embodiment, see Fig.12 , the fifth writing module 22 includes a seventeenth switch device M17. A first end of the seventeenth switch device M17 is electrically connected to the first node N1, a second end of the seventeenth switch device M17 is electrically connected to the second node N2, and a control end of the seventeenth switch device M17 is electrically connected to the first level line VGL. The first level line VGL provides a low level signal, at which time the seventeenth switch device M17 remains in a conducting state, that is, the level signal of the first node N1 is written to the second node N2.

[0099] In one embodiment, see Figure 1 The gate driving circuit 10 also includes a sixth writing module 23; the sixth writing module 23 is electrically connected to the first node N1, the trigger signal line STV and the second clock signal line CK respectively; the sixth writing module 23 is used to write the level signal of the trigger signal line STV into the first node N1 in response to the level signal of the second clock signal line CK.

[0100] In one embodiment, see Fig.13 , the sixth writing module 23 includes an eighteenth switch device M18; a first end of the eighteenth switch device M18 is electrically connected to the trigger signal line STV, a second end of the eighteenth switch device M18 is electrically connected to the first node N1, and a control end of the eighteenth switch device M18 is electrically connected to the second clock signal line CK. When the second clock signal line CK provides a low-level signal, the tenth switch device M18 switches to a conducting state, and the level signal provided by the trigger signal line STV can be written into the first node N1. When the second clock signal line CK provides a high-level signal, the tenth switch device M18 switches to a disconnected state, and the level signal provided by the trigger signal line STV cannot be written into the first node N1.

[0101] In one embodiment, see Figure 1 and Fig.13 The gate driving circuit 10 further includes a reset module. The reset module includes a nineteenth switch device M19. When the control terminal of the nineteenth switch device M19 receives the reset signal RST, it switches to a conducting state and can write a high level signal provided by the second level line VGH into the first node N1.

[0102] Combined with the above Figures 1 to 13 The gate drive circuit 10 shown, and Fig.14 The timing diagram shown in the figure analyzes the working process of the gate drive circuit, including:

[0103] In the first stage T1, the level signals of the first clock signal line XCK and the second clock signal line CK are refreshed at a set frequency. At this time, the clock control line Control provides a high level signal, and the first switch device M1 switches to the off state and the fourth switch device M4 switches to the on state. The equivalent circuit is as follows: Fig.15 shown.

[0104] See also Fig.15 At this time, the gate drive circuit is equivalent to a 16T3C GOA circuit, and its control timing is as follows Fig.16 As shown, it includes stages S1 to S9.

[0105] In the S1 phase, the trigger control line STV provides a low-level signal, the second clock line CK provides a high-level signal, and the first clock line XCK provides a high-level signal. At this time, the third switch device M3, the seventh switch device M7, the tenth switch device M10, the fourteenth switch device M14, and the eighteenth switch device M18 are switched to the off state, and the other switch devices are switched to the on state. At this time, the gate drive circuit outputs a low-level signal. For the convenience of description, the subsequent signal lines and switch devices are only represented by reference numerals.

[0106] In the S2 stage, STV, CK and XCK provide high level, low level and high level signals respectively. At this time, M2, M3, M6, M7, M9 and M11 are switched to the off state, and other switching devices are switched to the on state. At this time, the gate drive circuit outputs a low level signal.

[0107] In the S3 stage, STV, CK and XCK provide high level, high level and low level signals respectively. At this time, M2, M6, M9, M10, M11, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. The fifth node N5 is a low level signal, and the seventh node N7 is a low level signal. At this time, the gate drive circuit outputs a high level signal.

[0108] In the S4 stage, STV, CK and XCK provide high level, high level and high level signals respectively. At this time, M2, M6, M7, M9, M10, M11, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. There is no current path at the second node N2 and the seventh node N7. At this time, the gate drive circuit outputs a high level signal.

[0109] In the S5 stage, STV, CK and XCK provide low level, high level and low level signals respectively. At this time, M2, M6, M9, M10, M11, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. The second node N2 has no current path and maintains a high level signal. The seventh node N7 is a low level signal. At this time, the gate drive circuit outputs a high level signal.

[0110] In the S6 stage, STV, CK and XCK provide low level, high level and high level signals respectively. At this time, M2, M6, M7, M9, M10, M11, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. The fifth node N5 is a high level signal, and there is a circuit path at the seventh node N7. At this time, the gate drive circuit outputs a high level signal.

[0111] In the S7 stage, STV, CK and XCK provide low level, low level and high level signals respectively. At this time, M3 and M7 are switched to the off state, and other switching devices are switched to the on state. A high level signal is written by M6 at the seventh node N7. At this time, the gate drive circuit outputs a high level signal (VGL-Vth), that is, Fig.16 An intermediate level signal is shown as an example.

[0112] In the S8 stage, STV, CK and XCK provide low level, high level and high level signals respectively. At this time, M3, M7, M8, M10, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. The second node N2 and the seventh node N7 maintain the level signal. At this time, the gate drive circuit outputs a high level signal (VGL-Vth), that is, Fig.16 An intermediate level signal is shown as an example.

[0113] In the S9 stage, STV, CK and XCK provide low level, high level and low level signals respectively. At this time, M3, M8, M10, M14 and M18 are switched to the off state, and other switching devices are switched to the on state. The second node N2 is coupled by the third capacitor C3 and pulled down to a low level. At this time, the gate drive circuit outputs a low level signal VGL.

[0114] In the second stage T2, the clock control line Control provides a low-level signal. In this stage, the seventh node N7 has no current path, M3 switches to the disconnected state, and M1 switches to the on state, which can increase the pull-down capability of M2, so that the gate drive circuit 10 outputs a low-level signal, avoiding the problem that the temperature affects the threshold voltage of the second switch device M2 and the output of the pin is unstable, and ensuring reliable display. At this time, the first clock line XCK and the second clock line CK both provide a high level, and there is no need to provide a clock signal with high and low changes, which can reduce the scanning frequency of the gate drive circuit and reduce the power consumption of the GOA circuit.

[0115] The present disclosure also provides an array substrate, including a silicon substrate, a plurality of layers arranged on the silicon substrate, Figures 1 to 16 The gate drive circuit; the drive output end of each level of the gate drive circuit is electrically connected to the input end of the first input module of the next level of the gate drive circuit.

[0116] An embodiment of the present disclosure also provides an electronic device, comprising the above-mentioned array substrate, a plurality of pixels and a data driving circuit; each pixel of the array substrate is electrically connected to the data driving circuit through a data line; each pixel of the array substrate is electrically connected to the gate driving circuit through a scanning line.

[0117] The terms used in this disclosure are only for the purpose of describing specific embodiments and are not intended to limit the disclosure. Unless otherwise defined, the technical terms or scientific terms used in this disclosure should be understood by people with ordinary skills in the field to which the disclosure belongs. Similar words such as "one" or "one" used in this disclosure specification and claims do not indicate a quantitative limitation, but indicate that there is at least one. "Multiple" means at least two. Similar words such as "include" or "include" mean that the elements or objects appearing in front of "include" or "include" include the elements or objects listed after "include" or "include" and their equivalents, and do not exclude other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, and can include electrical connections, whether direct or indirect. The singular forms of "one", "said" and "the" used in this disclosure specification and the attached claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0118] As for the method embodiment, since it basically corresponds to the device embodiment, the relevant parts can be referred to the partial description of the device embodiment. The method embodiment and the device embodiment complement each other.

[0119] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A gate drive circuit, characterized in that: include: A first output module and a first voltage stabilizing module; The first output module is electrically connected to the second node, the output end of the gate driving circuit and the first level line respectively; The first voltage stabilizing module is electrically connected to the first level line and the output end of the gate driving circuit respectively; The first output module is used for writing the level signal provided by the first level line into the output end of the gate driving circuit in response to the level signal of the second node; The first voltage stabilizing module is used for writing the level signal provided by the first level line into the output end of the gate driving circuit when switching to the on state.

2. The gate driving circuit according to claim 1, characterized in that: The first voltage stabilizing module includes a first switch device; a first end of the first switch device is electrically connected to the output end, a second end of the first switch device is electrically connected to the first level line, and a control end of the first switch device is electrically connected to a clock control line.

3. The gate driving circuit according to claim 1, characterized in that: The first output module includes a second switch device; a first end of the second switch device is electrically connected to the output end, a second end of the second switch device is electrically connected to the first level line, and a control end of the second switch device is electrically connected to a second node.

4. The gate driving circuit according to claim 1, characterized in that: It also includes a second output module; the second output module is electrically connected to the seventh node, the second level line and the output end of the gate driving circuit respectively; The second output module is used for writing the level signal provided by the second level line into the output end of the gate driving circuit in response to the level signal of the seventh node.

5. The gate driving circuit according to claim 4, characterized in that: The second output module includes a third switching device and a first capacitor; the first end of the third switching device is electrically connected to the second level line, the second end of the third switching device is electrically connected to the output end of the gate drive circuit, and the control end of the third switching device is electrically connected to the seventh node; the first end of the first capacitor is electrically connected to the seventh node, and the second end of the first capacitor is electrically connected to the second level line.

6. The gate driving circuit according to claim 4, characterized in that: Also includes: A clock control module, wherein the clock control module is respectively connected to the clock control line, the second level line, the sixth node and the seventh node; The clock control module is used to connect or disconnect the electrical connection between the sixth node and the seventh node in response to the level signal of the clock control line and the level signal of the second level line.

7. The gate driving circuit according to claim 6, characterized in that: The clock control module includes a fourth switch device; A first terminal of the fourth switch device is electrically connected to the sixth node, a second terminal of the fourth switch device is electrically connected to the seventh node, and a control terminal of the fourth switch device is electrically connected to the clock control line.

8. The gate driving circuit according to claim 1, characterized in that: Also includes: A first writing module; the first writing module is electrically connected to the second level line, the sixth node and the first node respectively; The first writing module is used for writing the level signal of the second level line into the sixth node in response to the level signal of the first node.

9. The gate driving circuit according to claim 8, characterized in that: The first writing module includes a sixth switch device; a first end of the sixth switch device is electrically connected to the sixth node, a second end of the sixth switch device is electrically connected to the second level line, and a control end of the sixth switch device is electrically connected to the first node.

10. The gate driving circuit according to claim 1, characterized in that: Also includes: A first path switch module; The first path switch module is electrically connected to the fourth node, the sixth node and the first clock line respectively; The first path switch module is used for writing the level signal of the first clock line into the sixth node in response to the level signal of the fourth node.

11. The gate driving circuit according to claim 10, characterized in that: The first path switch module includes an eighth switch device, a seventh switch device and a second capacitor; The first end of the eighth switch device is electrically connected to the fifth node, the second end of the eighth switch device is electrically connected to the first clock line, and the control end of the eighth switch device is electrically connected to the fourth node; A first terminal of the seventh switch device is electrically connected to the fifth node, a second terminal of the seventh switch device is electrically connected to the sixth node, and a control terminal of the seventh switch device is electrically connected to the first clock line; A first end of the second capacitor is electrically connected to the fourth node, and a second end of the second capacitor is electrically connected to the fifth node.

12. The gate driving circuit according to claim 1, characterized in that: Also includes: The second writing module; The second writing module is electrically connected to the first node, the third node and the second clock line respectively; The second writing module is used for writing the level signal of the second clock line into the third node in response to the level signal of the first node.

13. The gate driving circuit according to claim 12, characterized in that: The second writing module includes a ninth switch device; a first end of the ninth switch device is electrically connected to the third node, a second end of the ninth switch device is electrically connected to the second clock line, and a control end of the ninth switch device is electrically connected to the first node.

14. The gate driving circuit according to claim 1, characterized in that: It also includes: a third writing module; the third writing module is electrically connected to the first level line, the third node and the second clock line respectively; The third writing module is used for writing the level signal of the first level line into the third node in response to the level signal of the second clock line.

15. The gate driving circuit according to claim 14, characterized in that: The third writing module includes a tenth switch device; a first end of the tenth switch device is electrically connected to the first level line, a second end of the tenth switch device is electrically connected to the third node, and a control end of the tenth switch device is electrically connected to the second clock line.

16. The gate driving circuit according to claim 1, characterized in that: Also includes: A second path switch module; The second path switch module is electrically connected to the first level line, the third node and the fourth node respectively; The second path switch module is used for electrically connecting the third node and the fourth node in response to the level signal of the first level line.

17. The gate driving circuit according to claim 16, characterized in that: The second path switch module includes a fifteenth switch device; a first end of the fifteenth switch device is electrically connected to the third node, a second end of the fifteenth switch device is electrically connected to the fourth node, and a control end of the fifteenth switch device is electrically connected to the first level line.

18. The gate driving circuit according to claim 1, characterized in that: Also includes: A third channel switch module; The third path switch module is electrically connected to the third node, the second node, the eighth node, the second level line and the first clock line respectively; The third path switch module is used for writing the level signal of the eighth node into the second node in response to the level signals of the third node and the eighth node.

19. The gate driving circuit according to claim 18, characterized in that: The third path switch module includes a third capacitor, an eleventh switch device, a twelfth switch device and a thirteenth switch device; The first end of the eleventh switch device is electrically connected to the first clock line, the second end of the eleventh switch device is electrically connected to the first end of the third capacitor, and the control end of the eleventh switch device is electrically connected to the second end of the third capacitor; The first end of the twelfth switch device is electrically connected to the first level line, the second end of the twelfth switch device is electrically connected to the first end of the third capacitor, and the control end of the twelfth switch device is electrically connected to the third node; The first end of the thirteenth switch device is electrically connected to the second end of the third capacitor and the eighth node respectively, the second end of the thirteenth switch device is electrically connected to the second node, and the control end of the thirteenth switch device is electrically connected to the second end of the third capacitor.

20. The gate driving circuit according to claim 1, characterized in that: It also includes: a fourth writing module; the fourth writing module is electrically connected to the second clock line, the first level line, the trigger signal line and the eighth node respectively; The fourth writing module is used for writing the level signal of the trigger signal line into the eighth node in response to the level signals of the second clock line and the first level line.

21. The gate driving circuit according to claim 20, characterized in that: The fourth writing module includes a fourteenth switching device and a sixteenth switching device; The first end of the fourteenth switch device is electrically connected to the trigger signal line, the second end of the fourteenth switch device is electrically connected to the first end of the sixteenth switch device, and the control end of the fourteenth switch device is electrically connected to the second clock line; A second terminal of the sixteenth switch device is electrically connected to the eighth node, and a control terminal of the sixteenth switch device is electrically connected to the first level line.

22. The gate driving circuit according to claim 1, characterized in that: Also includes: The fifth writing module; The fifth writing module is electrically connected to the first node, the second node and the first level line respectively; The fifth writing module is used for writing the level signal of the first node into the second node in response to the level signal of the first level line.

23. The gate driving circuit according to claim 22, characterized in that: The fifth writing module includes a seventeenth switching device; a first end of the seventeenth switching device is electrically connected to the first node, a second end of the seventeenth switching device is electrically connected to the second node, and a control end of the seventeenth switching device is electrically connected to the first level line.

24. The gate driving circuit according to claim 1, characterized in that: Also includes: The sixth writing module; The sixth writing module is electrically connected to the first node, the trigger signal line and the second clock signal line respectively; The sixth writing module is used for writing the level signal of the trigger signal line into the first node in response to the level signal of the second clock signal line.

25. The gate driving circuit according to claim 24, characterized in that: The sixth writing module includes an eighteenth switching device; the first end of the eighteenth switching device is electrically connected to the trigger signal line, the second end of the eighteenth switching device is electrically connected to the first node, and the control end of the eighteenth switching device is electrically connected to the second clock signal line.

26. An array substrate, characterized in that: A gate drive circuit comprising a silicon substrate and a plurality of gate drive circuits as claimed in any one of claims 1 to 25 arranged on the silicon substrate; the drive output end of each gate drive circuit is electrically connected to the input end of the first input module of the next gate drive circuit.

27. An electronic device, characterized in that: The method comprises the array substrate according to claim 26, a plurality of rows of pixels and a data driving circuit; Each pixel of the array substrate is electrically connected to the data driving circuit through a data signal line; each pixel of the array substrate is electrically connected to the gate driving circuit through a scanning signal line.

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