Isolation driving circuit and dynamic test system of MOS (Metal Oxide Semiconductor)

Abstract

The utility model provides an MOS isolation driving circuit, comprising an optocoupler isolation driving circuit, a voltage stabilizing circuit and an MOS double-pulse test circuit, the voltage stabilizing circuit is connected with the optocoupler isolation driving circuit, the optocoupler isolation driving circuit is connected with the MOS double-pulse test circuit, and the MOS double-pulse test circuit is connected with an external bus voltage VCC; the optocoupler isolation driving circuit comprises a driving circuit, the first input end of the driving circuit is used for being connected with an external main control chip MCU and obtaining a PWM signal from the main control chip MCU, and the second input end of the driving circuit is connected with a voltage stabilizing circuit and used for achieving that the main control chip MCU controls voltage output of an optocoupler chip; one end of the push-pull circuit is connected with the drive circuit, the other end of the push-pull circuit is connected with the MOS double-pulse test circuit, and the push-pull circuit is used for being matched with the drive circuit to increase the drive capability of the circuit and improve the stability of the circuit.

Description

Technical Field

[0001] The utility model relates to the technical field of drive circuits, in particular to an isolation drive circuit of MOS and a dynamic test system. Background Art

[0002] MOSFET is a metal-oxide semiconductor field effect transistor, which is a field effect transistor that can be widely used in analog circuits and digital circuits. According to the polarity of its "channel" (working carrier), MOSFET can be divided into two types: "N-type" and "P-type", which are usually called NMOSFET and PMOSFET. MOSFET is usually used as a "switch" in system circuits, so evaluating the switching characteristics is very important for the application of MOSFET. Double pulse test is a test method widely used in the evaluation of the characteristics of power switching elements such as MOSFET and IGBT. This test can not only evaluate the switching characteristics of the target element, but also evaluate the reverse recovery characteristics of the fast recovery diode (FRD) used with the body diode and IGBT, which can simulate the actual working state of MOSFET on the client to a certain extent.

[0003] For the double pulse test of MOSFET, the components and circuit structure in the drive circuit directly affect the final MOSFET evaluation results. For the system, the control signal and the bus voltage of the MOSFET are two different voltage levels, so isolating different voltage levels can enhance the reliability of the system. Currently, most drive circuits with isolation requirements are optocoupler plus isolated power supply or transformer isolation.

[0004] In the patent with announcement number CN211089460U, MCU is used to directly drive optocoupler isolation and output gate drive signals, eliminating the isolation power supply. The optocoupler and IGBT collector are powered simultaneously through diodes and resistors. When the IGBT collector voltage fluctuates, the operation of the optocoupler device may be affected, affecting the stability of the system. Utility Model Content

[0005] In view of the deficiencies existing in the prior art, the utility model provides a MOS isolation driving circuit, which solves the above-mentioned problems existing in the prior art.

[0006] According to an embodiment of the utility model, a MOS isolation driving circuit includes:

[0007] An optocoupler isolation driving circuit, a voltage stabilizing circuit and a MOS double pulse testing circuit, wherein the voltage stabilizing circuit is connected to the optocoupler isolation driving circuit, the optocoupler isolation driving circuit is connected to the MOS double pulse testing circuit, and the MOS double pulse testing circuit is connected to an external bus voltage VCC;

[0008] The optical coupling isolation driving circuit comprises:

[0009] A driving circuit, wherein the first input of the driving circuit is used to connect to an external main control chip MCU and obtain a PWM signal from the main control chip MCU, and the second input of the driving circuit is connected to a voltage stabilizing circuit to realize the voltage output of the main control chip MCU controlling the optocoupler chip;

[0010] A push-pull circuit, one end of which is connected to a driving circuit, and the other end of which is connected to a MOS double pulse test circuit, is used to cooperate with the driving circuit to increase the driving capability of the circuit and improve the stability of the circuit.

[0011] Preferably, the driving circuit comprises:

[0012] An optocoupler isolation chip U3, an ANOOE port of the optocoupler isolation chip U3 is connected to a voltage stabilizing circuit via a fourth resistor R4, a VCC port of the optocoupler isolation chip U3 is connected to a first power supply, a VOUT port of the optocoupler isolation chip U3 is connected to a push-pull circuit, a VEE port of the optocoupler isolation chip U3 is grounded, a sixth resistor R6 is connected in parallel between the VEE port and the VOUT port of the optocoupler isolation chip U3, and a second resistor R2 is connected in parallel between the VCC port and the VOUT port of the optocoupler isolation chip U3;

[0013] The first power supply is connected in parallel with the first capacitor C1 and the second capacitor C2 and then grounded;

[0014] The ninth resistor R9, one end of the ninth resistor R9 is used to connect to the IO port of the external main control chip MCU and obtain the PWM signal from the IO port of the main control chip MCU, the other end of the ninth resistor R9 is connected to the base of the second NPN tube U5, the eleventh resistor R11 is connected in parallel between the base and the emitter of the second NPN tube U5 and then grounded, and the collector of the second NPN tube U5 is connected to the CATHOOE port of the optocoupler isolation chip U3.

[0015] Preferably, the push-pull circuit comprises:

[0016] A tenth resistor R10, one end of the tenth resistor R10 is connected to the driving circuit, and the other end of the tenth resistor R10 is connected to the base of the first NPN tube U2 and the base of the PNP tube U4 respectively;

[0017] A third resistor R3 is connected in parallel between the base and emitter of the first NPN tube U2, the emitter of the first NPN tube U2 is connected in series with the fifth resistor and then connected to the MOS double pulse test circuit, the collector of the first NPN tube U2 is connected to the second power supply, the collector of the PNP tube U4 is grounded, and the PNP tube U4 is connected in series with the seventh resistor R7 and then connected to the MOS double pulse test circuit.

[0018] Preferably, the voltage stabilizing circuit comprises:

[0019] An LDO voltage regulator chip U1, wherein a VIN port of the LDO voltage regulator chip U1 is connected to a third power source, and the third power source is connected in series with a resistor R1 and an indicator LED1 and then grounded;

[0020] The TAB port and the VOUT port of the LDO voltage regulator chip U1 are connected to the driving circuit and one end of the third capacitor C3 respectively, and the other end of the third capacitor C3 is grounded.

[0021] Preferably, the MOS double pulse test circuit comprises:

[0022] A second N-MOS transistor Q2, wherein the gate of the second N-MOS transistor Q2 is connected to the push-pull circuit;

[0023] A first N-MOS transistor Q1, a gate and a source of the first N-MOS transistor Q1 are short-circuited, a source of the first N-MOS transistor Q1 is connected to a drain of the second N-MOS transistor Q2, a drain of the first N-MOS transistor Q1 is connected to an external bus voltage VCC, and an inductor L1 is connected in parallel between the drain and the source of the first N-MOS transistor Q1.

[0024] Preferably, the driving circuit further comprises:

[0025] TVS tube D3, one end of the TVS tube D3 is connected to the drain of the second N-MOS tube Q2, the other end of the TVS tube D3 is respectively connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13, the other end of the twelfth resistor R12 is connected to the base of the first NPN tube, and the other end of the thirteenth resistor R13 is connected to the gate of the second N-MOS tube Q2.

[0026] Preferably, the driving circuit further comprises:

[0027] The eighth resistor R8 is connected in parallel with the fourth capacitor C4, one end of the eighth resistor R8 is connected to the gate of the second N-MOS transistor Q2, and the other end of the eighth resistor R8 is connected to the source of the second N-MOS transistor Q2 and grounded;

[0028] One end of the fourth capacitor C4 is connected to the gate of the second N-MOS transistor Q2, and the other end of the fourth capacitor C4 is connected to the source of the second N-MOS transistor Q2 and is grounded.

[0029] Preferably, the resistance value of the first resistor R1 is 10KΩ, the resistance values ​​of the fourth resistor R4 and the ninth resistor R9 are both 150Ω, the resistance values ​​of the third resistor R3 and the eleventh resistor R11 are both 5KΩ, the resistance values ​​of the second resistor R2, the sixth resistor R6 and the eighth resistor R8 are all 10KΩ, the resistance value of the tenth resistor R10 is 50Ω, the resistance values ​​of the twelfth resistor R12 and the thirteenth resistor R13 are both 1KΩ, the resistance value of the seventh resistor R7 is 10Ω, and the resistance value of the fifth resistor R5 is 5Ω;

[0030] The first power supply, the second power supply and the third power supply are all 12V power supplies.

[0031] Preferably, the capacitance of the first capacitor C1 and the third capacitor C3 are both 10uF, the capacitance of the second capacitor C2 is 0.1uF, and the capacitance of the fourth capacitor is 10nF;

[0032] The value of inductor L1 is 20uH.

[0033] The utility model also provides a dynamic testing system, comprising any one of the above-mentioned MOS isolation driving circuits.

[0034] Compared with the prior art, the utility model has the following beneficial effects: by adopting a driving circuit in combination with a push-pull circuit connected to a MOS double pulse test circuit, the optocoupler device is prevented from being affected, the driving capability of the circuit is increased, and the stability of the circuit is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 Schematic diagram of a circuit of an embodiment of the utility model. DETAILED DESCRIPTION

[0036] The technical solution of the present utility model is further described below in conjunction with the accompanying drawings and embodiments.

[0037] like Figure 1 As shown, the embodiment of the utility model provides a MOS isolation driving circuit, including:

[0038] An optocoupler isolation driving circuit, a voltage stabilizing circuit and a MOS double pulse testing circuit, wherein the voltage stabilizing circuit is connected to the optocoupler isolation driving circuit, the optocoupler isolation driving circuit is connected to the MOS double pulse testing circuit, and the MOS double pulse testing circuit is connected to an external bus voltage VCC;

[0039] The optical coupling isolation driving circuit comprises:

[0040] A driving circuit, wherein the first input of the driving circuit is used to connect to an external main control chip MCU and obtain a PWM signal from the main control chip MCU, and the second input of the driving circuit is connected to a voltage stabilizing circuit to realize the voltage output of the main control chip MCU controlling the optocoupler chip;

[0041] A push-pull circuit, one end of which is connected to a driving circuit, and the other end of which is connected to a MOS double pulse test circuit, is used to cooperate with the driving circuit to increase the driving capability of the circuit and improve the stability of the circuit.

[0042] The working principle of the above technical solution is as follows: in actual use, the main control chip MCU sets the PWM wave period and duty cycle through the software program, and outputs the PWM signal to the input terminal MCU_IO; at the same time, a stable voltage is output to the drive circuit through the voltage stabilizing circuit, so as to realize the voltage output of the optocoupler isolation chip U5 of the MCU_IO port control drive circuit; the output voltage is input into the MOS double pulse test circuit through the push-pull circuit, so as to realize the control of the MOS tube switch by the signal output by the MCU, and at the same time, the isolation of the drive voltage signal and the main control voltage signal is also achieved;

[0043] The beneficial effects of the above technical solution: Through the above technical solution, by adopting a driving circuit with a push-pull circuit connected to a MOS double pulse test circuit, the optocoupler device is prevented from being affected, the driving capability of the circuit is increased, and the stability of the circuit is improved.

[0044] In one embodiment, the driving circuit comprises:

[0045] An optocoupler isolation chip U3, an ANOOE port of the optocoupler isolation chip U3 is connected to a voltage stabilizing circuit via a fourth resistor R4, a VCC port of the optocoupler isolation chip U3 is connected to a first power supply, a VOUT port of the optocoupler isolation chip U3 is connected to a push-pull circuit, a VEE port of the optocoupler isolation chip U3 is grounded, a sixth resistor R6 is connected in parallel between the VEE port and the VOUT port of the optocoupler isolation chip U3, and a second resistor R2 is connected in parallel between the VCC port and the VOUT port of the optocoupler isolation chip U3;

[0046] The first power supply is connected in parallel with the first capacitor C1 and the second capacitor C2 and then grounded;

[0047] A ninth resistor R9, one end of the ninth resistor R9 is used to connect to the IO port of the external main control chip MCU and obtain a PWM signal from the IO port of the main control chip MCU, the other end of the ninth resistor R9 is connected to the base of the second NPN tube U5, the base and emitter of the second NPN tube U5 are connected in parallel with an eleventh resistor R11 and then grounded, and the collector of the second NPN tube U5 is connected to the CATHOOE port of the optocoupler isolation chip U3;

[0048] The voltage stabilizing circuit comprises:

[0049] An LDO voltage regulator chip U1, wherein a VIN port of the LDO voltage regulator chip U1 is connected to a third power source, and the third power source is connected in series with a resistor R1 and an indicator LED1 and then grounded;

[0050] The TAB port and the VOUT port of the LDO voltage regulator chip U1 are connected to the driving circuit and one end of the third capacitor C3 respectively, and the other end of the third capacitor C3 is grounded;

[0051] The working principle and beneficial effects of the above technical solution: In actual use, the main control chip MCU sets the PWM wave period and duty cycle through the software program, outputs the PWM signal to the input terminal MCU_IO, and connects the second NPN tube U5 and the ninth resistor R9 in series, so that the main control chip MCU drives the second NPN tube U5 to switch the device, avoiding the need to drive the optocoupler isolation chip U3 in the forward analog diode input current of 7mA to 16mA, resulting in the main control chip MCU being unable to drive directly; the eleventh resistor R11 protects the base and emitter of the second NPN tube U5 from being broken down by voltage;

[0052] After the third power supply supplies 12V to the voltage stabilizing circuit, the indicator LED1 lights up, and a 12V voltage is input to the LDO voltage stabilizing chip U1, thereby outputting a stable voltage of 5V to the resistor R4 side of the optocoupler isolation chip U3; the model of the LDO voltage stabilizing chip is AMS1117-5.0, and the model of the optocoupler isolation chip U3 is CA-IS3211VBJ;

[0053] When MCU_IO outputs a high-level voltage, the second NPN tube U5 is turned on, forming a loop connecting the diode inside the optocoupler isolation chip U3 and the ground, and the optocoupler isolation chip U3 outputs a high level; when MCU_IO outputs a low-level signal, the second NPN tube U5 is turned off, the diode inside the optocoupler isolation chip U3 is disconnected from the ground, and the optocoupler isolation chip U3 outputs a low level; thereby realizing the voltage output of the optocoupler chip controlled by the MCU_IO port, so that the voltage level output to the MOS double pulse test circuit depends on the external bus voltage VCC of the power supply; wherein, the first power supply, the second power supply and the third power supply are all 12V power supplies, and a second capacitor C2 with a ceramic capacitor with a capacitance of 0.1uF is connected in parallel to reduce high-frequency noise, and a first capacitor C1 with a ceramic capacitor with a capacitance of 10uF is connected in parallel to provide a higher peak current capability.

[0054] In one embodiment, the push-pull circuit comprises:

[0055] A tenth resistor R10, one end of the tenth resistor R10 is connected to the driving circuit, and the other end of the tenth resistor R10 is connected to the base of the first NPN tube U2 and the base of the PNP tube U4 respectively;

[0056] A third resistor R3 is connected in parallel between the base and emitter of the first NPN tube U2, the emitter of the first NPN tube U2 is connected in series with the fifth resistor and then connected to the MOS double pulse test circuit, the collector of the first NPN tube U2 is connected to the second power supply, the collector of the PNP tube U4 is grounded, and the PNP tube U4 is connected in series with the seventh resistor R7 and then connected to the MOS double pulse test circuit;

[0057] The MOS double pulse test circuit comprises:

[0058] A second N-MOS transistor Q2, wherein the gate of the second N-MOS transistor Q2 is connected to the push-pull circuit;

[0059] A first N-MOS transistor Q1, wherein the gate and source of the first N-MOS transistor Q1 are short-circuited, the source of the first N-MOS transistor Q1 is connected to the drain of the second N-MOS transistor Q2, the drain of the first N-MOS transistor Q1 is connected to the external bus voltage VCC, and an inductor L1 is connected in parallel between the drain and source of the first N-MOS transistor Q1;

[0060] The working principle and beneficial effects of the above technical solution: in actual use, when the output voltage of the optocoupler isolation chip U3 is 12V, the first NPN tube U2 is turned on, the PNP tube U4 is turned off, the gate voltage of the second N-MOS tube Q2 is 12V, and the MOS tube is turned on; when the output voltage of the optocoupler isolation chip U3 is 0V, the first NPN tube U2 is turned off, the gate voltage of the second N-MOS tube Q2 is 0V, and the MOS tube is turned off; through the above process, the MCU signal controls the MOS tube switch, and at the same time, the isolation of the driving voltage signal and the main control voltage signal is realized, and the isolation of the large voltage and small voltage signals of the system under high-frequency operation is realized, which improves the safety of the system, reduces the use of driving chips in the driving circuit, and reduces the design cost; wherein, the fifth resistor R5 is the gate on-resistance of the second N-MOS tube Q2, and the seventh resistor R7 is the gate off-resistance of the second N-MOS tube Q2, and the values ​​can be adjusted separately in actual tests.

[0061] In one embodiment, the driving circuit further includes:

[0062] A TVS tube D3, one end of the TVS tube D3 is connected to the drain of the second N-MOS tube Q2, the other end of the TVS tube D3 is respectively connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13, the other end of the twelfth resistor R12 is connected to the base of the first NPN tube, and the other end of the thirteenth resistor R13 is connected to the gate of the second N-MOS tube Q2;

[0063] The working principle and beneficial effects of the above technical solution are as follows: in actual use, a TVS tube D3 is used to connect a resistor in series to the VOUT port of the optocoupler isolation chip U3, thereby forming a clamping circuit; the TVS tube D3 delays the shutdown of the switch tube by detecting VDS (drain-source voltage), limits the shutdown current speed and voltage spike, and when the drain potential of the second N-MOS tube Q2 is too high, the TVS tube D3 is broken down, so that current flows into the gate of the second N-MOS tube Q2, and its gate potential is increased, so that the shutdown current is not too steep, thereby reducing the spike; when both ends of the TVS tube D3 are subjected to high-energy impact, it can suddenly reduce its impedance at an extremely high speed, while absorbing a large current, and clamping the voltage at both ends to a predetermined value, thereby protecting the safety of circuit components; through the constructed clamping circuit, short-circuit protection and soft shutdown are achieved, and the reliability of the system is enhanced;

[0064] The TVS tube D3 is connected to two branch circuits: one branch is connected to the base of the first NPN tube of the driving circuit through the twelfth resistor R12, and the current and power consumption of the TVS tube D3 are reduced through the gain of the driving circuit. The addition of the driving circuit current provides a current gain for the TVS tube D3; the other branch is directly connected to the gate of the second N-MOS tube Q2 through the thirteenth resistor R13, so that the gate voltage can be increased without delay, so that the dynamic performance of the circuit is better, the TVS current can flow into the gate quickly, and the circuit responds faster.

[0065] In one embodiment, the driving circuit further includes:

[0066] The eighth resistor R8 is connected in parallel with the fourth capacitor C4, one end of the eighth resistor R8 is connected to the gate of the second N-MOS transistor Q2, and the other end of the eighth resistor R8 is connected to the source of the second N-MOS transistor Q2 and grounded;

[0067] One end of the fourth capacitor C4 is connected to the gate of the second N-MOS transistor Q2, and the other end of the fourth capacitor C4 is connected to the source of the second N-MOS transistor Q2 and is grounded;

[0068] The working principle and beneficial effects of the above technical solution: In actual use, the fourth capacitor C4 is a compensation capacitor between the gate and the source of the second N-MOS tube Q2. Because the input capacitance value of each product is different, the test waveform can be adjusted by adjusting the value of the fourth capacitor C4 in actual application; the resistor R8 protects the gate and the source of the second N-MOS tube Q2 from being broken down by voltage.

[0069] In one embodiment, the resistance of the first resistor R1 is 10KΩ, the resistance of the fourth resistor R4 and the ninth resistor R9 are both 150Ω, the resistance of the third resistor R3 and the eleventh resistor R11 are both 5KΩ, the resistance of the second resistor R2, the sixth resistor R6 and the eighth resistor R8 are all 10KΩ, the resistance of the tenth resistor R10 is 50Ω, the resistance of the twelfth resistor R12 and the thirteenth resistor R13 are both 1KΩ, the resistance of the seventh resistor R7 is 10Ω, and the resistance of the fifth resistor R5 is 5Ω;

[0070] The first power supply, the second power supply and the third power supply are all 12V power supplies.

[0071] In one embodiment, the capacitance of the first capacitor C1 and the third capacitor C3 are both 10uF, the capacitance of the second capacitor C2 is 0.1uF, and the capacitance of the fourth capacitor is 10nF;

[0072] The value of inductor L1 is 20uH.

[0073] The utility model also provides a dynamic testing system, comprising a MOS isolation driving circuit according to any one of the above-mentioned implementation modes.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model rather than to limit it. Although the utility model has been described in detail with reference to the preferred embodiments, ordinary technicians in the field should understand that the technical solution of the utility model can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution of the utility model, which should be included in the scope of the claims of the utility model.

Claims

1. A MOS isolation driving circuit, characterized in that: include: An optocoupler isolation driving circuit, a voltage stabilizing circuit and a MOS double pulse testing circuit, wherein the voltage stabilizing circuit is connected to the optocoupler isolation driving circuit, the optocoupler isolation driving circuit is connected to the MOS double pulse testing circuit, and the MOS double pulse testing circuit is connected to an external bus voltage VCC; The optical coupling isolation driving circuit comprises: A driving circuit, wherein the first input of the driving circuit is used to connect to an external main control chip MCU and obtain a PWM signal from the main control chip MCU, and the second input of the driving circuit is connected to a voltage stabilizing circuit to realize the voltage output of the main control chip MCU controlling the optocoupler chip; A push-pull circuit, one end of which is connected to a driving circuit, and the other end of which is connected to a MOS double pulse test circuit, is used to cooperate with the driving circuit to increase the driving capability of the circuit and improve the stability of the circuit.

2. A MOS isolation driving circuit as claimed in claim 1, characterized in that: The driving circuit comprises: An optocoupler isolation chip U3, an ANOOE port of the optocoupler isolation chip U3 is connected to a voltage stabilizing circuit via a fourth resistor R4, a VCC port of the optocoupler isolation chip U3 is connected to a first power supply, a VOUT port of the optocoupler isolation chip U3 is connected to a push-pull circuit, a VEE port of the optocoupler isolation chip U3 is grounded, a sixth resistor R6 is connected in parallel between the VEE port and the VOUT port of the optocoupler isolation chip U3, and a second resistor R2 is connected in parallel between the VCC port and the VOUT port of the optocoupler isolation chip U3; The first power supply is connected in parallel with the first capacitor C1 and the second capacitor C2 and then grounded; The ninth resistor R9, one end of the ninth resistor R9 is used to connect to the IO port of the external main control chip MCU and obtain the PWM signal from the IO port of the main control chip MCU, the other end of the ninth resistor R9 is connected to the base of the second NPN tube U5, the eleventh resistor R11 is connected in parallel between the base and the emitter of the second NPN tube U5 and then grounded, and the collector of the second NPN tube U5 is connected to the CATHOOE port of the optocoupler isolation chip U3.

3. The MOS isolation driving circuit according to claim 1, characterized in that: The push-pull circuit comprises: A tenth resistor R10, one end of the tenth resistor R10 is connected to the driving circuit, and the other end of the tenth resistor R10 is connected to the base of the first NPN tube U2 and the base of the PNP tube U4 respectively; A third resistor R3 is connected in parallel between the base and emitter of the first NPN tube U2, the emitter of the first NPN tube U2 is connected in series with the fifth resistor and then connected to the MOS double pulse test circuit, the collector of the first NPN tube U2 is connected to the second power supply, the collector of the PNP tube U4 is grounded, and the PNP tube U4 is connected in series with the seventh resistor R7 and then connected to the MOS double pulse test circuit.

4. The MOS isolation driving circuit according to claim 1, characterized in that: The voltage stabilizing circuit comprises: An LDO voltage regulator chip U1, wherein a VIN port of the LDO voltage regulator chip U1 is connected to a third power source, and the third power source is connected in series with a resistor R1 and an indicator LED1 and then grounded; The TAB port and the VOUT port of the LDO voltage regulator chip U1 are connected to the driving circuit and one end of the third capacitor C3 respectively, and the other end of the third capacitor C3 is grounded.

5. The MOS isolation driving circuit according to any one of claims 1 to 4, characterized in that: The MOS double pulse test circuit comprises: A second N-MOS transistor Q2, wherein the gate of the second N-MOS transistor Q2 is connected to the push-pull circuit; A first N-MOS transistor Q1, a gate and a source of the first N-MOS transistor Q1 are short-circuited, a source of the first N-MOS transistor Q1 is connected to a drain of the second N-MOS transistor Q2, a drain of the first N-MOS transistor Q1 is connected to an external bus voltage VCC, and an inductor L1 is connected in parallel between the drain and the source of the first N-MOS transistor Q1.

6. The MOS isolation driving circuit according to claim 5, characterized in that: The driving circuit further includes: TVS tube D3, one end of the TVS tube D3 is connected to the drain of the second N-MOS tube Q2, the other end of the TVS tube D3 is respectively connected to one end of the twelfth resistor R12 and one end of the thirteenth resistor R13, the other end of the twelfth resistor R12 is connected to the base of the first NPN tube, and the other end of the thirteenth resistor R13 is connected to the gate of the second N-MOS tube Q2.

7. The MOS isolation driving circuit according to claim 5, characterized in that: The driving circuit further includes: The eighth resistor R8 is connected in parallel with the fourth capacitor C4, one end of the eighth resistor R8 is connected to the gate of the second N-MOS transistor Q2, and the other end of the eighth resistor R8 is connected to the source of the second N-MOS transistor Q2 and grounded; One end of the fourth capacitor C4 is connected to the gate of the second N-MOS transistor Q2, and the other end of the fourth capacitor C4 is connected to the source of the second N-MOS transistor Q2 and is grounded.

8. The MOS isolation driving circuit according to claim 5, characterized in that: The resistance value of the first resistor R1 is 10KΩ, the resistance values ​​of the fourth resistor R4 and the ninth resistor R9 are both 150Ω, the resistance values ​​of the third resistor R3 and the eleventh resistor R11 are both 5KΩ, the resistance values ​​of the second resistor R2, the sixth resistor R6 and the eighth resistor R8 are all 10KΩ, the resistance value of the tenth resistor R10 is 50Ω, the resistance values ​​of the twelfth resistor R12 and the thirteenth resistor R13 are both 1KΩ, the resistance value of the seventh resistor R7 is 10Ω, and the resistance value of the fifth resistor R5 is 5Ω; The first power supply, the second power supply and the third power supply are all 12V power supplies.

9. The MOS isolation driving circuit according to claim 5, characterized in that: The capacitance of the first capacitor C1 and the third capacitor C3 are both 10uF, the capacitance of the second capacitor C2 is 0.1uF, and the capacitance of the fourth capacitor is 10nF; The value of inductor L1 is 20uH.

10. A dynamic testing system, characterized in that: An isolation driving circuit comprising the MOS as claimed in any one of claims 1 to 9.

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