Power MOS tube

Abstract

The utility model discloses a power MOS (Metal Oxide Semiconductor) tube, which comprises a substrate; the epitaxy is positioned on the front surface of the substrate; a first trench formed in the epitaxy; a second trench formed in the epitaxy; the drain electrode is formed on the back surface of the substrate; wherein a first part of a grid electrode and a first source electrode are formed around the first groove, and the first source electrode, the first part of the grid electrode and the drain electrode form a main tube; a second portion of the gate and a second source are formed around the second trench, the second source, the second portion of the gate, and the drain constitute a current mirror paired with the main tube. The problem caused by the fact that a resistor for current detection is omitted can be well solved, and the requirement for BMS application is met.

Description

Technical Field

[0001] The utility model relates to semiconductor products and manufacturing, in particular to power MOS tubes and manufacturing. Background Art

[0002] In existing BMS (battery management system) applications, two power MOS tubes are usually used to control the charge and discharge of lithium batteries. For example, on a conventional lithium battery protection board, there are: a protection control chip such as DW01, two power MOS tubes matched with the chip, and a current detection resistor connected in series in the current loop of the two power MOS tubes. Among them, one of the two power MOS tubes is used for the discharge control of lithium batteries, and the other is used for the discharge control of lithium batteries; this current detection resistor uses a high-precision, small-resistance metal resistor, which has its own power loss, heat, and high cost. In order to solve these problems caused by this current detection resistor, people have considered a variety of solutions.

[0003] An existing solution is to integrate the power MOS tube and the protection control circuit on a single chip, and use a current mirror that matches the power MOS tube to replace the detection resistor to achieve current detection. This technical path will lead to mutual entanglement and restriction between the on-wafer implementation of the power MOS tube and the on-wafer implementation of the protection control circuit.

[0004] Another existing solution is to integrate the power MOS tube and the protection control circuit on two chips respectively, so that the on-wafer implementation of the power MOS tube and the on-wafer implementation of the protection control circuit are independent of each other, and a current mirror matched with the power MOS tube is used to replace the detection resistor to realize current detection. This technical path will lead to a mismatch between the independently implemented current mirror and the power MOS tube. In order to correct the mismatch, it is necessary to configure a complex auxiliary circuit for the current mirror, which increases the complexity of the protection control circuit. Utility Model Content

[0005] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, the present invention proposes a power MOS tube, which can better solve the problem caused by omitting the resistor for current detection and meet the needs of BMS application.

[0006] The utility model solves the technical problem by adopting a technical solution comprising: providing a dual MOS tube, comprising: a substrate; an epitaxial portion located on the front side of the substrate; a first groove formed in the epitaxial portion; a second groove formed in the epitaxial portion; a drain formed on the back side of the substrate; wherein a first portion of a gate and a first source are formed around the first groove, and the first source, the first portion of the gate and the drain constitute a main tube; a second portion of the gate and a second source are formed around the second groove, and the second source, the second portion of the gate and the drain constitute a current mirror matched with the main tube.

[0007] In some embodiments, there are two main conductors and a current mirror paired with one of the two main conductors.

[0008] In some embodiments, the paired main pipe and the current mirror are respectively provided with a left gate, a left first source, and a left second source; the single main pipe is respectively provided with a right gate and a right first source.

[0009] In some embodiments, the first grooves of the two main pipes are divided into two types: deeper and shallower.

[0010] In some embodiments, there are two main tubes and two current mirrors paired with the two main tubes respectively.

[0011] In some embodiments, the first set of paired main pipes and current mirrors are respectively provided with a left gate, a left first source, and a left second source; the second set of paired main pipes and current mirrors are respectively provided with a right gate, a right first source, and a right second source.

[0012] In some embodiments, the first grooves of the two main pipes are divided into two types: deeper and shallower.

[0013] In some embodiments, the depth of the second trench is the same as the depth of the first trench.

[0014] Compared with the prior art, the dual MOS tube of the utility model can organically combine a main MOS and a current mirror paired with the main MOS by forming a first trench and a second trench of the same depth on the same epitaxial layer, and then forming a first source and a first part of a gate around the first trench and forming a second source and a second part of a gate around the second trench, so as to better solve the problem caused by eliminating the resistor for current detection and meet the needs of BMS applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The circuit structure of the power MOS tube of the utility model is schematically shown.

[0016] Figure 2 The flowchart of the manufacturing method of the power MOS tube of the utility model is shown.

[0017] Figures 3a-3k The relevant manufacturing process of the power MOS tube of the utility model is schematically illustrated.

[0018] Among them, the description of the reference numerals is as follows: 10 power MOS tube Q1 main tube Q2 main tube; 301, 301a substrate 302 epitaxy 303, 304, 305 deeper trench 307, 307a, 307b oxide layer 308, 309, 310 polysilicon filling 311 upper part of the first trench 311a upper part of the second trench 312, 313, 314 shallower trench 315 oxide layer 316, 317, 318, 319 polysilicon filling 320 channel 321 same doping of the left first source 321a same doping of the left second source 322 same doping of the right first source 322a same doping of the right second source 323 interlayer dielectric 324 metal of the left first source 324a metal of the left second source 325 metal of the right first source 325a metal of the right second source 327 metal of the drain DETAILED DESCRIPTION

[0019] Now, in conjunction with the accompanying drawings, a preferred embodiment of the present utility model is described in detail.

[0020] See also Figure 1 , Figure 1 The circuit structure of the power MOS tube of the utility model is schematically shown. The circuit 10 includes two main pipes Q1 and Q2 and two current mirrors Q1i and Q2i respectively matched with the two main pipes Q1 and Q2. The two main pipes Q1 and Q2 share a drain D.

[0021] Among them, the first group of paired main pipe Q1 and current mirror Q1i are correspondingly provided with a left gate G1, a left first source S1, and a left second source S1i (also called a first current sensing end); the second group of paired main pipe Q2 and current mirror Q2i are correspondingly provided with a right gate G2, a right first source S2, and a right second source S2i (also called a second current sensing end).

[0022] See also Figure 2 and Figure 3, Figure 2 The flowchart of the manufacturing method of the power MOS tube of the utility model is shown. Figure 3a-3j The relevant manufacturing process of the power MOS tube of the utility model is schematically illustrated.

[0023] The manufacturing method of the power MOS tube of the utility model generally comprises the following steps:

[0024] 201, engrave a deeper first groove and a deeper second groove, corresponding to Figure 1 The first pair of current mirrors Q1 and Q1i. Figure 3a The diagram schematically shows a substrate 301 located underneath and an epitaxial layer 302 located on the front side of the substrate 301 . Figure 3bThe first trench 303, the second trench 304, and the third trench 305 are shown as relatively deep, wherein the first trench 303 is used to form the first part of the subsequent left gate and the left first source, the second trench 304 is used to form the second part of the subsequent left gate and the left second source, and the third trench 305 is a floating trench. The trenches 303, 304, and 305 are formed by photolithography + etching process. The first trench 303 and the second trench 304 have the same depth.

[0025] Specifically, an epitaxy 302 having the same doping form as the substrate material is grown on the substrate 301 , and the concentration and thickness of the epitaxy 302 are jointly determined by the withstand voltage characteristics of the two main tubes.

[0026] It is worth mentioning that in this embodiment, three trenches 303, 304, 305 are illustrated, and the trench 305 outside the source formation region is used for isolation. In other embodiments, the number of trenches is not necessarily limited to three.

[0027] 202. Grow source oxide layer + fill source polysilicon. Figure 3c It is schematically shown that an oxide layer 307 is grown on the front side of the epitaxial layer 302 (including the surfaces of the trenches 303 , 304 , and 305 ) by thermal oxidation or chemical vapor deposition. Figure 3d It shows that the trenches 303 , 304 , 305 with oxide layers 307 are filled with polysilicon 308 , 309 , 310 , respectively, wherein the polysilicon 308 filled in the lower part of the trenches 303 , 304 forms the first part of the left first source S1 and the first part of the left second source S1i (also called shielding electrode).

[0028] Specifically, the grooves 303, 304, and 305 are first photolithographically made on the basis of the epitaxial 302, and then the silicon epitaxial layer is etched to obtain the desired voltage-resistant depth, and then an oxide layer is grown in the groove. The oxide layer is mainly used for charge coupling. The depth of the groove and the thickness of the charge-coupled oxide layer, together with the specifications of the epitaxial layer, determine the voltage levels of the main conductor Q1 and the current mirror Q1i.

[0029] After the charge-coupled oxide layer is grown, polysilicon is deposited to form source polysilicon, and then the polysilicon is etched to the silicon surface (i.e. Figure 3d The morphology of the polysilicon 310 is then determined, followed by photolithography of the source polysilicon, and then etching of the source polysilicon in the active region (i.e. Figure 3d morphology of polysilicon 308, 309).

[0030] 203. High-density plasma + chemical mechanical polishing. Figure 3e and Figure 3fThe diagram shows the situation after treatment with high-density plasma + chemical mechanical polishing process. At this time, the oxide layer 307a occupies the entire first groove 303 (excluding polysilicon 308), the oxide layer 307b occupies the entire second groove 304 (excluding polysilicon 309), and the oxide layer 307 on the front side of the epitaxial 302 (excluding the surface of the grooves 303, 304, and 305) has been removed.

[0031] It is worth mentioning that at this time, the upper part 311 of the first trench 303 is also formed, that is, the upper part of the oxide layer 307a in the first trench 303 has been removed, preparing for the subsequent formation of the first part of the left gate; similarly, the upper part 311a of the second trench 304 is also formed, that is, the upper part of the oxide layer 307b in the second trench 304 has been removed, preparing for the subsequent formation of the first part and the second part of the left gate.

[0032] Specifically, after the source polysilicon is defined, the oxide layer is deposited using high-density plasma (HDP) to fill the deep groove area of ​​the active area of ​​the main Q1 and the current mirror Q1i, and then the oxide layer is chemically mechanically polished to the silicon surface, followed by active area photolithography to etch the filled oxide layer to form Figure 3f The polysilicon 308, the upper portion 311 structure of the first trench 303 and the upper portion 311a structure of the second trench 304, and the remaining oxide layer is the isolation layer of the subsequent gate polysilicon and source polysilicon. Figure 3f The distance between the top of the middle polysilicon 308 and the bottom of the upper portion 311 of the first trench 303 is generally 2500 to 3500 angstroms.

[0033] 204, engrave a shallower first groove and a second groove, corresponding to Figure 1 The second pair of current mirrors Q2 and Q2i. Figure 3f The diagram shows a shallower first trench 312, a second trench 313, and a third trench 314, wherein the first trench 312 and the second trench 313 are used to form a subsequent right gate, and the third trench 314 is a floating trench. The trenches 312, 313, and 314 are formed by photolithography + etching process.

[0034] Specifically, after completing the partial architecture of the first set of paired main pipes Q1 and current mirrors Q1i, the second trench lithography begins, mainly used to define the second set of paired main pipes Q2 and current mirrors Q2i, and then the silicon is etched to a depth of between 1 and 1.5 microns, depending on the device's withstand voltage.

[0035] It is worth mentioning that in this embodiment, three trenches 312, 313, 314 are illustrated, and the trench 314 outside the source formation region is used for isolation. In other embodiments, the number of trenches is not necessarily limited to three.

[0036] 205. Grow gate oxide layer + fill gate polysilicon. Figure 3g The diagram shows that polysilicon 317, 318, 319 are filled in the trenches 312, 313, 314 where the oxide layer 315 has been grown, respectively, wherein the polysilicon 317 filled in the first trench 312 forms the first part of the right gate. It is worth mentioning that an oxide layer 315 is also formed in the upper part 311 of the first trench 312, and polysilicon 316 is filled to form the first part of the right gate. Similarly, corresponding to the second trench 313, the second part of the right gate is formed.

[0037] Specifically, thermal oxidation is then performed to form a sacrificial oxide layer for repairing the trench sidewalls. After wet etching to remove the sacrificial oxide layer, thermal oxidation is continued to grow a gate oxide layer (gate oxide), followed by gate polysilicon filling. At this time, the first part of the left gate and the first part of the right gate are completed together, and then the gate polysilicon is etched to define the gate structure.

[0038] 206. Injection into channel + injection into source. Figure 3h It illustrates the channel 320 formed on the front side of the epitaxy 302, the same doping 321 formed by source injection of the left first source S1, the same doping 321a formed by source injection of the left second source S1i, the same doping 322 formed by source injection of the right first source S2, and the same doping 322a formed by source injection of the right second source S2i.

[0039] Specifically, after the gate structure is determined, the channel is injected with impurities different from the epitaxial doping, and diffused at high temperature to form the MOS channel. Then the source is photolithographically processed to define the injection area of ​​the source, and then impurities consistent with the epitaxial layer doping are injected with a concentration between 4E15 and 8E15. A lower temperature of 900 to 950 degrees Celsius is used for activation to form the same doping 321, 321a, 322, and 322a.

[0040] 207. Engraving contact holes + engraving metal + depositing passivation layer. Figure 3i The diagram illustrates an interlayer dielectric 323, a metal 324 of the left first source (also called the second part of the left first source, which is connected to the first part of the left first source), a metal 324a of the left second source, a metal 325 of the right first source, a metal 325a of the right second source, and a passivation layer (not shown).

[0041] Specifically, after the source is completed, an oxide layer (ILD, interlayer dielectric) is chemically vapor deposited, followed by contact hole lithography, and then the oxide layer of the open area is etched and the silicon under the window is further etched. The etched silicon depth is generally between 0.25 and 0.5 microns.

[0042] After the contact hole is completed, metal sputtering is performed to form a contact metal electrode on the surface, and then metal lithography is performed to define the metal area of ​​the gate and the source. The two are physically isolated by graphic definition and corrosion. It is worth mentioning that metal lithography is used to isolate the metal area defined as the gate and the metal area defined as the source. The metal area of ​​the gate (not shown in the figure, it is connected to the first part and the second part of the gate) is also formed by the contact hole and the front metal process.

[0043] After the metal etching is completed, a passivation layer is deposited, and then the wiring area is defined by photolithography and etched, thereby completing the definition of the gate and source wiring areas.

[0044] 208. Grinding the back side + evaporating metal. Figure 3j It is understandable that by grinding the back side, the substrate 301a can become thinner, and then the metal 327 of the drain is formed by using a metal evaporation process.

[0045] Specifically, after the front process is completed, the silicon substrate on the back side is mechanically ground, and after grinding, the silicon is chemically etched (to remove surface defects caused by grinding). The final silicon thickness can be selected in the range of 40 to 200 microns. The thinner the silicon, the better the conduction characteristics. After grinding, the back side metal is sputtered or evaporated to form the drain of the MOS, and the power MOS of the utility model is finally completed.

[0046] See also Figure 3k , schematically shows the top view structure of the power MOS of the utility model. Among them, the first group of paired main tube Q1 and current mirror Q1i are shielded gate trench MOS, and the second group of paired main tube Q2 and current mirror Q2i are trench MOS. The withstand voltage performance between the gate and drain of the first main tube is better than the withstand voltage performance between the gate and drain of the second main tube.

[0047] For example, the withstand voltage performance between the gate and drain of the main MOS tube Q1 is 60V, and the withstand voltage performance between the gate and drain of the main MOS tube Q2 is 30V. Alternatively, the withstand voltage performance between the gate and drain of the main MOS tube Q1 is 80V, and the withstand voltage performance between the gate and drain of the main MOS tube Q2 is 20V.

[0048] It is understandable that, in conjunction with Figure 1A single power MOS tube of this type formed on a silicon-based wafer has seven metal pins: a metal pin corresponding to the source S1 of the main conductor Q1, a metal pin corresponding to the gate G1 of the main conductor Q1, a metal pin corresponding to the current sensing end S1i of the current mirror Q1i of the main conductor Q1, a metal pin corresponding to the source S2 of the main conductor Q2, a metal pin corresponding to the gate G2 of the main conductor Q2, a metal pin corresponding to the current sensing end S2i of the current mirror Q2i of the main conductor Q2, and a metal pin corresponding to the common drain D of the main conductor Q1, the current mirror Q1i, the main conductor Q2 and the current mirror Q2i.

[0049] It is understandable that, depending on the needs of actual applications, in some other embodiments, the main conductors Q1, Q2 and the current mirror Q1i may be retained, while the current mirror Q2i may be omitted. In this case, a single power MOS tube formed on a silicon-based wafer has six metal pins: a metal pin corresponding to the source S1 of the main conductor Q1, a metal pin corresponding to the gate G1 of the main conductor Q1, a metal pin corresponding to the current sensing end S1i of the current mirror Q1i of the main conductor Q1, a metal pin corresponding to the source S2 of the main conductor Q2, a metal pin corresponding to the gate G2 of the main conductor Q2, and a metal pin corresponding to the common drain D of the main conductor Q1, the current mirror Q1i and the main conductor Q2.

[0050] In some other embodiments, the main conductor Q1, the main conductor Q2 and the current mirror Q2i may be retained, while the current mirror Q1i is omitted. In this case, a single power MOS tube formed on a silicon-based wafer has six metal pins: a metal pin corresponding to the source S1 of the main conductor Q1, a metal pin corresponding to the gate G1 of the main conductor Q1, a metal pin corresponding to the source S2 of the main conductor Q2, a metal pin corresponding to the gate G2 of the main conductor Q2, a metal pin corresponding to the current sensing end S2i of the current mirror Q2i of the main conductor Q2, and a metal pin corresponding to the common drain D of the main conductor Q1, the main conductor Q2 and the current mirror Q2i.

[0051] In some other embodiments, the main conductor Q1 and the current mirror Q1i may be retained, while the main conductor Q2 and the current mirror Q2i may be omitted. In this case, a single power MOS transistor formed on a silicon-based wafer has four metal pins: a metal pin corresponding to the source S1 of the main conductor Q1, a metal pin corresponding to the gate G1 of the main conductor Q1, a metal pin corresponding to the current sensing end S1i of the current mirror Q1i of the main conductor Q1, and a metal pin corresponding to the common drain D of the main conductor Q1 and the current mirror Q1i.

[0052] In some other embodiments, the main conductor Q2 and the current mirror Q2i may be retained, while the main conductor Q1 and the current mirror Q1i may be omitted. In this case, a single power MOS transistor formed on a silicon-based wafer has four metal pins: a metal pin corresponding to the source S2 of the main conductor Q2, a metal pin corresponding to the gate G2 of the main conductor Q2, a metal pin corresponding to the current sensing end S2i of the current mirror Q2i of the main conductor Q2, and a metal pin corresponding to the common drain D of the main conductor Q2 and the current mirror Q2i.

[0053] For example, the main conductor Q1 and the main conductor Q2 have different performances, such as: the main conductor Q1 is an SGT MOS tube, and the main conductor Q2 is a TRENCH MOS tube; or, the main conductor Q1 and the main conductor Q2 are both SGT MOS tubes or TRENCH MOS tubes, but the sizes of the wafer areas occupied by the two are different. It can be understood that: the MOS tube occupying a larger wafer area has a smaller on-resistance than the MOS tube occupying a smaller wafer area, and allows a larger current to pass through.

[0054] It should be understood that the above embodiments are only used to illustrate the technical solutions of the present utility model, rather than to limit it. For those skilled in the art, the technical solutions described in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents; and these modifications and replacements should all fall within the scope of protection of the claims attached to the present utility model.

Claims

1. A power MOS tube, characterized in that: include: substrate; epitaxy, located on the front side of the substrate; a first trench formed in the epitaxy; a second trench formed in the epitaxy; A drain electrode formed on the back side of the substrate; Wherein, a first portion of the gate and a first source are formed around the first trench, and the first source, the first portion of the gate and the drain constitute a main pipe; A second portion of the gate and a second source are formed around the second trench, and the second source, the second portion of the gate and the drain constitute a current mirror paired with the main pipe.

2. The power MOS tube according to claim 1, characterized in that: There are two main conductors and a current mirror paired with one of the two main conductors.

3. The power MOS tube according to claim 2, characterized in that: The paired main tube and the current mirror are provided with a left gate, a left first source, and a left second source respectively; the single main tube is provided with a right gate and a right first source respectively.

4. The power MOS tube according to claim 2, characterized in that: The first grooves of the two main pipes are divided into two types: deeper and shallower.

5. The power MOS tube according to claim 1, characterized in that: The invention has two main pipes and two current mirrors which are paired with the two main pipes respectively.

6. The power MOS tube according to claim 5, characterized in that: The first set of paired main pipes and current mirrors are respectively provided with a left gate, a left first source, and a left second source; the second set of paired main pipes and current mirrors are respectively provided with a right gate, a right first source, and a right second source.

7. The power MOS tube according to claim 5, characterized in that: The first grooves of the two main pipes are divided into two types: deeper and shallower.

8. The power MOS tube according to claim 1, characterized in that: The depth of the second trench is the same as the depth of the first trench.

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