Semiconductor device

Abstract

A semiconductor device includes a semiconductor substrate, a first transistor, a second transistor over the first transistor, and a first isolation structure. The first transistor is on the semiconductor substrate. The first transistor comprises a first channel, a first source electrode and a first drain electrode. The first source and the first drain are on opposite sides of the first channel. The second transistor comprises a second channel, a second source electrode and a second drain electrode. The second source and the second drain are on opposite sides of the second channel. The first transistor and the second transistor are connected in series. The first isolation structure is vertically between the first drain and the second source. An isolation structure is formed between the epitaxial source / drain regions of the vertically stacked transistors, allowing the transistors to be connected in series with each other without increasing the footprint of the integrated circuit.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate; and using lithography to pattern the various material layers to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continuing to reduce minimum feature sizes, which allows more components to be integrated into a given area. Utility Model Content

[0004] In some embodiments, a semiconductor device includes a semiconductor substrate, a first transistor, a second transistor above the first transistor, and a first isolation structure. The first transistor is on the semiconductor substrate. The first transistor includes a first channel, a first source, and a first drain. The first source and the first drain are on opposite sides of the first channel. The second transistor includes a second channel, a second source, and a second drain. The second source and the second drain are on opposite sides of the second channel. The first isolation structure is vertically between the first drain and the second source.

[0005] In some embodiments, a semiconductor device includes a substrate, a plurality of first semiconductor layers, a first metal gate structure, a plurality of second semiconductor layers, and a second metal gate structure. The first semiconductor layers are disposed above each other above the substrate. The first metal gate structure encapsulates the first semiconductor layers. The second semiconductor layers are disposed above each other above the substrate. The second metal gate structure encapsulates the second semiconductor layers and is separated from the first metal gate structure. When viewed from a cross-sectional view, the first metal gate structure has a first height, and the second metal gate structure has a second height less than the first height. When viewed from a top view, the second metal gate structure has a top surface area different from a top surface area of ​​the first metal gate structure.

[0006] In some embodiments, a semiconductor device includes a semiconductor substrate, a plurality of first semiconductor layers, and a first epitaxial source / drain region and a second epitaxial source / drain region, wherein the first semiconductor layers are arranged above each other above the semiconductor substrate. The first epitaxial source / drain region and the second epitaxial source / drain region are on the semiconductor substrate, wherein the first epitaxial source / drain region and the second epitaxial source / drain region are respectively on opposite sidewalls of the plurality of first semiconductor layers, and the first epitaxial source / drain region has a height greater than a height of the second epitaxial source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. Please note that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the sizes of various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A , Figure 1B , Figure 1C and Figure 1D A method for manufacturing an integrated circuit including vertically stacked transistors on a semiconductor substrate according to some embodiments of the present disclosure;

[0009] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A and Fig.29A is a top view of an integrated circuit according to some embodiments of the present disclosure;

[0010] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.18B According to some embodiments, the steps of Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.18A A cross-sectional view taken along line AA';

[0011] Fig.18C For example, in various stages along the Fig.18A A cross-sectional view taken along line BB';

[0012] Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B and Fig.29B According to some embodiments, the following are respectively Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A and Fig.29A A cross-sectional view taken along line BB';

[0013] Fig.19C , Fig.23C , Fig.24C , Fig.26C , Fig.27C , Fig.28C and Fig.29C are respectively at various stages along the Fig.23A and Fig.24A A cross-sectional view taken along line AA';

[0014] Fig.29D Similar to Fig.29B , except for marking circuit reference numbers for discussing circuit diagrams;

[0015] Fig.29E According to some embodiments of the present disclosure FIG. 29A to FIG. 29DAn illustrative circuit diagram of vertically stacked transistors in an integrated circuit.

[0016]

Explanation of symbols

[0017] 1000:Method

[0018] 100:Substrate

[0019] 102: Shallow Trench Isolation (STI) Region

[0020] 104: Stack

[0021] 106: First multi-layer stack

[0022] 108: Middle sacrificial layer

[0023] 110: Second multi-layer stack

[0024] 112: First sacrificial layer

[0025] 114W: Width

[0026] 114: first semiconductor layer

[0027] 116: Second sacrificial layer

[0028] 118W: Width

[0029] 118: Second semiconductor layer

[0030] 120: Dielectric layer

[0031] 122: dummy gate structure

[0032] 124: Gate spacer

[0033] 126: Patterned photoresist

[0034] 128: Groove

[0035] 130a: side wall recess

[0036] 130b: side wall recess

[0037] 130c: side wall recess

[0038] 132: Internal spacer

[0039] 134: Dielectric layer

[0040] 136: Photoresist

[0041] 138: Groove

[0042] 140AH:Height

[0043] 140A: Epitaxial source / drain region

[0044] 140BH:Height

[0045] 140B: epitaxial source / drain region

[0046] 140: Epitaxial source / drain material

[0047] 142: Patterned photoresist

[0048] 144: concave part

[0049] 146: Patterned photoresist

[0050] 148: concave part

[0051] 150AT: Top surface

[0052] 150A: First isolation structure

[0053] 150BT: Top surface

[0054] 150B: Second isolation structure

[0055] 150: Isolation material

[0056] 152: Patterned photoresist

[0057] 154: concave part

[0058] 156: Patterned photoresist

[0059] 158: concave part

[0060] 160AH:Height

[0061] 160A: Epitaxial source / drain region

[0062] 160BH:Height

[0063] 160B: epitaxial source / drain region

[0064] 162: Source / drain contact

[0065] 164: Dielectric layer

[0066] 166: First groove

[0067] 168: Protective layer

[0068] 170: side wall recess

[0069] 172: Internal spacer

[0070] 172H:Height

[0071] 172W: Width

[0072] 174: Gap

[0073] 176: first metal gate structure

[0074] 176H:Height

[0075] 176L: Length

[0076] 176W: Width

[0077] 178: Interface layer

[0078] 180: Gate dielectric layer

[0079] 182: Work function layer

[0080] 184: Filler Metal

[0081] 186: Second groove

[0082] 188: Gap

[0083] 190: Spacer material

[0084] 190H: Maximum height

[0085] 190W: Width

[0086] 192: Gap

[0087] 194: Second metal gate structure

[0088] 194H:Height

[0089] 194L: Length

[0090] 194W: Width

[0091] 196: Interface layer

[0092] 198: Gate dielectric layer

[0093] 200: work function layer

[0094] 202: Filler Metal

[0095] 300: Power Amplifier

[0096] 302: Pre-amplified signal

[0097] 304: Input signal

[0098] 306: Amplified output signal

[0099] 308: Control voltage

[0100] 310: Node

[0101] A-A': section line

[0102] CH1: Channel 1

[0103] CH2: Second channel

[0104] CH3: The third channel

[0105] CH4: The fourth channel

[0106] D1: Drain

[0107] D2: Drain

[0108] D3: Drain

[0109] D4: Drain

[0110] d: vertical distance

[0111] S1: Source

[0112] S2: Source

[0113] S3: Source

[0114] S4: Source

[0115] S100: Block

[0116] S102: Block

[0117] S104: Block

[0118] S106: Block

[0119] S108: Block

[0120] S110: Block

[0121] S112: Block

[0122] S114: Block

[0123] S116: Block

[0124] S118: Block

[0125] S120: Block

[0126] S122: Block

[0127] S124: Block

[0128] S126: Block

[0129] S128: Block

[0130] S130: Block

[0131] S132: Block

[0132] S134: Block

[0133] S136: Block

[0134] S138: Block

[0135] S140: Block

[0136] S142: Block

[0137] S144: Block

[0138] S146: Block

[0139] S148: Block

[0140] S150: Block

[0141] S152: Block

[0142] T1: First transistor

[0143] T2: Second transistor

[0144] T3: The third transistor

[0145] T4: The fourth transistor

[0146] VDD: High power supply voltage

[0147] VSS: Low power supply voltage

[0148] XYZ: Coordinates DETAILED DESCRIPTION

[0149] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first and second features are formed in direct contact, and may also include an embodiment in which an additional feature may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0150] Additionally, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein for ease of description to describe the relationship of one or more elements or features to another or further elements or features as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0151] As used herein, "substantially," "approximately," "about," or "substantially" may mean within 20% or within 10%, or within 5% of a given value or range. However, one skilled in the art will recognize that the values ​​or ranges recited throughout the description are merely examples and may decrease as integrated circuits are scaled down. The quantities given herein are approximate, meaning that the terms "substantially," "about," "approximately," or "substantially" may be interpreted without explicit statement.

[0152] Unless otherwise defined, all terms (including technical terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which the present disclosure belongs. It should be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense, unless otherwise expressly defined herein.

[0153] A gate all around (GAA) transistor structure may be patterned by any suitable method. For example, the structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. In general, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing patterns to be produced that have, for example, a pitch that is smaller than would otherwise be obtained using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

[0154] As discussed in more detail below, embodiments of the present disclosure describe an integrated circuit including vertically stacked transistors on a semiconductor substrate. The techniques described herein include forming isolation structures between epitaxial source / drain regions of the vertically stacked transistors to allow the transistors to be connected in series with each other without increasing the footprint of the integrated circuit.

[0155] View now Figures 1A to 1D, illustrated is a flow chart of an exemplary method 1000 for fabricating an integrated circuit including vertically stacked transistors on a semiconductor substrate according to some embodiments. The method 1000 includes relevant portions of the overall fabrication process. It should be understood that additional operations may be performed by Figures 1A to 1D The illustrated processes are provided before, during, and after, and some of the operations described below may be replaced or eliminated for additional embodiments of the method. The order of the operations / processes may be interchangeable. The method 1000 includes manufacturing a semiconductor device. However, the manufacturing of the semiconductor device is merely an example for describing a manufacturing process according to some embodiments of the present disclosure.

[0156] FIG. 2A to FIG. 29C A schematic diagram illustrating an intermediate stage in forming vertically stacked transistors in an integrated circuit according to some embodiments of the present disclosure. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A and Fig.29A FIG. 4 is a top view of an integrated circuit according to some embodiments of the present disclosure. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B and Fig.18B According to some embodiments, the steps of Figure 2A , Figure 3A , Figure 4A, Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A and Fig.18A A cross-sectional view taken along line AA'. Fig.18C For example, in various stages along the Fig.18A A cross-sectional view taken along line BB'.

[0157] Fig.19B , Fig. 20B , Fig. 21B , Fig. 22B , Fig. 23B , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28B and Fig.29B According to some embodiments, the following are respectively Fig.19A , Fig. 20A , Fig.21A , Fig.22A , Fig.23A , Fig.24A , Fig.25A , Fig.26A , Fig.27A , Fig.28A and Fig.29A A cross-sectional view taken along line BB'. Fig.19C , Fig.23C , Fig.24C , Fig.26C , Fig.27C , Fig.28C and Fig.29C are respectively at various stages along the Fig.23A and Fig.24A A cross-sectional view taken along line AA'. Fig.29E Similar to Fig.29B , except that circuit elements are marked for clarity and structural elements are omitted. The XYZ coordinates are shown in FIG. 2A to FIG. 29C and Fig.29E middle.

[0158] The method 1000 begins with block S100 of forming one or more shallow trench isolation (STI) regions in a substrate. Figure 2A and Figure 2BIn some embodiments of block S100, STI regions 102 are formed in substrate 100. Forming STI regions 102 includes, by way of example and not limitation, etching substrate 100 to form one or more trenches, depositing one or more dielectric materials (e.g., silicon oxide) to overfill the trenches in substrate 100, followed by a CMP process to planarize the one or more STI regions 102 and substrate 100.

[0159] In some embodiments, the substrate 100 may be made of: a suitable elemental semiconductor, such as silicon, diamond, or germanium; a suitable alloy or compound semiconductor, such as a Group IV compound semiconductor (silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), GeSn, SiSn, SiGeSn); a Group III-V compound semiconductor (e.g., gallium arsenide, indium gallium arsenide InGaAs, indium arsenide, indium phosphide, indium antimonide, gallium arsenide phosphide, or indium gallium phosphide); or the like. In addition, the substrate 100 may include an epitaxial layer (epi-layer) strained for performance enhancement, and / or may include a silicon-on-insulator (SOI) structure.

[0160] Replay Figure 1A The method M1 then proceeds to block S102 where a stack is formed on the substrate. Figure 2A and Figure 2B In some embodiments of block S102, a stack 104 including a first multilayer stack 106, an intermediate sacrificial layer 108, and a second multilayer stack 110 is formed above a substrate 100. The first multilayer stack 106 includes first sacrificial layers 112 and first semiconductor layers 114 that are alternately stacked. The intermediate sacrificial layer 108 is formed between the first multilayer stack 106 and the second multilayer stack 110. The second multilayer stack 110 includes second sacrificial layers 116 and second semiconductor layers 118 that are alternately stacked. In some embodiments, as will be described in more detail later, the first sacrificial layer 112, the intermediate sacrificial layer 108, and the second sacrificial layer 116 are alternately stacked. Fig. 23B , Fig.26B and Fig.28B The ones shown in the figure are removed in sequence.

[0161] The first sacrificial layer 112 has a high etch selectivity with respect to the first semiconductor layer 114 during a subsequent etching process. The etch selectivity describes the etching ratio between two different materials being etched. The second sacrificial layer 116 has a high etch selectivity with respect to the second semiconductor layer 118 during a subsequent etching process. In some embodiments, the first semiconductor layer 114 includes a material different from the material of the first sacrificial layer 112. The second semiconductor layer 118 includes a material different from the material of the second sacrificial layer 116. The first sacrificial layer 112, the second sacrificial layer 116, and the intermediate sacrificial layer 108 may include materials different from each other. The first semiconductor layer 114 and the second semiconductor layer 118 may each be selected from a candidate semiconductor material of the substrate 100. For example, the first semiconductor layer 114 and the second semiconductor layer 118 may include Si, Ge, Sn, Si 1-x Ge x ,Ge 1-y Sn y 、Si 1-x-y Ge x Sn y , III-V compound semiconductors, or the like. In some embodiments, the first semiconductor layer 114 and the second semiconductor layer 118 include the same material, such as Ge.

[0162] In some embodiments, the first sacrificial layer 112, the second sacrificial layer 116, and the middle sacrificial layer 108 include silicon germanium having different germanium atomic percentages. In some embodiments, the first semiconductor layer 114 may include germanium, and the first sacrificial layer 112 may include silicon germanium, such as Si x Ge 1-x , where x may be in the range of 0 to 1. In some embodiments, the first sacrificial layer 112 includes Si 0.2 Ge 0.8 In some embodiments, the second semiconductor layer 118 may include germanium, and the second sacrificial layer 116 may include silicon germanium, such as Si x Ge 1-x , where x may be in the range of 0 to 1. In some embodiments, the second sacrificial layer 116 includes Si 0.6 Ge 0.4 In some embodiments, the intermediate sacrificial layer includes silicon germanium, such as Si 0.4 Ge 0.6 .

[0163] In some embodiments, the first multilayer stack 106 includes three layers including a first sacrificial layer 112 and two layers of a first semiconductor layer 114. In some embodiments, the second multilayer stack 110 includes three layers including two layers of a second sacrificial layer 116 and a second semiconductor layer 118. It should be understood that the first multilayer stack 106 may include any number of first sacrificial layers 112 and first semiconductor layers 114, and the second multilayer stack 110 may include any number of second sacrificial layers 116 and second semiconductor layers 118. By way of example and not limitation of the present disclosure, the number of first semiconductor layers 114 and second semiconductor layers 118 may be in the range of about 1 to about 500.

[0164] In some embodiments, each of the multiple layers of the stack 104 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. Subsequently, the stack 104 is patterned using suitable optical lithography and etching techniques to produce a fin-like stack.

[0165] Replay Figure 1A The method 1000 then proceeds to block S104 where a dielectric layer is deposited over the substrate. Figure 3A and Figure 3BIn some embodiments of block S104, a dielectric layer 120 is deposited over the substrate 100. The dielectric layer 120 extends along the sidewalls and top surface of the stack 104 and the top surface of the STI region 102. The dielectric layer 120 is then etched using an acceptable optical lithography technique to expose the STI region 102. In some embodiments, the dielectric layer 120 may be made of silicon oxide. In some other embodiments, the dielectric layer 120 includes silicon nitride, silicon oxynitride, silicon carbide, SiOC, tetraethoxysilane (TEOS), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, or the like. Examples of low-k dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, polyparaxylene, bis-benzocyclobutenes (BCB), or polyimide. In some embodiments, dielectric layer 120 may be deposited using any suitable deposition method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, or the like. In some embodiments, dielectric layer 120 may include a material similar to that of STI region 102. For example, dielectric layer 120 and STI region 102 may both include SiO2.

[0166] Replay Figure 1A The method 1000 then proceeds to block S106 where a dummy gate structure is deposited over the dielectric layer. Figure 3A and Figure 3B In some embodiments of block S106, a dummy gate structure 122 is formed on a dielectric layer 120 above the stack 104. Forming the dummy gate structure 122 includes depositing a dummy gate material over the stack 104, followed by patterning the dummy gate material. The dummy gate material may be any acceptable electrode layer, such as polysilicon, metal, or the like. The dummy gate material may be deposited by any acceptable deposition process, such as CVD, plasma enhanced CVD (PECVD), or the like. In some embodiments, the dummy gate material is patterned using a patterned photoresist as an etch mask. The patterned photoresist may be a photoresist layer (not shown) or other mask (not shown) formed above the dummy gate material, which is formed by a spin coating technique and then patterned using an acceptable optical lithography technique.

[0167] See also Figure 4A and Figure 4B , gate spacers 124 are formed on the sidewalls of the dummy gate structure 122. In some embodiments of the gate spacer formation step, the spacer material may be conformally deposited on the dielectric layer 120, and then subsequently etched back to form the gate spacers 124. The spacer material is made of a low-k dielectric material. The low-k dielectric material has a dielectric constant (k value) less than about 3.5. Suitable materials for the low-k dielectric material may include silicon oxide, silicon nitride (e.g., Si3N4), silicon oxynitride, or the like. By way of example and not limitation, the spacer material may be formed by a suitable process, such as a deposition process. For example, the deposition process includes a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process. An anisotropic etching process, such as plasma etching, is then performed on the deposited spacer material to expose portions of the dielectric layer 120 that are not covered by the dummy gate structure 122. The portion of the spacer material on the top surface of the dummy gate structure 122 may be completely removed by this anisotropic process. A portion of the spacer material on the sidewalls of the dummy gate structure 122 may remain, thereby forming a gate spacer 124 .

[0168] Afterwards, a patterned photoresist 126 or other mask may be formed on the dielectric layer 120. In some embodiments, the patterned photoresist 126 may be formed by a spin coating technique and may then be patterned using acceptable optical lithography techniques. The dummy gate structure 122, the gate spacer 124, and a portion of the dielectric layer 120 are exposed through the openings in the patterned photoresist 126.

[0169] Replay Figure 1A The method 1000 then proceeds to block S108 where the dielectric layer 120 is etched. Figure 5A and Figure 5B In some embodiments of block S108 , the dielectric layer 120 is not covered by the patterned photoresist 126 , and the dummy gate structure 122 and the gate spacer 124 are etched by an etching process to form a trench 128 . Figure 5A The grooves 128 in the top view of FIG. 1 are connected to form a rectangular ring pattern.

[0170] Replay Figure 1A The method 1000 then proceeds to block S110 where the sidewalls of the first sacrificial layer, the second sacrificial layer, and the middle sacrificial layer are etched. Fig. 6A and Figure 6BIn some embodiments of block S110, the sidewalls of the first sacrificial layer 112, the second sacrificial layer 116, and the middle sacrificial layer 108 exposed by the trench 128 are etched to form sidewall recesses 130a between the corresponding first semiconductor layers 114, sidewall recesses 130b between the topmost layer in the first semiconductor layer 114 and the bottommost layer in the second semiconductor layer 118, and sidewall recesses 130c between the corresponding second semiconductor layers 118. Although the sidewalls of the first sacrificial layer 112, the second sacrificial layer 116, and the middle sacrificial layer 108 in the sidewall recesses 130a, 130b, 130c are Figure 6B 108, the sidewalls may be concave or convex in some other embodiments. The sidewalls may be etched using an isotropic etching process, such as wet etching or the like. The first sacrificial layer 112, the second sacrificial layer 116, and the intermediate sacrificial layer 108 may include, for example, Si 1-x Ge x In some embodiments where the first semiconductor layer 114 and the second semiconductor layer 118 include, for example, Ge, the sidewalls may be removed by a selective wet etching or a selective dry etching process to produce sidewall recesses 130a, 130b, 130c. In some embodiments, a solution of NH4OH:H2O2:H2O may be used as a solution for Si 1-x Ge x Selective wet etching of the alloy may be used for the first sacrificial layer 112, the second sacrificial layer 116, and the middle sacrificial layer 108. In other examples, the selective dry etching includes selective reactive ion etching using SF6:O2 or CF4:O2 etching chemistry, which is also a selective reactive ion etching for Si. 1-x Ge x Other suitable techniques such as inductively coupled plasma (ICP) etching techniques may also be used to remove the sidewalls of the first sacrificial layer 112 , the second sacrificial layer 116 , and the middle sacrificial layer 108 .

[0171] exist FIG. 7A to FIG. 7B In the embodiment, the inner spacer 132 is formed in the side wall recesses 130a, 130b, 130c. The inner spacer 132 can be formed by Fig. 6A and Figure 6B 128 is formed by depositing an inner spacer layer (not shown separately) over the structure in . The inner spacer 132 acts as an isolation feature between the subsequently formed epitaxial source / drain regions and the gate structure. As will be discussed in more detail below, the epitaxial source / drain regions will be formed in the trenches 128, and the first sacrificial layer 112, the second sacrificial layer 116, and the middle sacrificial layer 108 will be replaced by corresponding gate structures.

[0172] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include a material such as silicon nitride (Si3N4) or oxynitride, although any suitable material may be utilized, such as a low-dielectric constant (low-k) material having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched using a process such as RIE, NBE, or the like to form the inner spacer 132. Although the outer sidewalls of the inner spacer 132 are illustrated as being flush with the sidewalls of the first semiconductor layer 114 and the second semiconductor layer 118, the outer sidewalls of the inner spacer 132 may extend beyond the sidewalls of the first semiconductor layer 114 and the second semiconductor layer 118 or be recessed from these sidewalls. In addition, although the outer sidewalls of the inner spacer 132 are Figure 7B 1. The photoresist 126 is shown as straight in FIG. 1, but the outer sidewalls of the inner spacers 132 may be concave or convex in some other embodiments. The patterned photoresist 126 may then be removed, such as by an acceptable ashing process.

[0173] Replay Figure 1A The method 1000 then proceeds to block S112 where a dielectric layer is formed on the STI region, the dummy gate structure, and the gate spacer and then patterned. Fig. 8A and Figure 8BIn some embodiments of block S112, a dielectric layer 134 including, for example, silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), SiOC, or a low-k dielectric material is formed on the STI region 102, the gate spacer 124, and the dummy gate structure 122. In some embodiments, the dielectric layer 134 may be deposited using flowable chemical vapor deposition (FCVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), chemical vapor deposition (CVD), or the like. A photoresist 136 or other mask (not shown) may then be formed over the dielectric layer 134 using a spin coating technique, and may then be patterned using acceptable optical lithography techniques to form openings in the photoresist 136 to expose the dielectric layer 134. Next, dielectric layer 134 is patterned by an etching process through the openings in photoresist 136 such that STI regions 102 are exposed, thereby forming trenches 138. After etching dielectric layer 134, photoresist 136 may be removed, such as by an acceptable ashing process.

[0174] Replay Figure 1B The method 1000 then proceeds to block S114 where the epitaxial source / drain material is filled into the trench. Fig. 9A and Fig. 9B In some embodiments of block S114, epitaxial source / drain material 140 is deposited in trench 138 (see Figure 8B ). In other words, the epitaxial source / drain material 140 is deposited on the first sidewall and the second sidewall of the stack 104. For example, forming the epitaxial source / drain material 140 includes depositing the epitaxial source / drain material 140 to overfill the trench 138, followed by a chemical mechanical planarization (CMP) process to planarize the epitaxial source / drain material 140 so that the top surface of the dielectric layer 134 and the dummy gate structure 122 are exposed.

[0175] The epitaxial source / drain material 140 may be epitaxially grown by selective epitaxial growth using the exposed end surfaces of the first semiconductor layer 114 and the second semiconductor layer 118 as epitaxial seed layers. The epitaxial source / drain material 140 may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and / or other suitable processes. The epitaxial source / drain material 140 may be implanted with dopants to form source / drain regions, followed by annealing. In some embodiments, the epitaxial source / drain material 140 may be in-situ doped during growth. In some embodiments, the epitaxial source / drain material 140 may include any acceptable material suitable for an n-type transistor. For example, if the first semiconductor layer 114 and the second semiconductor layer 118 are Ge, the epitaxial source / drain material 140 may include a material that applies tensile strain to the first semiconductor layer 114 and the second semiconductor layer 118, such as silicon doped with an n-type dopant, to enhance electron mobility. For example, the epitaxial source / drain material 140 is phosphorus-doped silicon or arsenic-doped silicon.

[0176] Replay Figure 1B The method 1000 then proceeds to block S116 where the first portion of the epitaxial source / drain material is recessed. Fig. 10A and Fig. 10B, in some embodiments of block S116. An etching process is performed to recess a first portion of the epitaxial source / drain material 140 on a first sidewall of the stack 104, thereby producing an epitaxial source / drain region 140A. This can be achieved by a photolithography patterning process using a patterned photoresist 142. For example, the patterned photoresist 142 can be a photoresist layer (not shown) or other mask (not shown) formed by spin coating technology over the dielectric layer 134, the dummy gate structure 122, and the second portion of the epitaxial source / drain material 140 and then patterned using photolithography technology. The patterned photoresist 142 covers the second portion of the epitaxial source / drain material 140, the dielectric layer 134, and the dummy gate structure 122. The etching process used to recess the first portion of the epitaxial source / drain material 140 can be an anisotropic etching process using inductively coupled plasma (ICP) etching, reactive ion etching (RIE) and / or any other suitable etching technique. The etching process is selectively tuned to remove the epitaxial source / drain material 140 but not to remove the patterned photoresist 142. Thus, a recess 144 is formed above the top surface of the first portion of the epitaxial source / drain material 140. The patterned photoresist 142 can then be removed, such as by an acceptable etching process.

[0177] Replay Figure 1B The method 1000 then proceeds to block S118 where the second portion of the epitaxial source / drain material is recessed. Fig.11A and Fig. 11BIn some embodiments of block S118, an etching process is performed to recess a second portion of the epitaxial source / drain material 140 on the second sidewall of the stack 104, thereby producing an epitaxial source / drain region 140B. In other words, the epitaxial source / drain region 140A on the second sidewall of the stack 104 is etched back so that the epitaxial source / drain region 140A on the first sidewall of the stack 104 has a height 140AH that is different from the height 140BH of the epitaxial source / drain region 140B on the second sidewall. For example, the height 140AH is greater than the height 140BH. The epitaxial source / drain region 140A and the epitaxial source / drain region 140B have top surfaces at different heights. This can be achieved by a photolithography patterning process using a patterned photoresist 146. For example, the patterned photoresist 146 may be a photoresist layer (not shown) or other mask (not shown) formed over the dielectric layer 134, the dummy gate structure 122, and the epitaxial source / drain region 140A using a spin coating technique and then patterned using an acceptable optical lithography technique. The patterned photoresist 146 covers the epitaxial source / drain region 140A, the dielectric layer 134, and the dummy gate structure 122. The etching process used to recess the second portion of the epitaxial source / drain material 140 may be an anisotropic etching process using inductively coupled plasma (ICP) etching, reactive ion etching (RIE), and / or other suitable etching techniques. The etching process is selectively tuned to remove the epitaxial source / drain material 140 but not to remove the patterned photoresist 146. Thus, a recess 148 is formed above the top surface of the second portion of the epitaxial source / drain material 140. The patterned photoresist 146 may then be removed, such as by an acceptable ashing process.

[0178] Replay Figure 1B Then, the method 1000 proceeds to block S120 where the isolation material is filled into the recess. Fig. 12A and Fig. 12B In some embodiments of block S120, an isolation material 150 is formed in the recess 144 and the recess 148. Forming the isolation material 150 includes depositing the isolation material 150 to overfill the recesses 144 and 148, followed by a chemical mechanical planarization (CMP) process to planarize the isolation material so that the top surface of the dielectric layer 134 and the dummy gate structure 122 are exposed. For example, the isolation material 150 can be deposited using a deposition process such as a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process.

[0179] Replay Figure 1B , method 1000 then proceeds to block S122 where the first portion of isolation material 150 is recessed. Fig.13A and Fig. 13B In some embodiments of block S122, an etching process is performed to recess a first portion of the isolation material 150 on the first sidewall of the stack 104. The remaining portion of the first portion of the isolation material 150 may be referred to as a first isolation structure 150A. This may be achieved using a patterned photoresist 152 by a photolithography patterning process. For example, the patterned photoresist 152 may be a photoresist layer (not shown) or other mask (not shown) formed over the dielectric layer 134, the dummy gate structure 122, and the second portion of the isolation material 150 using a spin coating technique and then patterned using a photoresist layer that is receptive to photolithography techniques. The patterned photoresist 152 covers the second portion of the isolation material 150, the dielectric layer 134, and the dummy gate structure 122. The etching process used to recess the first portion of the isolation material 150 may be an anisotropic etching process using inductively coupled plasma (ICP) etching, reactive ion etching (RIE), and / or other suitable etching techniques. The etching process is selectively tuned to remove the isolation material 150 but not the patterned photoresist 152. Thus, a recess 154 is formed over the top surface of the first isolation structure 150A. The patterned photoresist 152 may then be removed, such as by an acceptable ashing process.

[0180] Replay Figure 1B , the method 1000 then proceeds to block S124 where the second portion of the isolation material 150 is recessed. Fig.14A and Fig. 14BIn some embodiments of block S124, the second portion of the isolation material 150 is recessed. An etching process is performed to recess the second portion of the isolation material 150 on the second sidewall of the stack 104. The remaining portion of the second portion of the isolation material 150 may be referred to as the second isolation structure 150B. This may be achieved by an optical lithography patterning process using a patterned photoresist 156. For example, the patterned photoresist 156 may be a photoresist layer (not shown) or other mask (not shown) formed over the dielectric layer 134, the dummy gate structure 122, and the first isolation structure 150A using a spin coating technique and then patterned using an optical lithography technique. The patterned photoresist 156 covers the first isolation structure 150A, the dielectric layer 134, and the dummy gate structure 122. The etching process used to recess the second portion of the isolation material 150 may be an anisotropic etching process using inductively coupled plasma (ICP) etching, reactive ion etching (RIE), and / or other suitable etching techniques. The etching process is selectively tuned to remove the isolation material 150 but not the patterned photoresist 156. Thus, a recess 158 is formed above the top surface of the second isolation structure 150B. The patterned photoresist 156 may then be removed, such as by an acceptable etching process. The resulting structure is shown in FIG. Fig.15A and Fig. 15B The first isolation structure 150A and the second isolation structure 150B have top surfaces at different heights. The second isolation structure has a top surface 150BT that is lower than the top surface 150AT of the first isolation structure 150A.

[0181] Replay Figure 1B The method 1000 then proceeds to block S126 where an epitaxial source / drain material is formed on the first isolation structure and the second isolation structure. Fig.16A and Fig. 16B. Epitaxial source / drain region 160A and epitaxial source / drain region 160B are formed on first isolation structure 150A and second isolation structure 150B, respectively. Epitaxial source / drain region 160A has a height 160AH, which is different from height 160BH of epitaxial source / drain region 160B. For example, height 160AH is less than height 160BH. Epitaxial source / drain region 160A and epitaxial source / drain region 160B have bottom surfaces at different heights. Epitaxial source / drain region 160B interfaces with the sidewall of the top layer of first semiconductor layer 114. Epitaxial source / drain regions 160A and 160B can be formed by selective epitaxial growth using end surfaces of second semiconductor layer 118 and first semiconductor layer 114 as epitaxial seed layers. The formation of the epitaxial source / drain regions 160A, 160B may be performed by using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), liquid phase epitaxy (LPE) and / or other suitable processes.

[0182] Replay Figure 1C The method 1000 then proceeds to block S128 where source / drain contacts are formed on the epitaxial source / drain material. Fig.17A and Fig. 17B In some embodiments of block S128, source / drain contacts 162 are formed on epitaxial source / drain regions 160A, 160B. Forming source / drain contacts 162 includes depositing source / drain contacts 162 to overfill recesses 154 and 158 by blanket deposition using an ALD process, a CVD process, or a PVD process, followed by a chemical mechanical planarization (CMP) process to planarize source / drain contacts 162, such that the top surfaces of dielectric layer 134 and dummy gate structure 122 are exposed and an etch-back process is performed to reduce the top surface of source / drain contacts 162. The etch-back process may be an anisotropic etching process using inductively coupled plasma (ICP) etching, reactive ion etching (RIE), and / or other suitable etching techniques. In some embodiments, the source / drain contacts 162 may be made of metal, such as cobalt (Co), tungsten (W), copper (Cu), nickel (Ni), ruthenium (Ru), or other suitable materials.

[0183] Replay Figure 1C , method 1000 then proceeds to block S130 where the dielectric layer is removed. 18A to 18C ,exist 18A to 18CIn some embodiments, the dielectric layer 134 is removed by a suitable etching process. For example, the dielectric layer 134 is removed by an isotropic etching process such as a wet etching process using a suitable etching chemistry. In such embodiments, the etchant and other etching parameters may be tuned so that certain materials of the dielectric layer 134 are etched without etching other materials, such as the dummy gate structure 122 and the gate spacer 124. In other words, a wet isotropic etch is used that is selective to the material of the dielectric layer 134.

[0184] Replay Figure 1C The method 1000 then proceeds to block S132 where the dummy gate structure and dielectric layer are removed and then a dielectric layer is deposited over the stack and STI regions. FIG. 19A to FIG. 19C In some embodiments of block S132, the dummy gate structure 122 and the dielectric layer 120 (see Fig.18C ) is removed. A dielectric layer 164 is formed on the stack 104 and the STI region 102. For example, forming the dielectric layer 164 includes depositing the dielectric layer 164 so as to cover the source / drain contacts 162, followed by a chemical mechanical planarization (CMP) process to planarize the dielectric layer 164 to obtain a dielectric layer 164 having a desired thickness. In some embodiments, after planarizing the dielectric layer 164, the dielectric layer 164 covers the source / drain contacts 162 to protect the source / drain contacts 162 from being damaged or oxidized by subsequent processes. In some embodiments, the dielectric layer 164 is made of a low-k dielectric material. The low-k dielectric material has a dielectric constant (k value) less than about 3.5. Suitable materials for the low-k dielectric material may include SiOC, silicon oxide, silicon nitride, silicon oxynitride, or the like. By way of example and not limitation, the dielectric material may be formed using a process such as a CVD process, a subatmospheric CVD (SACVD) process, a flow CVD process, an ALD process, a physical vapor deposition (PVD) process, or other suitable process.

[0185] Replay Figure 1C The method 1000 then proceeds to block S134 where the dielectric layer is patterned. Fig. 20A and Fig. 20BIn some embodiments of block S134, the dielectric layer 164 is patterned to form a first trench 166 extending through the dielectric layer 164 to expose the first sidewall of the stack 104. For example, a patterned mask (not shown) may be formed over the dielectric layer 164 using a photolithography process, and then the dielectric layer 164 is etched by a suitable etching process using the patterned mask as an etching mask. The photolithography process may include photoresist (or resist) coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and / or combinations thereof. The etching process includes dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). After forming the first trench 166, the patterned mask may be removed by a suitable technique, such as an etching process. In some embodiments, the first trench 166 may be interchangeably referred to as a first opening.

[0186] Replay Figure 1C The method 1000 then proceeds to block S136 where a protection layer is formed in the first trench and then the sidewalls of the second semiconductor layer are etched. Fig.21A and Fig. 21B In some embodiments of block S136, a protection layer 168 is formed in the first trench 166 to cover the first multilayer stack 106. The protection layer 168 can protect the first multilayer stack 106 from being etched during the etching of the sidewalls of the second semiconductor layer 118. In other words, during the etching of the sidewalls of the second semiconductor layer 118, the sidewalls of the second semiconductor layer 118 are etched without etching the first semiconductor layer 114. The sidewalls of the second semiconductor layer 118 of the second multilayer stack 110 exposed by the protection layer 168 are etched to form sidewall recesses 170 between the corresponding second sacrificial layers 116. Although the sidewalls of the second semiconductor layer 118 in the sidewall recesses 170 are Fig. 21B Shown as straight in FIG, the sidewalls may be concave or convex in some other embodiments.

[0187] The sidewalls of the second semiconductor layer 118 may be removed or etched using an etchant that selectively etches the second semiconductor layer 118 relative to the second sacrificial layer 116. For example, when the second semiconductor layer 118 is formed of Ge and the second sacrificial layer 116 is formed of SiGe, the second semiconductor layer 118 may be selectively removed using a thermal etching technique using a gaseous mixture of HCl and H2, or a dry etching technique using plasma such as CF4, or a wet etching technique such as using, but not limited to, a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and acetic acid (CH3COOH).

[0188] Replay Figure 1CThe method 1000 then proceeds to block S138 where an inner spacer is formed in the sidewall recess. Fig.22A and Fig. 22B In some embodiments of block S138, the inner spacer 172 is formed in the sidewall recess 170 (see Fig. 21B ). The internal spacer 172 can be formed by Fig.21A and Fig. 21B The first sacrificial layer 166 is formed by depositing an inner spacer layer (not separately shown) over the structure in FIG. The inner spacer 172 acts as an isolation feature between a subsequently formed gate structure and the second semiconductor layer 118. As will be discussed in more detail below, a gate structure will be formed in the first trench 166, and the first sacrificial layer will be replaced by a corresponding gate structure.

[0189] The inner spacer layer may be deposited by a conformal deposition process such as CVD, ALD, or the like. The inner spacer layer may include a material such as SiBCN. In some embodiments, the inner spacer layer may include other low-dielectric constant (low-k) materials having a k value of less than about 3.5. The inner spacer layer may then be anisotropically etched, such as using RIE, NBE, or the like, to form inner spacers 172. Although the outer sidewalls of the inner spacer 172 are shown as being flush with the sidewalls of the second sacrificial layer 116, the outer sidewalls of the inner spacer 172 may extend beyond the sidewalls of the second sacrificial layer 116 or be recessed from these sidewalls. The protective layer 168 is then removed. In some embodiments, the protective layer 168 is removed during the etching process of anisotropically etching the inner spacer layer.

[0190] Replay Figure 1C , method 1000 then proceeds to block S140 where the first sacrificial layer is removed. FIG. 23A to FIG. 23C In some embodiments of block S140, the first multilayer stack 106 (see Fig. 22B ) in the first sacrificial layer 112 (see Fig. 22B ) is removed by an isotropic etching process such as wet etching or the like using an etchant that is selective to the material of the first sacrificial layer 112. In other words, the first sacrificial layer 112 is removed by using a selective etching process that etches the first sacrificial layer 112 at a faster etching rate than the etching rate at which it etches the first semiconductor layer 114, thereby forming a space between the first semiconductor layers 114 (if the first semiconductor layer 114 is a nanosheet, the space is also referred to as an inter-sheet space). The first semiconductor layers 114 are arranged above each other over the substrate 100. This step may be referred to as a channel release process. Fig. 23BAs shown in FIG. 1 , gaps 174 (empty spaces) are formed between the first semiconductor layers 114. At this intermediate processing step, the gaps 174 between the first semiconductor layers 114 may be filled with ambient conditions (eg, air, nitrogen, etc.).

[0191] In some embodiments, the first semiconductor layer 114 may be referred to as a nanosheet, a nanowire, a nanoslat, a nanoring having a nanoscale size (e.g., a few nanometers), depending on its geometric dimensions. For example, in some embodiments, due to the selective etching process that completely removes the first sacrificial layer 112, the first semiconductor layer 114 may be trimmed to have a substantially circular shape (i.e., a cylindrical shape). In this case, the resulting first semiconductor layer 114 may be referred to as a semiconductor nanowire. For example, the nanowire may have a diameter ranging from 0.5 nm to 50 nm. In some other embodiments, the geometry of the cross-sectional view along the BB' line may be a rectangle, a square, a diamond with or without rounded corners; a circle or an ellipse. In some embodiments, the first semiconductor layer 114 may have substantially the same or different thicknesses. For example, the first semiconductor layer 114 may have a thickness ranging from 0.5 nm to 50 nm. The first semiconductor layer 114 may have a vertical distance d ranging from 3 nm to 100 nm between. In some embodiments, the vertical distances d between adjacent first semiconductor layers 114 may be different or substantially the same. In some other embodiments, the number of first semiconductor layers 114 may be in the range of 1 to 100.

[0192] Replay Figure 1D The method 1000 then proceeds to block S142 where a first metal gate structure is formed in the first trench and the gap. FIG. 24A to FIG. 24C In some embodiments of block S142, the first metal gate structure 176 is formed between the first trench 166 and the gap 174 (see Fig. 23B ). The first metal gate structure 176 covers the first semiconductor layer 114. Since the first metal gate structure 176 inherits the shape of the first sacrificial layer 112 (see Fig. 22B), it can be inferred that the first sacrificial layer 112 is replaced by the first metal gate structure 176. Each of the internal spacers 172 is horizontally between the first metal gate structure 176 and the corresponding semiconductor layer of the second semiconductor layer 118 to separate the first metal gate structure 176 from the corresponding semiconductor layer of the second semiconductor layer 118. In some embodiments, the first metal gate structure 176 includes an interface layer 178, a gate dielectric layer 180, a work function layer 182, and a filling metal 184. For example, the interface layer 178, the gate dielectric layer 180, and the work function layer 182 are blanket formed in the gap 174 and the first trench 166 in sequence. Subsequently, the filling metal 184 is deposited over the work function layer 182 to fill the remaining space of the first trench 166. A CMP process is then performed on the interface layer 178, the gate dielectric layer 180, the work function layer 182, and the fill metal 184 until the dielectric layer 164 is exposed, thereby causing the dielectric layer 164, the interface layer 178, the gate dielectric layer 180, the work function layer 182, and the fill metal 184 to have substantially flat top surfaces.

[0193] In some embodiments, the interfacial layer 178 is a silicon oxide layer deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, or the like. In some embodiments, the gate dielectric layer 180 may include a high-k dielectric material, other suitable dielectric materials, or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, hafnium dioxide-aluminum oxide (HfO2-Al2O3) alloys, the like, or combinations thereof.

[0194] In some embodiments, the work function layer 182 includes one or more n-type work function layers that can fill the remaining space of the gap 174. The one or more n-type work function layers may include one or more n-type work function metals (N-metals). The n-type work function metal may illustratively include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials.

[0195] In some embodiments, fill metal 184 includes a metal such as tungsten. In some other embodiments, the fill metal 184 may illustratively include, but is not limited to, titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum carbon nitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC), aluminides, and / or other suitable materials. In alternative embodiments, the fill metal 184 may include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), silver (Ag), gold (Au), conductive metal oxides, and / or other suitable materials. In some embodiments, the fill metal 184 may be deposited using any suitable method, such as CVD, physical vapor deposition (PVD), ALD, PEALD, PECVD, SACVD, FCVD, spin coating, or the like.

[0196] Replay Figure 1D The method 1000 then proceeds to block S144 where the dielectric layer is patterned. Fig.25A and Fig.25B In some embodiments of block S144, the dielectric layer 164 is patterned to form a second trench 186, which extends through the dielectric layer 164 to expose the sidewalls of the second multilayer stack 110, the first metal gate structure 176, the intermediate sacrificial layer 108, and the first semiconductor layer 114, and the top surface of the STI region 102. For example, a patterned mask (not shown) can be formed over the dielectric layer 164 using a photolithography process, and then the dielectric layer 164 is etched by a suitable etching process using the patterned mask as an etching mask. The photolithography process may include photoresist (or resist) coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), other suitable processes, and / or combinations thereof. The etching process includes dry etching, wet etching, and / or other etching methods (e.g., reactive ion etching). After forming the second trench 186, the patterned mask may be removed by a suitable technique, such as an ashing process. In some embodiments, the second trench 186 may be interchangeably referred to as a second opening.

[0197] Replay Figure 1D , method 1000 then proceeds to block S146 where the middle sacrificial layer is removed. FIG. 26A to FIG. 26CIn some embodiments of block S146, the middle sacrificial layer 108 is removed using an etchant that selectively etches the middle sacrificial layer 108 relative to the second sacrificial layer 116, the first semiconductor layer 114, and the second semiconductor layer 118. A gap 188 is formed between the first metal gate structure 176 and the bottommost sacrificial layer of the second sacrificial layer 116.

[0198] Replay Figure 1D The method 1000 then proceeds to block S148 where a spacer material is formed between the gap and the second trench. FIG. 27A to FIG. 27C In some embodiments of block S148, spacer material 190 is formed in gap 188 (see Fig.26B ) and the second trench 186. In some embodiments, the inner spacer 172 has a height 172H extending in a direction perpendicular to the substrate 100, the height 172H being less than a maximum height 190H of the spacer material 190 extending in a direction perpendicular to the substrate 100. The spacer material 190 is wider than the inner spacer 172 in the y-axis. In some embodiments, the inner spacer 172 has a width 172W in the y-axis direction, which is less than a width 190W of the spacer material 190 in the y-axis. The spacer material 190 is a low-k dielectric layer, such as a nitride layer (e.g., a silicon carbon boron nitride (SiBCN) layer). By way of example and not limitation, forming the spacer material 190 includes depositing the spacer material 190 to overfill the second trench 186, followed by a CMP process to planarize the spacer material 190 through the first metal gate structure 176 and the dielectric layer 164. Next, an etching process is performed to recess the spacer material 190. The etching process may be an anisotropic etch, such as RIE or dry etching. In some embodiments, the etching process is highly selective to the spacer material 190. Thus, a recess is formed over the top surface of the spacer material 190.

[0199] Replay Figure 1D , method 1000 then proceeds to block S150 where the second sacrificial layer is removed. FIG. 28A to FIG. 28C In some embodiments of block S150, the dielectric layer 164 on the second multilayer stack 110 is removed, and then the second multilayer stack 110 is removed (see Fig.27B ) in the second sacrificial layer 116 (see Fig.27B ). For example, the dielectric layer 164 is patterned by using a suitable optical lithography and etching process to expose the top surface of the topmost sacrificial layer of the second sacrificial layer 116 .

[0200] Then, in some embodiments, the second sacrificial layer 116 (see Fig.27B) may be removed by an isotropic etching process such as wet etching or the like using an etchant that is selective to the material of the second sacrificial layer 116. In other words, the second sacrificial layer 116 is removed by using a selective etching process that etches the second sacrificial layer 116 at a faster etching rate than the etching rate at which it etches the second semiconductor layer 118, thereby forming a space between the second semiconductor layers 118 (if the second semiconductor layer 118 is a nanosheet, the space is also referred to as a sheet space). The second semiconductor layers 118 are arranged above each other over the substrate 100. This step may be referred to as a channel release process. As Fig.28B As shown in , gaps 192 (empty spaces) are formed between the second semiconductor layers 118. At this intermediate processing step, the gaps 192 between the second semiconductor layers 118 may be filled with ambient conditions (eg, air, nitrogen, etc.).

[0201] In some embodiments, depending on its geometric size, the second semiconductor layer 118 may be referred to as a nanosheet, a nanowire, a nanoslat, a nanoring having a nanoscale size (e.g., a few nanometers). The geometry of the second semiconductor layer 118 may be similar to that of the first semiconductor layer 114, and thus its description is omitted herein for simplicity.

[0202] Replay Figure 1D The method 1000 then proceeds to block S152 where a second metal gate structure is formed in the second trench and the gap. FIG. 29A to FIG. 29C In some embodiments of block S152, a second metal gate structure 194 is formed in the second trench 186 and the gap 192. The second metal gate structure 194 covers the second semiconductor layer 118. Since the second metal gate structure 194 inherits the shape of the second sacrificial layer 116 (see Fig.27B), it can be inferred that the second sacrificial layer 116 is replaced by the second metal gate structure 194. The second metal gate structure 194 is separated from the first metal gate structure 176. The spacer material 190 extends along the sidewalls of the first semiconductor layer 114 and the bottom surface of the second metal gate structure 194, thereby separating the first metal gate structure 176 from the second metal gate structure 194. In some embodiments, the second metal gate structure 194 includes an interface layer 196, a gate dielectric layer 198, a work function layer 200, and a filling metal 202. For example, the interface layer 196, the gate dielectric layer 198, and the work function layer 200 are blanket formed in the second trench 186 and the gap 192 in sequence. Subsequently, the filling metal 202 is deposited over the work function layer 200, thereby filling the remaining space of the second trench 186. CMP is then performed on fill metal 202 until dielectric layer 164 and first metal gate structure 176 are exposed, resulting in the layers of dielectric layer 164, interface layer 196, gate dielectric layer 198, work function layer 200, fill metal 202, and first metal gate structure 176 having substantially planar top surfaces.

[0203] In some embodiments, the interface layer 196, the gate dielectric layer 198, the work function layer 200 and the fill metal 2021 may be similar in composition and formation to the interface layer 178, the gate dielectric layer 180, the work function layer 182 and the fill metal 184, respectively. Therefore, their description is omitted herein for simplicity.

[0204] When viewed from the cross-sectional view, the first metal gate structure 176 has a height 176H, and the second metal gate structure 194 has a height 194H different from the height 176H. For example, the height 194H is less than the height 176H. When viewed from the top view, the second metal gate structure 194 has a top surface area different from the top surface area of ​​the first metal gate structure 176. For example, when viewed from the top view, the top surface area of ​​the second metal gate structure 194 is greater than the top surface area of ​​the first metal gate structure 176.

[0205] The source / drain contacts 162, the first metal gate structure 176, and the second metal gate structure 194 spaced apart in a first direction (i.e., the x-axis) are disposed between the source / drain contacts 162, and in a second direction (i.e., the y-axis) perpendicular to the first direction (i.e., the x-axis), the second metal gate structure 194 has a length 194L greater than a length 176L of the first metal gate structure 176. When viewed from a top view, the first metal gate structure 176 has a width 176W along the x-axis, which is substantially the same as a width 194W of the second metal gate structure 194 along the x-axis. In some embodiments, the first semiconductor layer 114 has a width 114W along the y-axis, which is different from a width 118W of the plurality of second semiconductor layers 118 along the y-axis. For example, the first semiconductor layer 114 has a width 114W along the y-axis, which is greater than a width 118W of the second semiconductor layer 118 along the y-axis.

[0206] Fig.29D Similar to Fig.29B , except that circuit reference numbers are marked for use in discussing the circuit diagrams. Fig.29E According to some embodiments of the present disclosure FIG. 29A to FIG. 29D An exemplary circuit diagram of vertically stacked transistors in an integrated circuit of FIG. 1 is shown in FIG. 1 . The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. See FIG. Fig.29A and Fig.29E The vertically stacked transistors include a first transistor T1 , a second transistor T2 , a third transistor T3 , and a fourth transistor T4 that collectively function as a power amplifier (PA) 300 such as a cascade amplifier.

[0207] For example, the lower semiconductor layer in the first semiconductor layer 114 serves as a channel of the first transistor T1 and may be referred to as the first channel CH1, and the upper semiconductor layer of the first semiconductor layer 114 serves as a channel of the second transistor T2 and may be referred to as the second channel CH2. The epitaxial source / drain region 140B connected to the first channel CH1 is the drain D1 of the first transistor T1 and is coupled to the high power supply voltage VDD. The lower portion of the epitaxial source / drain region 140A is connected to the first channel CH1 and may therefore serve as the source S1 of the first transistor T1. The source S1 and the drain D1 are on opposite sides of the first channel CH1. The upper portion of the epitaxial source / drain region 140A is connected to the second channel CH2 and may therefore serve as the drain D2 of the second transistor T2. The epitaxial source / drain region 160B connected to the second channel CH2 is the source S2 of the second transistor T2. The source S2 and the drain D2 are on opposite sides of the second channel CH2. In some embodiments, the source S1 and the drain D2 share a common epitaxial structure because the source S1 and the drain D2 are formed in a common epitaxial source / drain region 140A. Since the epitaxial source / drain region 140B and the epitaxial source / drain region 160B are separated from each other by the second isolation structure 150B, the epitaxial source / drain region 140B is vertically isolated from the epitaxial source / drain region 160B. Therefore, the drain D1 of the first transistor T1 is isolated from the source S2 of the second transistor T2, but the source S1 of the first transistor T1 is electrically coupled to the drain D2 of the second transistor T2, so that the first transistor T1 is connected in series with the second transistor T2.

[0208] The second transistor T2 is above the first transistor T1. The first transistor T1 and the second transistor T2 are connected in series with the third transistor T3 and the fourth transistor T4. In some embodiments, the lower semiconductor layer in the second semiconductor layer 118 serves as a channel of the third transistor T3 and may be referred to as the third channel CH3, and the upper semiconductor layer of the second semiconductor layer 118 serves as a channel of the fourth transistor T4 and may be referred to as the fourth channel CH4. The spacer material 190 is vertically between the second channel CH2 and the third channel CH3. The middle portion of the epitaxial source / drain region 160B is connected to the third channel CH3 and may therefore serve as the drain D3 of the third transistor T3. The lower portion of the epitaxial source / drain region 160A is connected to the third channel CH3 and may therefore serve as the source S3 of the third transistor T3, which is coupled to the low power supply voltage VSS. The source S3 and the drain D3 are on opposite sides of the third channel CH3. The first isolation structure 150A is vertically disposed between the drain D2 and the source S3. The upper portion of the epitaxial source / drain region 160A is connected to the fourth channel CH4, and can therefore serve as the source S4 of the fourth transistor T4, which is coupled to the low power supply voltage VSS. The upper portion of the epitaxial source / drain region 160B is connected to the fourth channel CH4, and can therefore serve as the drain D4 of the fourth transistor T4. That is, the drain D4 and the drain D3 share a common epitaxial structure. The source S4 and the drain D4 are on opposite sides of the fourth channel CH4. Therefore, the third transistor T3 can be connected in parallel with the fourth transistor T4.

[0209] The third transistor T3 and the fourth transistor T4 are preamplifiers of variable gain amplifiers and have a wide power spectrum. An input signal (i.e., a gain control signal) 304 may be generated and used to control the gain of the third transistor T3 and the fourth transistor T4 to achieve a desired gain. The third transistor T3 and the fourth transistor T4 generate a pre-amplified signal 302 that is passed through the second transistor T2. The gain of the third transistor T3 and the fourth transistor T4 is variable so as to provide a first amount of gain according to the desired output power level of the amplified output signal 306. The first transistor T1 and the second transistor T2 may be biased by a control voltage 308 to control the impedance at the node 310. The first transistor T1 and the second transistor T2 then amplify the pre-amplified signal 302 to generate an amplified output signal 306, thereby providing the remainder of the required gain and power amplification. The amplified output signal 306 at the node 310 is the product of the current passed through the first transistor T1 and the impedance at the node 310.

[0210] As previously discussed, by disposing the second isolation structure 150B between the epitaxial source / drain region 140B and the epitaxial source / drain region 140B, the first transistor T1 can be connected in series with the second transistor T2. Because the first transistor T1 is connected in series with the second transistor T2, the effective gate length of the combination of the first transistor T1 and the second transistor T2 increases. The effective gate length of the combination of the first transistor T1 and the second transistor T2 is different from the effective gate length of the third transistor T3 or the effective gate length of the fourth transistor T4. The increased effective gate length can provide an increased output resistance, which allows an increased control voltage 308 and is beneficial for the transistor array of the power amplifier 300 to provide high output power. The first transistor T1 can allow a high voltage swing at the node 310. Since the first transistor T1 and the second transistor T2 are stacked vertically, the footprint of the power amplifier 300 is not increased. That is, the power amplifier 300 can have a small array size and a reduced distance of electrical wiring, thereby causing a reduced parasitic capacitance.

[0211] The source S2 of the second transistor T2 (i.e., the lower portion of the epitaxial source / drain region 160B) and the drain D3 of the third transistor T3 (i.e., the middle portion of the epitaxial source / drain region 160B) are formed in a common epitaxial source / drain region. Because the source S2 of the second transistor T2 (i.e., the lower portion of the epitaxial source / drain region 160B) and the drain D3 of the third transistor T3 (i.e., the middle portion of the epitaxial source / drain region 160B) share a common epitaxial structure, no additional metal wiring is required to connect the source S2 and the drain D3 together. Therefore, the metal wiring resistance and contact resistance between the source / drain connection can be omitted. Therefore, high performance of the power amplifier 300 under radio frequency (RF) can be achieved.

[0212] In the configuration of the power amplifier 300, the first transistor T1 and the second transistor T2 allow a high voltage swing at the node 310, and the third transistor T3 and the fourth transistor T4 provide gain. In some embodiments where the first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are n-type transistors, a transistor stack to achieve vertically stacked high power nFETs and high gain nFETs is achieved.

[0213] Based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no specific advantages are required for all embodiments. The present disclosure provides an integrated circuit in various embodiments, which includes transistors stacked vertically on a semiconductor substrate. One advantage is that an isolation structure is formed between the epitaxial source / drain regions of the vertically stacked transistors, thereby allowing the transistors to be connected in series with each other without increasing the footprint of the integrated circuit. Another advantage is that because the source of the second transistor (i.e., the lower portion of the epitaxial source / drain region) and the drain of the third transistor (i.e., the middle portion of the epitaxial source / drain region) share a common epitaxial structure, no additional metal wiring is required to connect the second transistor and the third transistor together. Therefore, the metal wiring resistance and contact resistance between the source / drain connection can be omitted. High performance can therefore be achieved at the radio frequency (RF) of the power amplifier.

[0214] In some embodiments, a device includes a semiconductor substrate, a first transistor, a second transistor above the first transistor, and a first isolation structure. The first transistor is on the semiconductor substrate. The first transistor includes a first channel, a first source and a first drain. The first source and the first drain are on opposite sides of the first channel. The second transistor includes a second channel, a second source and a second drain. The second source and the second drain are on opposite sides of the second channel. The first transistor is connected in series with the second transistor. The first isolation structure is vertically between the first drain and the second source. In some embodiments, the first source and the second drain share a common epitaxial structure. In some embodiments, the device further includes a third transistor above the second transistor. The third transistor includes a third channel, a third drain and a third source. The third drain and the third source are on opposite sides of the third channel. The third drain and the second source share a common epitaxial structure. In some embodiments, the device further includes a fourth transistor above the third transistor. The fourth transistor includes a fourth channel, a fourth drain and a fourth source. The fourth drain and the fourth source are on opposite sides of the fourth channel. The fourth drain and the third drain share a common epitaxial structure. In some embodiments, the fourth source and the third source share a common epitaxial structure. In some embodiments, the device further includes a second isolation structure vertically between the second drain and the third source. In some embodiments, the device further includes a spacer material vertically between the second channel and the third channel. In some embodiments, the spacer material extends along a sidewall of the first channel and a sidewall of the second channel.

[0215] In some embodiments, a device includes a substrate, a plurality of first semiconductor layers, a first metal gate structure, a plurality of second semiconductor layers, and a second metal gate structure. The first semiconductor layers are arranged above each other above the substrate. The first metal gate structure covers the first semiconductor layer. The second semiconductor layer is arranged above each other above the substrate. The second metal gate structure covers the second semiconductor layer and is separated from the first metal gate structure. When viewed from a cross-sectional view, the first metal gate structure has a first height, and the second metal gate structure has a second height less than the first height. When viewed from a top view, the second metal gate structure has a top surface area different from the top surface area of ​​the first metal gate structure. In some embodiments, the device further includes a plurality of first epitaxial structures disposed on opposite sides of the first semiconductor layer, and wherein the first epitaxial structure has a plurality of top surfaces at different heights. In some embodiments, the device further includes a first isolation structure and a second isolation structure. The first isolation structure is on a first one of the first epitaxial structures. The second isolation structure is on a second one of the first epitaxial structures. The first isolation structure and the second isolation structure have top surfaces at different heights. In some embodiments, the device further includes a plurality of second epitaxial structures disposed on opposite sides of the second semiconductor layer. The second epitaxial structure has multiple bottom surfaces at different heights. In some embodiments, one of the second epitaxial structures is in contact with a sidewall of the topmost one of the first semiconductor layer. In some embodiments, the device further includes a spacer material extending along multiple sidewalls of the first semiconductor layer and the bottom surface of the second metal gate structure. In some embodiments, the device further includes an internal spacer that separates the first metal gate structure from the second semiconductor layer. In some embodiments, the spacer material is wider than the internal spacer when viewed from the cross-sectional view. In some embodiments, the internal spacer has a height less than the maximum height of the spacer material when viewed from the cross-sectional view.

[0216] In some embodiments, a method of forming a device includes the following steps. A stack is formed on a semiconductor substrate. The stack includes a first multilayer stack, a first sacrificial layer, and a second multilayer stack stacked in sequence on the semiconductor substrate. The first multilayer stack includes a plurality of first semiconductor layers and a plurality of second sacrificial layers stacked alternately. The second multilayer stack includes a plurality of second semiconductor layers and a third sacrificial layer stacked alternately. A first epitaxial source / drain region and a second epitaxial source / drain region are formed on the semiconductor substrate. The first epitaxial source / drain region and the second epitaxial source / drain region are respectively on opposite sidewalls of the stack. The first epitaxial source / drain region has a height greater than the height of the second epitaxial source / drain region. The second sacrificial layer is replaced with a first metal gate structure. The third sacrificial layer is replaced with a second metal gate structure. In some embodiments, the method further includes the following steps. Before replacing the third sacrificial layer with the second metal gate structure, multiple sidewalls of the second semiconductor layer are etched without etching the first semiconductor layer. Multiple internal spacers are formed on the etched sidewalls of the second semiconductor layer. In some embodiments, the method further includes the following steps. A first isolation structure is formed above the first epitaxial source / drain region, and a second isolation structure is formed above the second epitaxial source / drain region. A third epitaxial source / drain region is formed above the first isolation structure, and a fourth epitaxial source / drain region is formed above the second isolation structure. The third epitaxial source / drain region has a height greater than a height of the fourth epitaxial source / drain region.

[0217] In some embodiments, a semiconductor device includes a semiconductor substrate, a plurality of first semiconductor layers, and a first epitaxial source / drain region and a second epitaxial source / drain region, wherein the first semiconductor layers are arranged above each other above the semiconductor substrate. The first epitaxial source / drain region and the second epitaxial source / drain region are on the semiconductor substrate, wherein the first epitaxial source / drain region and the second epitaxial source / drain region are respectively on opposite sidewalls of the stack, and the first epitaxial source / drain region has a height greater than the height of the second epitaxial source / drain region. In some embodiments, the semiconductor device further includes a first isolation structure and a second isolation structure, wherein the first isolation structure is above the first epitaxial source / drain region, and the second isolation structure is above the second epitaxial source / drain region. In some embodiments, the semiconductor device further includes a third epitaxial source / drain region and a fourth epitaxial source / drain region. The third epitaxial source / drain region is above the first isolation structure, and the fourth epitaxial source / drain region is above the second isolation structure, wherein the third epitaxial source / drain region has a height less than the height of the fourth epitaxial source / drain region.

[0218] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and such equivalent constructions may be variously modified, substituted, and replaced herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: Include: a semiconductor substrate; a first transistor on the semiconductor substrate, wherein the first transistor comprises a first channel, a first source and a first drain, the first source and the first drain being on opposite sides of the first channel; a second transistor above the first transistor, wherein the second transistor comprises a second channel, a second source and a second drain, the second source and the second drain being on opposite sides of the second channel; and A first isolation structure is vertically disposed between the first drain and the second source.

2. The semiconductor device according to claim 1, wherein One of the first source and the first drain of the first transistor and one of the second source and the second drain of the second transistor share a common epitaxial structure.

3. The semiconductor device according to claim 1, wherein: Further including: A third transistor above the second transistor, wherein the third transistor includes a third channel, a third drain and a third source, the third drain and the third source are on opposite sides of the third channel, and one of the third source and the third drain of the third transistor shares a common epitaxial structure with one of the second source and the second drain of the second transistor.

4. The semiconductor device according to claim 3, wherein: Further including: A fourth transistor above the third transistor, wherein the fourth transistor includes a fourth channel, a fourth drain and a fourth source, the fourth drain and the fourth source are on opposite sides of the fourth channel, and one of the fourth source and the fourth drain of the fourth transistor shares a common epitaxial structure with one of the third source and the third drain of the third transistor.

5. A semiconductor device, characterized in that: Include: a substrate; a plurality of first semiconductor layers disposed above each other above the substrate; a first metal gate structure covering the plurality of first semiconductor layers; a plurality of second semiconductor layers disposed above each other above the substrate; and A second metal gate structure encapsulating the plurality of second semiconductor layers and separated from the first metal gate structure, wherein when viewed from a cross-sectional view, the first metal gate structure has a first height, the second metal gate structure has a second height less than the first height, and wherein when viewed from a top view, the second metal gate structure has a top surface area different from a top surface area of ​​the first metal gate structure.

6. The semiconductor device according to claim 5, wherein: Further including: A plurality of first epitaxial structures are disposed on opposite sides of the plurality of first semiconductor layers, and wherein the plurality of first epitaxial structures have a plurality of top surfaces at different heights.

7. The semiconductor device according to claim 6, wherein: Further including: a first isolation structure on a first one of the plurality of first epitaxial structures; and A second isolation structure is provided on a second one of the plurality of first epitaxial structures, wherein the first isolation structure and the second isolation structure have top surfaces at different heights.

8. A semiconductor device, characterized in that: Include: a semiconductor substrate; a plurality of first semiconductor layers disposed above each other above the semiconductor substrate; as well as A first epitaxial source / drain region and a second epitaxial source / drain region are on the semiconductor substrate, wherein the first epitaxial source / drain region and the second epitaxial source / drain region are respectively on opposite side walls of the plurality of first semiconductor layers, and the first epitaxial source / drain region has a height greater than a height of the second epitaxial source / drain region.

9. The semiconductor device according to claim 8, wherein: Further including: a first isolation structure above the first epitaxial source / drain region; and A second isolation structure is above the second epitaxial source / drain region.

10. The semiconductor device according to claim 9, wherein: Further including: a third epitaxial source / drain region above the first isolation structure; and A fourth epitaxial source / drain region is above the second isolation structure, wherein the third epitaxial source / drain region has a height less than a height of the fourth epitaxial source / drain region.

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