Semiconductor device

Abstract

The semiconductor device includes a first fully-wound gate field effect transistor and a second fully-wound gate field effect transistor. And a wall fin located between the first fully-wound gate field effect transistor and the second fully-wound gate field effect transistor and located on the isolation insulating layer. The wall fin includes a first dielectric layer, a second dielectric layer on the first dielectric layer, and a third dielectric layer. The first dielectric layer, the second dielectric layer and the third dielectric layer are made of different materials; and the third dielectric layer includes a recess.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a method of physically and electrically separating adjacent source / drain epitaxial layers using a wall fin structure (such as a dielectric dummy fin structure) and defining the shape of the source / drain epitaxial layers. Background Art

[0002] As the semiconductor industry progresses to nanometer technology manufacturing nodes for higher device density, higher performance, and lower cost, challenges from manufacturing and design issues have led to the development of three-dimensional designs, such as multi-gate field effect transistors such as fin field effect transistors and all-around gate field effect transistors. Summary of the invention

[0003] In another embodiment of the present invention, a semiconductor device includes: a first fully wrapped gate field effect transistor and a second fully wrapped gate field effect transistor; and a wall fin located between the first fully wrapped gate field effect transistor and the second fully wrapped gate field effect transistor and located on an isolation insulating layer. The wall fin includes a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer; the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are different from each other; and the third dielectric layer includes a recess.

[0004] In one embodiment, a ratio of the width of the third dielectric layer to the width of the recess is about 1.5 to about 3.5.

[0005] In one embodiment, the width of the third dielectric layer is 14 nm to 40 nm, and the width of the recess is 8 nm to 12 nm.

[0006] In one embodiment, the depth of the recess is 13 nm to 22 nm.

[0007] In one embodiment, the height of the third dielectric layer is 30 nm to 33 nm.

[0008] In one embodiment, a refill material is further included in the recess.

[0009] In one embodiment, the first dielectric layer is U-shaped.

[0010] In one embodiment, the thickness of the first dielectric layer is 2.5 nm to 20 nm.

[0011] In one embodiment, the thickness of the second dielectric layer is 60 nm to 500 nm.

[0012] In one embodiment, the recess corresponds to a cut metal gate region between the first all-around gate field effect transistor and the second all-around gate field effect transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 , 2 , 3, 4, 5, 6, 7, and 8 are cross-sectional views of various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0014] Fig. 9A , 9B , 9C, and 9D are various drawings showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0015] Fig. 10A , 10B , and 10C are various drawings showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0016] Fig.11A , 11B , and 11C are various drawings showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0017] Fig. 12A , 12B , and 12C are various drawings showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0018] Fig.13A , 13B , 13C, and 13D are various diagrams showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0019] Fig.14A , 14B , and 14C are various drawings showing one of the various stages of manufacturing a semiconductor field effect transistor device in one embodiment of the present invention.

[0020] Fig.15 This is a deposition and patterning process for forming an opening in a hard mask layer in one embodiment of the present invention.

[0021] Fig.16 In one embodiment of the present invention, the process is to transfer the pattern of the photoresist layer to the hard mask layer to form an opening pattern passing through the hard mask layer.

[0022] Fig.17 This is an etching process for cutting a metal gate in one embodiment of the utility model.

[0023] Fig.18 In one embodiment of the present invention, a process is provided for depositing a material including a hard mask layer on a cut metal gate and then filling a material on the cut metal gate opening.

[0024] Fig.19In one embodiment of the utility model, the Fig.18 A continuous diffusion process on a polysilicon edge is performed on a semiconductor device fabricated in FIG.

[0025] Fig. 20 This is a process for etching the gate and the first semiconductor layer and the second semiconductor layer thereunder in one embodiment of the utility model.

[0026] Fig.21 Displays the stack offset.

[0027] Fig.22A , 22B , 22C, 22D, and 22E are various diagrams showing various stages of forming a semiconductor device having a wider third dielectric layer in one embodiment of the present invention.

[0028] Fig.23 The invention relates to a semiconductor device having a wider third dielectric layer after a metal gate etching process and a deposited metal gate is filled with a material.

[0029] Fig.24 It is matched with Fig. 20 The process described is to form a groove in Fig.23 FIG. 1 is a diagram of a device in FIG.

[0030] Fig.25 is Fig.24 On the device Fig.17 FIG. 1 is a diagram of a cutting metal gate etching process in which the cutting metal gate opening extends into the third dielectric layer to form a recess.

[0031] Fig.26 is deposited in Fig.25 The cut metal gate opening and the cut metal gate refill material containing the hard mask layer in the recess.

[0032] Fig. 27 is Fig.26 In the device Fig. 20 The process is to form the groove.

[0033] Fig.28 In some embodiments of the present invention, the semiconductor device does not contain recesses in all third dielectric layers.

[0034] Fig.29 This is the V-shaped bottom of the third dielectric layer in some embodiments of the present invention.

[0035] Fig.30 In some embodiments of the present invention, a fin field effect transistor device is manufactured using the process.

[0036] Description of reference numerals:

[0037] D: Depth

[0038] H: Height

[0039] W1, W2: Width

[0040] Y1-Y1, Y2-Y2: Section line

[0041] 10: Semiconductor substrate

[0042] 15: Hard mask layer

[0043] 15A: First hard mask layer

[0044] 15B: Second hard mask layer

[0045] 18: Pad insulation layer

[0046] 20: First semiconductor layer

[0047] 22: First bottom semiconductor layer

[0048] 23: Second bottom semiconductor layer

[0049] 24: Top semiconductor layer

[0050] 25: Second semiconductor layer

[0051] 26: Cover semiconductor layer

[0052] 29: Fin structure

[0053] 30: Insulation material layer

[0054] 35: Sacrificial coating

[0055] 40: First dielectric layer

[0056] 45: Second dielectric layer

[0057] 50,50-1,50-2: The third dielectric layer

[0058] 62: Sacrificial gate dielectric layer

[0059] 64: Gate

[0060] 65: Sidewall spacer

[0061] 66: Hard Mask Layer

[0062] 69: Source / Drain Space

[0063] 301,401: Open

[0064] 303: Photoresist layer

[0065] 701: Cutting metal gate openings

[0066] 901: Groove

[0067] 1001: Depression

[0068] 3000: FinFET device DETAILED DESCRIPTION

[0069] The following detailed description may be accompanied by the accompanying drawings to facilitate understanding of various aspects of the present invention. It is worth noting that the various structures are only for illustrative purposes and are not drawn to scale, as is common in the industry. In fact, the dimensions of the various structures may be increased or decreased arbitrarily for the sake of clarity.

[0070] It should be understood that the following disclosure provides many different embodiments or examples to implement different structures of the present invention. The embodiments of specific components and arrangements are used to simplify the present invention and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes direct contact between the two, or there are other additional components between the two rather than direct contact. A variety of structures can be shown at any scale to simplify and clarify the description.

[0071] In addition, spatial relative terms such as "below", "below", "lower", "above", "above", or similar terms can be used to simplify the description of the relative relationship between a certain element and another element in the diagram. Spatially relative terms can be extended to elements used in other directions, and are not limited to the illustrated direction. The elements can also be rotated 90 degrees or other angles, so directional terms are only used to illustrate the direction in the diagram. In addition, the term "consisting of" can mean "including" or "consisting of..." In the embodiments of the present utility model, the description "one of A, B, and C" refers to "A, B, and / or C" such as A, B, C, A and B, A and C, B and C, or A and B and C, rather than only A, only B, or only C, unless otherwise specified.

[0072] FinFETs are non-planar multi-gate transistors that have fins extending vertically from the gate, and the fins form the source and drain of the transistor. Multiple FinFETs can be coupled to each other to provide an integrated circuit device. One of the factors that determines the device performance of FinFETs or similar devices is the capacitance between adjacent fins. Increased parasitic capacitance degrades circuit speed, thereby reducing device performance.

[0073] One of the factors that determines the device performance of fin field effect transistors such as fin field effect transistors and all-around gate field effect transistors is the shape of the epitaxial source / drain structure. Specifically, the source / drain region of the fin field effect transistor or the all-around gate field effect transistor is recessed, and then the epitaxial source / drain layer is formed in the recess, and the etching substantially defines the shape of the epitaxial source / drain structure. In addition, when two adjacent fin structures are closer to each other, the epitaxial layers may unexpectedly merge with each other. In an embodiment of the present invention, a wall fin structure (such as a dielectric dummy fin structure) is used to physically and electrically separate adjacent source / drain epitaxial layers and define the shape of the source / drain epitaxial layers. The optimized source / drain shape can improve the on current / off current ratio of the fin field effect transistor and the all-around gate field effect transistor, and can improve device performance.

[0074] In the embodiment of the present invention, source / drain may refer to source and / or drain. It should be noted that in the embodiment of the present invention, source and drain may be used interchangeably, and their structures are substantially the same.

[0075] Figures 1 to 14C 1 is a diagram of various stages of manufacturing a semiconductor fully wound gate field effect transistor device in one embodiment of the present invention. It should be understood that the manufacturing process can also be used to manufacture other devices besides the fully wound gate field effect transistor device. Figures 1 to 14C Additional steps may be provided before, during, and after the processes shown, and additional embodiments of the method may replace or omit some of the steps described below. The order of the steps / processes may be reversed.

[0076] like Figure 1 As shown, the first bottom semiconductor layer 22 is epitaxially formed on the semiconductor substrate 10. In some embodiments, the semiconductor substrate 10 is a crystalline silicon substrate. In other embodiments, the semiconductor substrate 10 may include another semiconductor element (such as germanium), a semiconductor compound (such as IV-VI semiconductor compounds such as silicon carbide or silicon germanium, III-V semiconductor compounds such as gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, indium antimonide, gallium arsenide phosphide, aluminum gallium nitride, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof. In one embodiment, the semiconductor substrate 10 is a silicon layer of a silicon-on-insulator substrate.

[0077] The first bottom semiconductor layer 22 is made of a different material than the semiconductor substrate 10. In some embodiments, when the semiconductor substrate 10 is a silicon substrate, the first bottom semiconductor layer 22 includes silicon germanium, and the germanium content is about 10 atomic % to about 60 atomic %. In some embodiments, the thickness of the first bottom semiconductor layer 22 may be about 4 nm to about 30 nm. In other embodiments, the thickness of the first bottom semiconductor layer 22 may be about 5 nm to about 25 nm.

[0078] In addition, the second bottom semiconductor layer 23 is epitaxially formed on the first bottom semiconductor layer 22. The second bottom semiconductor layer 23 is composed of different materials from the first bottom semiconductor layer 22. When the composition of the first bottom semiconductor layer 22 is silicon germanium, the second bottom semiconductor layer 23 includes silicon or silicon germanium. In some embodiments, the germanium content (greater than 0 atomic % to about 10 atomic %) in the silicon germanium of the second bottom semiconductor layer 23 is less than the germanium content of the first bottom semiconductor layer 22. In some embodiments, the thickness of the second bottom semiconductor layer 23 is about 40nm to about 200nm. In other embodiments, the thickness of the second bottom semiconductor layer 23 is about 50nm to about 150nm. However, in other embodiments, the first bottom semiconductor layer 22 is not formed.

[0079] Then, the first semiconductor layer 20 and the second semiconductor layer 25 are alternately formed on the second bottom semiconductor layer 23. In some embodiments, the first bottom semiconductor layer and the second bottom semiconductor layer are not formed, and the first semiconductor layer 20 and the second semiconductor layer 25 are directly formed on the semiconductor substrate 10. The constituent materials of the first semiconductor layer 20 and the second semiconductor layer 25 have different lattice constants, and may include one or more layers of silicon, germanium, silicon germanium, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, indium aluminum arsenide, indium gallium arsenide, gallium antimony phosphide, gallium antimony arsenide, or indium phosphide. In some embodiments, the first semiconductor layer 20 and the second semiconductor layer 25 are composed of silicon, silicon compounds, silicon germanium, germanium, or germanium compounds. In one embodiment, the first semiconductor layer 20 is silicon germanium (whose germanium atomic % is greater than or equal to about 20% and less than or equal to about 60%), and the second semiconductor layer 25 is silicon or silicon germanium (whose germanium atomic % is less than the germanium atomic % of the silicon germanium of the first semiconductor layer 20, and less than or equal to about 10%). In the embodiments of the present invention, "M compound" or "M-based compound" means that the main component of the compound is M.

[0080] The thickness of the first semiconductor layer 20 may be less than or equal to the thickness of the second semiconductor layer 25. In some embodiments, the thickness of the first semiconductor layer 20 may be about 4 nm to about 30 nm. In other embodiments, the thickness of the first semiconductor layer 20 may be about 5 nm to about 20 nm. In some embodiments, the thickness of the second semiconductor layer 25 may be about 4 nm to about 30 nm. In other embodiments, the thickness of the second semiconductor layer 25 may be about 5 nm to about 20 nm. The thicknesses of the first semiconductor layers 20 may be the same or different from each other, and the thicknesses of the second semiconductor layers 25 may be the same or different from each other. Although Figure 1 Three first semiconductor layers 20 and three second semiconductor layers 25 are shown, but the number is not limited to 3 and may be 1, 2, or more than 3 and less than 10.

[0081] In addition, in some embodiments, the top semiconductor layer 24 is epitaxially formed on the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25. In some embodiments, the top semiconductor layer 24 is silicon germanium, and its germanium atomic % is greater than or equal to about 0.2 and less than or equal to about 0.7. In some embodiments, the germanium atomic % of the silicon germanium of the top semiconductor layer 24 is equal to the germanium atomic % of the silicon germanium of the first semiconductor layer 20. The thickness of the top semiconductor layer 24 is greater than the thickness of the first semiconductor layer 20 and also greater than the thickness of the second semiconductor layer 25. In some embodiments, the thickness of the top semiconductor layer 24 is about 10nm to about 100nm. In other embodiments, the thickness of the top semiconductor layer 24 is about 20nm to about 50nm. In addition, in some embodiments, a cap semiconductor layer 26 is epitaxially formed on the top semiconductor layer 24, and the composition material of the cap semiconductor layer 26 is different from the top semiconductor layer 24. In some embodiments, the composition of the cap semiconductor layer is silicon, and its thickness is about 0.5nm to about 10nm. The cap semiconductor layer 26 is used to control the germanium out-diffused from the top semiconductor layer 24 and maintain the surface quality of the top semiconductor layer 24 during the subsequent chemical mechanical polishing process.

[0082] In addition, a hard mask layer 15 including one or more layers of insulating material or amorphous semiconductor material (e.g., amorphous silicon) is formed on the cap semiconductor layer 26. In some embodiments, the hard mask layer 15 includes a first hard mask layer 15A and a second hard mask layer 15B. In some embodiments, the first hard mask layer 15A is silicon oxide with a thickness of 1 nm to about 20 nm. The second hard mask layer 15B is silicon nitride with a thickness of about 10 nm to about 100 nm.

[0083] In the formation Figure 1 After stacking the layers as shown, one or more photolithography and etching steps may be used to form the fin structure, such as Figure 2 As shown. The patterning method of the fin structure may be any suitable method. For example, the fin structure may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Generally speaking, the double patterning or multiple patterning process combines photolithography with a self-alignment process, and the pattern spacing produced by the double patterning or multiple patterning process may be smaller than the pattern spacing obtained by using a single direct photolithography process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithography process. A self-alignment process is used to form spacers along the sides of the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the hard mask layer 15. The patterned hard mask layer is used as a mask, and the stacked semiconductor layers are patterned into Figure 2 The fin structure 29 is shown. In some embodiments, the top semiconductor layer 24 and the cap semiconductor layer 26 are part of an etch stop layer and a hard mask layer used in a subsequent chemical mechanical polishing process.

[0084] exist Figure 2 In the embodiment, the fin-shaped structure 29 extends in the Y direction and is arranged in the X direction. The number of fin-shaped structures is not limited to Figure 2 Two are shown, and may be less (eg, one) or more (eg, three or more). In some embodiments, one or more dummy fin structures are formed on both sides of the fin structure 29 to improve pattern fidelity during the patterning step.

[0085] In some embodiments, the width of the upper portion of the fin structure 29 along the Y direction is about 5 nm to about 40 nm. In other embodiments, the width of the upper portion of the fin structure 29 along the Y direction is about 10 nm to about 30 nm.

[0086] After forming the fin structure 29 , one or more liner insulation layers 18 are formed on the fin structure, and an insulation material layer 30 containing one or more layers of insulation material is formed on the substrate, so that the fin structure 29 and the liner insulation layer 18 are completely buried in the insulation material layer 30 .

[0087] The insulating materials used for the liner insulating layer 18 and the insulating material layer 30 may be the same or different from each other, and may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, silicon oxycarbide, silicon carbon nitride, fluorosilicate glass, and a low dielectric constant dielectric material. In some embodiments, the composition of the liner insulating layer 18 is silicon oxide or silicon nitride, and the composition of the insulating material layer 30 is silicon oxide. The method for forming the insulating material may be low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, flowable chemical vapor deposition, and / or atomic layer deposition. An annealing step may be performed after forming the insulating material layer 30. Then, a planarization step such as chemical mechanical polishing and / or back etching may be performed to expose the upper surface of the hard mask layer 15 (such as the second hard mask layer 15B) from the insulating material layer 30, such as Figure 3 shown.

[0088] Then as Figure 4 As shown, the insulating material layer is recessed to form an insulating material layer 30 and expose the upper side portion of the fin structure 29. This step allows the fin structures 29 to be separated from each other by the insulating material layer 30 (which can also be regarded as shallow trench isolation).

[0089] In some embodiments, the insulating material layer 30 is recessed until the upper portion of the second bottom semiconductor layer 23 is exposed. The first semiconductor layer 20 is a sacrificial layer that is removed later, and the second semiconductor layer 25 is later formed into a semiconductor line or sheet such as a channel layer of a fully wrapped gate field effect transistor. In some embodiments, during or after the recess etching of the insulating material layer 30, the liner insulating layer 18, the hard mask layer 15, and the cap semiconductor layer 26 may be removed to expose the top semiconductor layer 24, such as Figure 4 shown.

[0090] After forming the insulating material layer 30 , a sacrificial capping layer 35 may be formed on the exposed portion of the fin structure 29 . Figure 5 As shown. The sacrificial capping layer 35 includes one or more insulating materials or semiconductor materials. In some embodiments, the sacrificial capping layer 35 includes an amorphous or polycrystalline semiconductor material (such as silicon, silicon carbide, silicon germanium, or germanium). In these embodiments, the sacrificial capping layer 35 is amorphous silicon germanium, and its germanium concentration is about 20 atomic % to about 40 atomic %. In some embodiments, the germanium concentration of the sacrificial capping layer 35 is the same or similar to the germanium concentration of the first semiconductor layer 20 (the difference is within 5%). In some embodiments, the thickness of the sacrificial capping layer 35 is about 5nm to about 50nm. If the thickness of the sacrificial capping layer 35 is less than this range, the space used to form the metal gate may be too small, and some layers of the metal gate structure cannot be properly formed. If the thickness of the sacrificial capping layer 35 is greater than this range, the electrical separation between adjacent fin structures may be insufficient. In some embodiments, before forming the sacrificial capping layer 35, a thin semiconductor layer may be formed on the exposed portion of the fin structure 29. In some embodiments, the thin semiconductor layer is undoped silicon. In some embodiments, the undoped silicon is polycrystalline silicon. In some embodiments, the thickness of the thin semiconductor layer is about 2 nm to about 3 nm. In some embodiments, the sacrificial capping layer 35 is conformally formed by chemical vapor deposition or atomic layer deposition. In some embodiments, the deposition temperature of the sacrificial capping layer 35 is less than or similar to the deposition temperature of the first semiconductor layer 20. In some embodiments, the deposition temperature of the sacrificial capping layer 35 may be about 500° C. to 650° C. The source gas includes a mixture of silane, germane, and hydrogen chloride, and a carrier gas such as hydrogen or nitrogen. The sacrificial capping layer 35 can control the stress in the isolation region.

[0091] Then as Figure 6 As shown, one or more back etching steps are performed to remove the horizontal portion of the sacrificial capping layer 35 to expose the upper surface of the top semiconductor layer 24 and the upper surface of the insulating material layer 30. In some embodiments, the back etching step includes a deposition-etching process. In some embodiments, plasma generated from methane can be used for the deposition step, and plasma generated from hydrogen bromide and helium can be used for the etching step, and these steps can be repeated. In some embodiments, a wet cleaning process can be performed after the deposition-etching step to remove residues.

[0092] Then, a first dielectric layer 40 is formed on the fin structure, and a second dielectric layer 45 is formed on the first dielectric layer 40 so that the fin structure is completely buried in the second dielectric layer 45. Figure 7As shown. The first dielectric layer 40 includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride oxide, which can be formed by low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, or any other suitable film forming method. In these embodiments, silicon carbonitride or silicon carbonitride oxide can be used as the first dielectric layer 40. Figure 7 In some embodiments shown, the first dielectric layer 40 is conformally formed on the fin structure so that a space is formed between adjacent fin structures. In some embodiments, the thickness of the first dielectric layer 40 is about 2.5 nm to about 20 nm. In other embodiments, the thickness of the first dielectric layer 40 is about 5 nm to about 10 nm.

[0093] The material of the second dielectric layer 45 is different from the material of the first dielectric layer 40. In some embodiments, the second dielectric layer 45 includes one or more layers of insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, silicon oxycarbide, silicon carbonitride, or silicon carbonitride oxide, which may be formed by low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, or any other suitable film forming method. In some embodiments, the second dielectric layer 45 is composed of silicon nitride or silicon oxide. In some embodiments, the second dielectric layer 45 includes a first layer and a second layer. The first layer is silicon oxide, which may be formed by a flowable chemical vapor deposition process, followed by a thermal annealing process at 400°C to 800°C in an inert gas environment. The second layer may also be silicon oxide, which may be formed by a plasma assisted chemical vapor deposition process. In some embodiments, the thickness of the second dielectric layer 45 may be from about 60nm to about 500nm. Figure 7 In some embodiments shown, the second dielectric layer 45 completely fills the space between adjacent fin structures. In other embodiments, a void is formed in the bottom of the space. In some embodiments, one or more additional dielectric layers may be formed between the first dielectric layer 40 and the second dielectric layer 45.

[0094] After forming the second dielectric layer 45, a planarization step such as an etch-back process or a chemical mechanical polishing process may be performed to planarize the second dielectric layer 45 and expose the upper surface of the top semiconductor layer 24. In some embodiments, the top semiconductor layer 24 may be slightly etched by about 5 nm to about 10 nm. In addition, one or more additional etch-back steps may be performed to recess the second dielectric layer 45, such as Figure 8 The second dielectric layer 45 may be recessed to substantially the same height (within 5 nm) as the interface between the top semiconductor layer 24 and the uppermost second semiconductor layer 25. In some embodiments, the first dielectric layer 40 may be trimmed (eg, etched) to expose a portion of the sacrificial capping layer 35.

[0095] Afterwards Figures 9A to 9DAs shown, the third dielectric layer 50 is formed on the recessed second dielectric layer 45 . Fig. 9A is a cross-sectional view along the X direction, Fig. 9B It is along the corresponding Fig. 9A The cross-sectional view of the section line Y1-Y1 in the Y direction, Fig. 9C It is along the corresponding Fig. 9A The cross-sectional view of the section line Y2-Y2 in the Y direction, and Fig.9D It is an isometric drawing.

[0096] The material of the third dielectric layer 50 is different from the material of the first dielectric layer 40 and the second dielectric layer 45. In some embodiments, the material included in the third dielectric layer 50 has a lower etching rate for polysilicon or amorphous silicon germanium than the etching rate of the second dielectric layer 45. In some embodiments, the third dielectric layer 50 includes a dielectric material with a high dielectric constant. In some embodiments, the dielectric constant of the dielectric material included in the third dielectric layer 50 is higher than the dielectric constant of the second dielectric layer 45 and / or the first dielectric layer 40.

[0097] In some embodiments, the third dielectric layer 50 includes one or more of undoped hafnium oxide, hafnium oxide doped with other elements (such as hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, or hafnium zirconium oxide), zirconium oxide, aluminum oxide, titanium oxide, and hafnium oxide-aluminum oxide alloy. In these embodiments, hafnium oxide is used as the third dielectric layer 50. The third dielectric layer 50 may be formed by low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, or any other suitable film forming method. Fig. 9A As shown, the third dielectric layer 50 completely fills the space between adjacent fin structures. After the third dielectric layer 50 is formed to completely cover the fin structure, a planarization step such as an etch-back process or a chemical mechanical polishing process may be performed to planarize the upper surface of the third dielectric layer 50 to expose the upper surface of the top semiconductor layer 24, as shown in FIG. Figures 9A to 9D As shown. In some embodiments, the thickness of the third dielectric layer 50 retained on the top semiconductor layer 24 is about 5nm to about 100nm, and the top width of the third dielectric layer 50 can be about 10nm to about 80nm, depending on the device and / or process requirements. In summary, the first dielectric layer 40, the second dielectric layer 45, and the third dielectric layer 50 between adjacent fin structures form a wall fin structure. After forming the wall fin structure, some embodiments may perform an annealing step at a temperature of about 800°C to about 1000°C for about 10 seconds to about 60 seconds.

[0098] Then as Figures 10A to 10C As shown, the top semiconductor layer 24 is removed by one or more dry or wet etching steps. Figures 10A to 10C arrive Figures 11A to 11CIn the figure, the figure ending with B is a cross-sectional view along the Y direction of the section line Y1-Y1 in the figure ending with A, and the figure ending with C is a cross-sectional view along the Y direction of the section line Y2-Y2 in the figure ending with A. Fig. 10A As shown in FIG. 1 , a pit may be formed having sidewalls formed by the sacrificial capping layer 35. After removing the top semiconductor layer 24, a sacrificial gate dielectric layer 62 may be formed on the uppermost second semiconductor layer 25, the sidewalls of the first dielectric layer, and the third dielectric layer 50. Figures 10A to 10C As shown. The sacrificial gate dielectric layer 62 includes one or more layers of insulating materials such as silicon oxide. In one embodiment, silicon oxide formed by chemical vapor deposition can be used. In some embodiments, the thickness of the sacrificial gate dielectric layer 62 can be about 1 nm to about 5 nm.

[0099] In addition, if Figures 11A to 11C As shown, a sacrificial (dummy) gate 64 is formed, and a hard mask layer 66 is formed on the sacrificial gate 64. The sacrificial gate 64 can be blanket deposited on the sacrificial gate dielectric layer 62 and the third dielectric layer 50, so that the third dielectric layer 50 is completely buried in the sacrificial gate 64. The sacrificial gate 64 includes silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate 64 can be about 100nm to about 200nm. In some embodiments, the sacrificial gate layer is planarized. The deposition method of the sacrificial gate dielectric layer and the sacrificial gate layer can adopt chemical vapor deposition such as low pressure chemical vapor deposition or plasma assisted chemical vapor deposition, physical vapor deposition, atomic layer deposition, or other suitable processes. Thereafter, a hard mask layer 66 is formed on the sacrificial gate layer. The hard mask layer 66 includes one or more layers of silicon nitride or silicon oxide. Then, a patterning step is performed on the hard mask layer 66, and the layer of the sacrificial gate 64 is patterned into a sacrificial gate, such as Figures 12A to 12C As shown. In some embodiments, the width of the sacrificial gate 64 is about 5 nm to about 30 nm, such as about 10 nm to about 20 nm. In some embodiments, two or more sacrificial gates are arranged in the Y direction. In these embodiments, one or more dummy sacrificial gates are formed on both sides of the sacrificial gate to improve pattern fidelity.

[0100] In addition, sidewall spacers 65 are formed on the sacrificial gate 64, such as Figures 13A to 13CAs shown. One or more insulating layers are deposited in a conformal manner to have substantially the same thickness on the vertical surfaces of the sacrificial gate, such as the sidewalls, horizontal surfaces, and top, and the sidewalls of the first dielectric layer 40. Anisotropic etching is then performed to form sidewall spacers. In some embodiments, the thickness of the sidewall spacers is about 3 nm to about 20 nm. The sidewall spacers 65 include one or more of silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, and any other suitable dielectric material. In some embodiments, since the height of the third dielectric layer 50 is much smaller than the height of the sacrificial gate layer 64 and the hard mask layer, the thickness of the sidewall spacers on the sidewalls of the first dielectric layer on the third dielectric layer 50 is less than the thickness of the sidewall spacers on the sacrificial gate layer 64, or there are no sidewall spacers on the sidewalls of the first dielectric layer on the third dielectric layer 50 (such as Fig.13D shown).

[0101] Then, one or more etching steps are used to etch down the stacked structure of the first semiconductor layer 20 and the second semiconductor layer 25 in the source / drain region to form a source / drain space 69, such as Fig.14A and 14B As shown. In some embodiments, the second bottom semiconductor layer 23 is also partially etched. In some embodiments, the sacrificial capping layer 35 may be partially or completely removed during etching. In some embodiments, thin sidewall spacers or no sidewall spacers are formed on the sidewalls of the first dielectric layer on the third dielectric layer 50, and the etching to form the source / drain space 69 also removes the sacrificial capping layer 35.

[0102] like Fig.15 As shown, a deposition and patterning process is performed to form an opening 301 through the photoresist layer 303 on the hard mask layer 66. The deposition method of the photoresist layer can adopt any suitable deposition or coating process, its thickness can be any suitable thickness, and its patterning method can adopt any suitable photolithography method to form the opening 301 through the photoresist layer 303 and expose the surface of the hard mask layer 66 in the area on the sacrificial gate 64 between adjacent fin structures. Fig.15 Before the step in, the sacrificial gate 64 may be removed and replaced with a metal gate 64. In some embodiments, the gate comprises a metal-based material. For example, the sacrificial gate 64 may be removed by one or more dry or wet etching steps.

[0103] like Fig.16As shown, the pattern of the photoresist layer 303 is transferred to the hard mask layer 66 to form a pattern of an opening 401 through the hard mask layer 66. In some embodiments, the etchant used to etch the hard mask layer 66 includes a reactive gas having an etching selectivity to the material used for the hard mask layer 66 greater than an etching selectivity to the gate layer material used for the gate 64. In this way, the gate 64 acts as a contact etch stop layer, and the opening 401 exposes the region of the gate 64 on the third dielectric layer 50. In some embodiments, the etching process may use a gas containing carbon and fluorine, such as carbon tetrafluoride, difluoromethane, fluoroform, or the like.

[0104] like Fig.17 As shown, a cut metal gate etching process is performed to remove the exposed portion of the gate 64 and the portion of the sacrificial gate dielectric layer 62 to form a cut metal gate opening 701. The cut metal gate etching process can separate the gate 64 into two gate portions to effectively cut the gate 64. In some embodiments, the cut metal gate etching process includes a dry etching process using a chlorine-containing or fluorine-containing gas such as chlorine, nitrogen trifluoride, silicon tetrachloride, boron trichloride, oxygen, nitrogen, hydrogen, argon, a combination of the above, or the like. However, any suitable dry etching gas can be used for the cut metal gate etching process.

[0105] During the cut metal gate etching process, residual byproduct materials may be formed, such as byproducts of the reaction between the material of the sacrificial gate dielectric layer 62, the material of the gate 64, the hard mask layer 66, and the reaction gases during the cut metal gate etching process. In some embodiments, once the cut metal gate opening 701 is formed, a removal process may be performed to remove any residual byproducts. For example, hydrofluoric acid / ammonia gas may be used to remove the material. The hydrofluoric acid / ammonia gas has a low selectivity for metals, and the pressure and temperature may be adjusted when removing polymer byproducts to adjust the hydrofluoric acid / ammonia gas to have different selectivity for silicon nitride,

[0106] In some embodiments, once the cut metal gate polymer byproducts are removed, a wet clean may be performed to ensure a clean surface of the cut metal gate opening 701 for subsequent processes. In some embodiments, a solution such as SC-1 or SC-2 cleaning solution may be used for the wet cleaning process. Other solutions such as a mixture of sulfuric acid and hydrogen peroxide or a solution of hydrofluoric acid may also be used. However, any suitable solution or any suitable process may be used for the wet cleaning process.

[0107] like Fig.18As shown, a cut metal gate refill material (including the material of the hard mask layer 66) is deposited on the cut metal gate opening 701. The cut metal gate refill material includes one or more layers of silicon nitride or silicon oxide, depending on the material in the hard mask layer 66. The cut metal gate refill material can be deposited by plasma assisted chemical vapor deposition, atomic layer deposition, chemical vapor deposition, or the like. In some embodiments, the cut metal gate refill material is the same material as the hard mask layer 66. In other embodiments, the dielectric material used for the cut metal gate refill material is different from that of the hard mask layer 66.

[0108] The continuous poly on diffusion edge (CPODE) pattern can be used to remove a dummy structure such as the gate 64 and a portion of the substrate such as the semiconductor substrate 10 below the dummy structure to form a trench. In some embodiments, the continuous poly on diffusion edge layout pattern is used to indicate that the gate layout pattern is a dummy gate layout pattern. Other configurations or pattern numbers in the continuous poly on diffusion edge layout pattern also fall within the scope of the embodiments of the present invention.

[0109] like Fig.19 As shown, using Fig.18 The semiconductor device fabricated in the process is subjected to continuous diffusion on the polysilicon edge process. For illustration, Fig.19 Additional fin structures 29 and insulating material layers 30 are shown, and Fig.18 As shown, a portion of the hard mask layer 66 is etched to expose the lower gate 64 between adjacent cut metal gate openings 701 on the fin structure. In some embodiments, the etching process may use a gas containing carbon and fluorine, such as carbon tetrafluoride, difluoromethane, fluoroform, or the like.

[0110] like Fig. 20 As shown, the gate 64 and the lower fin structure including the first semiconductor layer 20 and the second semiconductor layer 25 are etched. The etching process may use one or more dry and / or wet etching steps, such as Fig. 20 As shown. The gate 64, the first semiconductor layer 20 and the second semiconductor layer 25 below, and other structures below the cut metal gate opening 701 can be patterned by any suitable method. In some embodiments, the etching step includes etching the metal gate layer and then etching the semiconductor layer. The etching process can remove the fin structure 29 and form the trench 901.

[0111] Some examples are Fig.18 In the manufacturing process shown, there may be stacking offsets in the metal gate cutting process. Fig.16 For example, the stack offset comes from the misalignment between the cut metal gate opening 701 and the third dielectric layer 50 . Fig.21 The stack offset is shown in the dashed ellipse. The misalignment between the cut metal gate opening 701 and the third dielectric layer 50 may come from Fig.17 The cut metal gate opening 701 formed by the cut metal gate etching process shown is offset. One of the reasons for the stack offset is that the size of the third dielectric layer 50 is narrow, and the cut metal gate opening 701 cannot land correctly on the third dielectric layer 50. If the cut metal gate opening 701 and the third dielectric layer 50 are not aligned, the trench 901 cannot be formed correctly. For example, Fig. 20 The side wall portion indicated by the dotted ellipse in FIG. 1 is misaligned.

[0112] One way to reduce stack offset is tighter stack control to ensure that the misalignment is close to zero. Another solution is to increase the critical dimension (width) of the cut metal gate opening 701 to increase the tolerance range to achieve alignment between the cut metal gate opening 701 and the third dielectric layer 50. However, the manufacturing process for tighter stack control to ensure that the misalignment between the cut metal gate opening 701 and the third dielectric layer 50 is close to zero is time-consuming and costly. The enlarged (widened) cut metal gate opening 701 substantially reduces the work function of the gate 64.

[0113] The present invention relates to increasing the critical dimension (width) of the third dielectric layer 50 to improve the alignment between the cut metal gate opening 701 and the third dielectric layer 50. The present invention also relates to forming a recess in the third dielectric layer 50 to improve the contact between the hard mask layer 66 and the third dielectric layer 50.

[0114] Fig.22A The third dielectric layer 50 of the semiconductor device shown is Fig. 14C The third dielectric layer 50 is wider.

[0115] The first dielectric layer 40 ( Figure 8 ), so as to obtain a wider third dielectric layer 50, such as Figures 9A to 9C As shown. Fig. 22B As shown, and with Figure 8 and 22A As described above, the first dielectric layer 40 above the second dielectric layer 45 and within the recess formed by the second dielectric layer 45 can be etched to produce a wider recess. The etching can expose the sidewalls of the sacrificial cap layer 35.

[0116] The third dielectric layer 50 is formed in the widened recess on the second dielectric layer 45 and on the fin structure. Fig. 22CThe third dielectric layer 50 may be formed by low pressure chemical vapor deposition, plasma assisted chemical vapor deposition, atomic layer deposition, or any other suitable film forming method. After the third dielectric layer 50 is formed to completely cover the fin structure, a planarization step such as an etch back process or a chemical mechanical polishing process may be performed to planarize the upper surface of the third dielectric layer 50 to expose the upper surface of the fin structure, such as Fig.22D shown.

[0117] Then as Fig.22E As shown, the top semiconductor layer 24 and the sacrificial capping layer 35 are removed by one or more dry or wet etching steps to form a recess, and the sidewall of the recess is formed by the third dielectric layer 50 .

[0118] After removing the top semiconductor layer 24 and the sacrificial capping layer 35, a sacrificial gate dielectric layer 62 may be formed on the sidewalls of the topmost second semiconductor layer 25 and the third dielectric layer 50. Fig.22E As shown. The sacrificial gate dielectric layer 62 includes one or more layers of insulating materials such as silicon oxide. In one embodiment, silicon oxide formed by chemical vapor deposition can be used. In some embodiments, the thickness of the sacrificial gate dielectric layer 62 is about 1 nm to about 5 nm. In addition, as shown Fig.22E As shown, a gate 64 may be formed. A hard mask layer 66 may be formed on the gate 64, which may be matched with Fig.11A The process described is similar. Fig.22E Pairing on the device Figures 15 to 18 The process technology described in this paper is Fig.23 Device in.

[0119] like Fig.23 As shown, the metal gate etching process and the deposited metal gate refill material (with Fig.17 and 18 The semiconductor device after the process is similar to that shown in FIG. 1 has a wider third dielectric layer 50. Since the third dielectric layer 50 is wider, a narrower cut metal gate opening 701 can be used.

[0120] like Fig.24 As shown, a groove 901 is formed at Fig.23 The device in the embodiment of the present invention can be formed by using a combination of Fig. 20 As shown in the figure, due to the increase in the critical dimension (width) of the third dielectric layer 50, the available area for forming the cut metal gate opening 701 is increased. Therefore, the probability of misalignment between the cut metal gate opening 701 and the third dielectric layer 50 can be reduced. Due to the increase in the critical dimension (such as width W1) of the third dielectric layer 50, the critical dimension of the cut metal gate opening 701 can be smaller to improve the work function of the gate 64. In some embodiments, the critical dimension (width W1) of the third dielectric layer 50 can be reduced from about 10nm (see Figures 9A to 19 ) is increased to about 20 nm. In some embodiments, the critical dimension (width) of the third dielectric layer 50 may be about 20 nm to about 40 nm. In other embodiments, the critical dimension (width) of the third dielectric layer 50 may be about 25 nm to about 35 nm. In some embodiments, the bottom width of the third dielectric layer 50 is substantially equal to the sum of the width of the second dielectric layer 45 and twice the width of the first dielectric layer 40.

[0121] Additionally or alternatively, the critical dimension (width) of the third dielectric layer 50 may be increased, and a recess may be formed in the wider third dielectric layer 50, and a cut metal gate refill material may be deposited in the recess. Fig.25 As shown, in Fig.24 Performing a metal gate etching process on a device in Fig.17 ), wherein the cut metal gate opening 701 extends into the third dielectric layer 50 to form a recess 1001. The critical dimension (width) of the cut metal gate opening 701 is greater than Fig.17 The width of the cut metal gate opening 701 is narrow. Fig.26 As shown, the cut metal gate refill material containing the material of the hard mask layer 66 can be deposited in the cut metal gate opening 701 and the recess 1001. The embodiment of the utility model is conducive to improving the alignment between the cut metal gate opening 701 and the third dielectric layer 50. In this way, a narrower cut metal gate opening 701 can be formed, and the work function of the gate 64 can be improved.

[0122] like Fig. 27 As shown, a groove 901 is formed at Fig.26 In the device, and the forming method can be used with Fig. 20 The process described above.

[0123] The semiconductor device may include a wider third dielectric layer 50, and a third dielectric layer 50 including recesses. Similarly, the semiconductor device may include recesses only in some third dielectric layers. Fig.28 It is shown that the recesses included in the semiconductor device in the embodiment of the present invention are not in all the third dielectric layers 50. Fig.28 As shown, the third dielectric layers 50 - 1 and 50 - 2 have a recess 1001 .

[0124] In some embodiments, the depth D of the recess 1001 may be about 13 nm to about 22 nm. In some embodiments, the width W1 of the third dielectric layer 50 may be about 14 nm to about 20 nm. In some embodiments, the width W2 of the cut metal gate opening 701 may be about 8 nm to about 12 nm. In some embodiments, the height H of the third dielectric layer 50 is about 30 nm to about 33 nm. In some embodiments, the ratio of the widths W1 and W2 may be about 1.5 to about 3.5.

[0125] like Fig.29 In some embodiments shown, the bottom of the third dielectric layer 50 may be V-shaped or similar. In some embodiments, the bottom may be U-shaped or any other shape.

[0126] Fig.30 The fin field effect transistor device 3000 is fabricated using the process in the embodiments described herein. In some embodiments, the width W1 of the third dielectric layer 50 is about 20 nm. In some embodiments, the depth D of the recess 1001 is about 26 nm.

[0127] The present invention is advantageous in improving the alignment between the cut metal gate opening 701 and the third dielectric layer 50. In this way, a narrower cut metal gate opening 701 can be formed and the work function of the gate 64 can be improved. It should be understood that not all advantages are necessarily described here, not all embodiments necessarily have a particular advantage, and other embodiments or examples may provide different advantages.

[0128] In one embodiment of the utility model, a method for manufacturing a semiconductor device includes: forming a fin-shaped structure, which includes a stacked layer of a plurality of first semiconductor layers and a plurality of second semiconductor layers located on the bottom fin-shaped structure, and a first hard mask layer located on the stacked layer. Forming an isolation insulating layer so that the first hard mask layer and the stacked layer are exposed from the isolation insulating layer. Forming a sacrificial coating layer on at least the sidewalls of the exposed first hard mask layer and the stacked layer. Forming a first dielectric layer. Forming a second dielectric layer on the first dielectric layer, and the materials of the first dielectric layer and the second dielectric layer are different. Recessing the second dielectric layer. After recessing the second dielectric layer, removing the exposed first dielectric layer. Forming a third dielectric layer on the recessed second dielectric layer to form a wall fin-shaped structure, and the materials of the second dielectric layer and the third dielectric layer are different. Removing the first hard mask layer. Forming a gate layer on the third dielectric layer and the portion occupied by the first hard mask layer before the removal step. Forming a second hard mask layer on the gate layer. Forming an opening in the second hard mask layer on the third dielectric layer. The portions of the gate layer and the third dielectric layer exposed in the opening are removed to expose the upper portion of the third dielectric layer. A refill material is deposited in the opening, wherein the refill material in the opening is completely located in the third dielectric layer in a cross-sectional view. In some embodiments, the step of removing the first dielectric layer includes removing the first dielectric layer to expose a sacrificial coating on the second dielectric layer and at least the sidewalls of the first hard mask layer and the stacked layer. In some embodiments, the step of forming the third dielectric layer includes depositing the third dielectric layer on the first hard mask layer and the sacrificial coating; and planarizing the third dielectric layer to expose the upper portion of the first hard mask layer. In some embodiments, the sacrificial coating is amorphous or polycrystalline silicon. In some embodiments, the second hard mask layer includes silicon nitride, silicon oxide, or silicon oxynitride. In some embodiments, the refill material is the same material as the second hard mask layer. In some embodiments, the ratio of the width of the third dielectric layer to the width of the opening in the cut metal gate region is about 1.5 to about 3.5. In some embodiments, the width of the third dielectric layer is 14nm to 40nm, and the width of the opening in the cut metal gate region is 8nm to 12nm. In some embodiments, the third dielectric layer has a height of 30 nm to 33 nm. In some embodiments, the method further comprises removing the fin structure between the third dielectric layers and the bottom fin structure below the fin structure to form a trench.

[0129] In another embodiment of the present invention, a method for manufacturing a semiconductor device includes: forming a fin-shaped structure, which includes a stack of multiple first semiconductor layers and multiple second semiconductor layers located on the bottom fin-shaped structure, and a first hard mask layer located on the stack. Forming an isolation insulating layer so that the first hard mask layer and the stack are exposed from the isolation insulating layer. Forming a sacrificial coating on at least the sidewalls of the exposed first hard mask layer and the stack. Forming a first dielectric layer. Forming a second dielectric layer on the first dielectric layer, and the first dielectric layer and the second dielectric layer are made of different materials. Recessing the second dielectric layer. After recessing the second dielectric layer, removing the exposed first dielectric layer. Forming a third dielectric layer on the recessed second dielectric layer to form a wall fin-shaped structure, and the third dielectric layer and the second dielectric layer are made of different materials. Removing the first hard mask layer. Forming a gate layer on the third dielectric layer and the portion occupied by the first hard mask layer before the removal step. Forming a second hard mask layer on the gate layer. Forming an opening in the second hard mask layer on the third dielectric layer. Portions of the gate layer and the third dielectric layer exposed in the opening are removed to form openings in the cut metal gate region and the third dielectric layer, thereby forming a recess in the third dielectric layer. Refill material is deposited in the opening and the recess. In some embodiments, the refill material in the opening and the recess is completely located in the third dielectric layer in a cross-sectional view. In some embodiments, the ratio of the width of the third dielectric layer to the width of the opening in the cut metal gate region is about 1.5 to about 3.5. In some embodiments, the width of the third dielectric layer is 14nm to 40nm, and the width of the opening in the cut metal gate region is 8nm to 12nm. In some embodiments, the height of the third dielectric layer is 30nm to 33nm. In some embodiments, the depth of the recess is 13nm to 22nm.

[0130] In another embodiment of the utility model, the semiconductor device includes: a first fully wrapped gate field effect transistor and a second fully wrapped gate field effect transistor; and a wall fin, located between the first fully wrapped gate field effect transistor and the second fully wrapped gate field effect transistor, and located on the isolation insulating layer. The wall fin includes a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer; the materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are different from each other; and the third dielectric layer includes a recess. In some embodiments, the ratio of the width of the third dielectric layer to the width of the recess is about 1.5 to about 3.5. In some embodiments, the width of the third dielectric layer is 14nm to 40nm, and the width of the recess is 8nm to 12nm. In some embodiments, the depth of the recess is 13nm to 22nm. In some embodiments, the height of the third dielectric layer is 30nm to 33nm. In some embodiments, the semiconductor device also includes a refill material located in the recess. In some embodiments, the first dielectric layer is U-shaped. In some embodiments, the thickness of the first dielectric layer is 2.5nm to 20nm. In some embodiments, the second dielectric layer has a thickness of 60 nm to 500 nm. In some embodiments, the recess corresponds to a cut metal gate region between the first all-around gate field effect transistor and the second all-around gate field effect transistor.

[0131] The features of the above embodiments are helpful for those skilled in the art to understand the present invention. Those skilled in the art should understand that the present invention can be used as a basis to design and change other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art should also understand that these equivalent substitutions do not depart from the concept and scope of the present invention, and can be changed, replaced, or modified without departing from the concept and scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a first fully wound gate field effect transistor and a second fully wound gate field effect transistor; as well as A wall fin is located between the first all-wrap gate field effect transistor and the second all-wrap gate field effect transistor and is located on an isolation insulating layer, wherein: The wall fin includes a first dielectric layer, a second dielectric layer located on the first dielectric layer, and a third dielectric layer; The materials of the first dielectric layer, the second dielectric layer, and the third dielectric layer are different from each other; as well as The third dielectric layer includes a recess.

2. The semiconductor device according to claim 1, wherein A ratio of the width of the third dielectric layer to the width of the recess is about 1.5 to about 3.

5.

3. The semiconductor device according to claim 2, wherein: The width of the third dielectric layer is 14 nm to 40 nm, and the width of the recess is 8 nm to 12 nm.

4. The semiconductor device according to claim 1 or 2, wherein: The depth of the recess is 13 nm to 22 nm.

5. The semiconductor device according to claim 1 or 2, wherein: The height of the third dielectric layer is 30 nm to 33 nm.

6. The semiconductor device according to claim 1 or 2, wherein: Also included is a refill material located in the recess.

7. The semiconductor device according to claim 1 or 2, wherein: The first dielectric layer is U-shaped.

8. The semiconductor device according to claim 1 or 2, wherein: The thickness of the first dielectric layer is 2.5 nm to 20 nm.

9. The semiconductor device according to claim 1 or 2, wherein: The thickness of the second dielectric layer is 60 nm to 500 nm.

10. The semiconductor device according to claim 1 or 2, wherein: The recess corresponds to a cut metal gate region between the first all-around gate field effect transistor and the second all-around gate field effect transistor.

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