Display panel

Abstract

The utility model discloses a display panel, which comprises a substrate, a buffer layer, a first metal layer, a gate insulation layer, a semiconductor layer and a second metal layer, and is characterized in that the buffer layer is arranged on the substrate; the first metal layer comprises a grid electrode arranged on the buffer layer, and the area of the lower surface of the grid electrode is smaller than that of the upper surface of the grid electrode; the gate insulating layer covers the outer surface of the gate, the gate insulating layer comprises a first insulating part, and the first insulating part covers at least one part of the side surface of the gate; the semiconductor layer covers the gate insulating layer, the semiconductor layer comprises a channel part, and the channel part covers the first insulating part; the second metal layer comprises a first electrode and a second electrode, the first electrode is located on one side of the grid electrode, the second electrode is located above the grid electrode, and the second electrode and the first electrode are arranged on different layers; wherein the orthographic projection of the channel part on the substrate is located in the range of the orthographic projection of the second electrode on the substrate. According to the invention, the mobility and stability of the TFT device can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel. Background Art

[0002] In a conventional display panel, a semiconductor layer covers a gate insulating layer, and a second metal layer covers the semiconductor layer. After the second metal layer is formed, the second metal layer needs to be patterned to form a source electrode and a drain electrode spaced apart on the semiconductor layer.

[0003] The etching solution used in the process of patterning the second metal layer will etch the back channel of the semiconductor layer, causing the back channel of the semiconductor layer to be destroyed, thereby reducing the mobility of the TFT device and causing the stability of the device to decrease.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above technical problems. Utility Model Content

[0005] The purpose of the present application is to provide a display panel to improve the mobility and stability of TFT devices.

[0006] To solve the above problems, the technical solution of this application is as follows:

[0007] The present application proposes a display panel, comprising:

[0008] substrate;

[0009] A buffer layer is disposed on the substrate;

[0010] A first metal layer, comprising a gate, wherein the gate is disposed on the buffer layer, and an area of ​​a lower surface of the gate is smaller than an area of ​​an upper surface of the gate;

[0011] a gate insulating layer, disposed on the buffer layer and covering an outer surface of the gate, the gate insulating layer comprising a first insulating portion, the first insulating portion covering at least a portion of a side surface of the gate;

[0012] a semiconductor layer covering the gate insulating layer, the semiconductor layer including a channel portion, the channel portion covering the first insulating portion; and

[0013] A second metal layer is provided on the semiconductor layer, the second metal layer comprises a first electrode and a second electrode which are arranged at intervals, wherein the first electrode is located on one side of the gate, the second electrode is located above the gate, and the second electrode and the first electrode are arranged in different layers;

[0014] The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the second electrode on the substrate.

[0015] In one embodiment of the present application, the orthographic projection of the lower surface of the gate on the substrate is located within the range of the orthographic projection of the upper surface of the gate on the substrate.

[0016] In one embodiment of the present application, the semiconductor layer further includes:

[0017] a first doped portion, disposed on the gate insulating layer and located on one side of the gate; and

[0018] a second doping portion, disposed on the gate insulating layer and above the gate, wherein the second doping portion and the first doping portion are disposed in different layers;

[0019] The channel portion connects the first doped portion and the second doped portion, the first electrode is disposed on an upper surface of the first doped portion, and the second electrode is disposed on an upper surface of the second doped portion.

[0020] In one embodiment of the present application, an orthographic projection of the channel portion on the substrate overlaps with an orthographic projection of the second doped portion on the substrate;

[0021] An orthographic projection of the channel portion on the substrate overlaps with an orthographic projection of the first doped portion on the substrate.

[0022] In one embodiment of the present application, the gate insulating layer further includes:

[0023] a second insulating portion, disposed on the buffer layer and located on one side of the gate; and

[0024] A third insulating portion, provided on the upper surface of the gate;

[0025] The first insulating portion connects the second insulating portion and the third insulating portion, the first doped portion is disposed on an upper surface of the second insulating portion, and the second doped portion is disposed on an upper surface of the third insulating portion.

[0026] In one embodiment of the present application, the first insulating portion covers the outer circumference of the gate, the second insulating portion is arranged around the periphery of the gate, and the third insulating portion covers the upper surface of the gate;

[0027] Wherein, the second doped portion covers the upper surface of the third insulating portion, and the second electrode covers the upper surface of the second doped portion;

[0028] The first doped portion covers an upper surface of the second insulating portion, the first electrode covers an upper surface of the first doped portion, and the first doped portion is disposed around a periphery of the gate.

[0029] In an embodiment of the present application, the orthographic projection of the semiconductor layer on the substrate is located within the range of the orthographic projection of the second metal layer on the substrate.

[0030] In one embodiment of the present application, the gate includes:

[0031] A first film layer is disposed on the buffer layer; and

[0032] A second film layer, disposed on the first film layer;

[0033] The orthographic projection of the first film layer on the substrate is located within the range of the orthographic projection of the second film layer on the substrate, and the first insulating portion covers the side surfaces of the first film layer and the second film layer.

[0034] In one embodiment of the present application, the display panel further includes a light shielding layer, the light shielding layer is disposed on the substrate, and the buffer layer covers the light shielding layer;

[0035] The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the light shielding layer on the substrate.

[0036] The present application also proposes a display panel, comprising:

[0037] substrate;

[0038] A buffer layer is disposed on the substrate;

[0039] A first metal layer, comprising a gate, wherein the gate is disposed on the buffer layer, and at least a portion of a side surface of the gate is provided with a recessed portion;

[0040] a gate insulating layer, disposed on the buffer layer and covering an outer surface of the gate, the gate insulating layer comprising a first insulating portion, the first insulating portion covering the recessed portion;

[0041] a semiconductor layer covering the gate insulating layer, the semiconductor layer including a channel portion, the channel portion covering the first insulating portion; and

[0042] A second metal layer is provided on the semiconductor layer, the second metal layer comprises a first electrode and a second electrode which are arranged at intervals, wherein the first electrode is located on one side of the gate, the second electrode is located above the gate, and the second electrode and the first electrode are arranged in different layers;

[0043] The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the second electrode on the substrate.

[0044] In the present application, the area of ​​the lower surface of the gate is smaller than the area of ​​the upper surface of the gate. At this time, an undercut structure is formed between the side of the gate and the buffer layer. At this time, a conformal gate insulating layer and a semiconductor layer can be formed on the buffer layer in sequence by a film forming method with good step coverage. Since the gate insulating layer and the semiconductor layer are conformal, the gate insulating layer and the semiconductor layer will not be disconnected at the undercut structure. Then, a non-conformal second metal layer is formed on the semiconductor layer by a film forming method with poor step coverage. Due to the poor step coverage, the second metal layer will automatically disconnect at the undercut structure to form a first electrode and a second electrode arranged at intervals. In the process of patterning the second metal layer, since the first insulating part and the channel part cover the undercut structure, and the second electrode is located above the undercut structure, the second electrode can protect the back channel of the channel part from being etched, thereby improving the mobility of the TFT device, thereby improving the stability of the TFT device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a top view of an embodiment of a display panel of the present application;

[0046] Figure 2 yes Figure 1 A schematic diagram of a first embodiment of a cross section AA' of a display panel is shown;

[0047] Figure 3 yes Figure 1 A schematic diagram of a second embodiment of a cross section AA' of a display panel is shown;

[0048] Figure 4 is a top view of another embodiment of a display panel of the present application;

[0049] Figure 5 yes Figure 4 A schematic diagram of a BB' cross section of the display panel shown;

[0050] Figure 6 yes Figure 4 A schematic diagram of a CC' cross section of the display panel shown;

[0051] Figure 7 yes Figure 1 A schematic diagram of a third embodiment of a display panel showing a cross section AA';

[0052] Figure 8 yes Figure 1 A schematic diagram of a fourth embodiment of a display panel showing a cross section AA';

[0053] Fig. 9 yes Figure 1 A schematic diagram of a fifth embodiment of a display panel showing a cross section AA';

[0054] Fig.10 is a schematic diagram of a conventional display panel. DETAILED DESCRIPTION

[0055] The meanings of the terms used in this specification and claims correspond to the meanings commonly understood by those of ordinary skill in the art to which this application belongs. The terms used in this specification and claims are only for the purpose of facilitating the description and understanding of this application, and are not intended to limit this application to the narrow interpretation of the specific terms used in the specification and claims.

[0056] The present application proposes a display panel 100, comprising:

[0057] Substrate 10;

[0058] A buffer layer 20, disposed on the substrate 10;

[0059] A first metal layer, including a gate 30, wherein the gate 30 is disposed on the buffer layer 20, and an area of ​​a lower surface of the gate 30 is smaller than an area of ​​an upper surface of the gate 30;

[0060] A gate insulating layer 40 is disposed on the buffer layer 20 and covers the outer surface of the gate 30 , wherein the gate insulating layer 40 includes a first insulating portion 41 , and the first insulating portion 41 covers at least a portion of a side surface of the gate 30 ;

[0061] a semiconductor layer 50 covering the gate insulating layer 40 , wherein the semiconductor layer 50 includes a channel portion 51 , and the channel portion 51 covers the first insulating portion 41 ; and

[0062] A second metal layer is provided on the semiconductor layer 50, and the second metal layer includes a first electrode 61 and a second electrode 62 which are arranged at intervals, wherein the first electrode 61 is located on one side of the gate 30, and the second electrode 62 is located above the gate 30, and the second electrode 62 and the first electrode 61 are arranged in different layers;

[0063] The orthographic projection of the channel portion 51 on the substrate 10 is located within the range of the orthographic projection of the second electrode 62 on the substrate 10 .

[0064] See also Figure 1 and Figure 2In the present application, the area of ​​the lower surface of the gate 30 is smaller than the area of ​​the upper surface of the gate 30. At this time, an undercut structure is formed between the side of the gate 30 and the buffer layer 20. At this time, a conformal gate insulating layer 40 and a semiconductor layer 50 can be sequentially formed on the buffer layer 20 by a film forming method with good step coverage. Since the gate insulating layer 40 and the semiconductor layer 50 are conformal, the gate insulating layer 40 and the semiconductor layer 50 will not be disconnected at the undercut structure 80. A non-conformal second metal layer is then formed on the semiconductor layer 50 by a film-forming method with poor step coverage. Due to the poor step coverage of the second metal layer, the film-forming method automatically disconnects at the undercut structure 80 to form a first electrode 61 and a second electrode 62 that are spaced apart. In the process of patterning the second metal layer, since the first insulating portion 41 and the channel portion 51 cover the undercut structure 80, and the second electrode 62 is located above the undercut structure 80, the second electrode 62 can protect the back channel of the channel portion 51 from being etched, thereby improving the mobility of the TFT device and thus improving the stability of the TFT device.

[0065] See also Figure 2 The channel portion 51 of the semiconductor layer 50 includes a front channel and a back channel, wherein the front channel is a side of the channel portion 51 close to the gate 30 , and the back channel is a side of the channel portion 51 away from the gate 30 .

[0066] See also Fig.10 In a conventional display panel 100, the channel portion 51 of the semiconductor layer 50 is exposed on the second metal layer. During the patterning process of the second metal layer, the back channel (the side of the channel portion 51 away from the gate 30) of the semiconductor layer 50 will be etched, resulting in a decrease in the mobility of the TFT device.

[0067] See also Figure 2 When the area of ​​the lower surface of the gate 30 is smaller than the area of ​​the upper surface of the gate 30, an undercut structure 80 is formed between at least one side surface of the gate 30 and the upper surface of the buffer layer 20. When the first insulating portion 41 and the channel portion 51 cover the inner wall of the undercut structure 80, the second electrode 62 located above the channel portion 51 can protect the channel portion 51, so that the back channel of the channel portion 51 is not etched, thereby improving the mobility of the TFT device.

[0068] See also Figure 2 In the present application, since the first electrode 61 is arranged on one side of the gate 30, and the orthographic projection of the first electrode 61 on the substrate 10 and the orthographic projection of the gate 30 on the substrate 10 do not overlap, the parasitic capacitance generated by the overlap of the first metal layer and the second metal layer is reduced, the crosstalk generated inside the display panel 100 is reduced, and the display effect is improved.

[0069] See also Figure 2In the manufacturing process of the display panel 100, the gate insulating layer 40 and the semiconductor layer 50 are made by atomic layer deposition (ALD). The film forming method of atomic layer deposition has good step coverage. When the film is formed at the bottom cut structure 80, the film layer will not be disconnected, and the film formation has good conformality.

[0070] See also Figure 2 In the manufacturing process of the display panel 100, the second metal layer is manufactured by physical vapor deposition (PVD). The film forming method of physical vapor deposition has poor step coverage. When the film is formed at the bottom cut structure 80, the film layer will be disconnected to form a first electrode 61 and a second electrode 62 that are spaced apart. The film forming method of physical vapor deposition has non-conformal properties.

[0071] See also Figure 2 Through the undercut structure 80 and physical vapor deposition, the second metal layer is automatically disconnected at the undercut structure 80 to form the first electrode 61 and the second electrode 62 .

[0072] See also Figure 2 In this embodiment, the channel portion 51 is disposed on the side of the gate 30 to form a vertical channel. The length of the channel portion 51 is similar to the length of the side of the gate 30, which is easy to form a short channel and a small size device.

[0073] In this embodiment, the thickness of the gate 30 is about 1000 angstroms. The thickness of the gate insulating layer 40 is in the range of 500 angstroms to 2000 angstroms. The angle between the side surface of the gate 30 and the upper surface of the buffer layer 20 is in the range of 45° to 80°.

[0074] See also Figure 2 The length of the channel portion 51 is determined by the thickness of the gate 30, the thickness of the gate insulating layer 40, and the angle between the side of the gate 30 and the upper surface of the buffer layer 20. Compared with a planar channel, it has a shorter channel length, thereby increasing the on-state current of the TFT device.

[0075] The ratio of the area of ​​the upper surface of the gate to the area of ​​the lower surface of the gate is greater than 1, and the ratio of the area of ​​the upper surface of the gate to the area of ​​the lower surface of the gate is less than 2.

[0076] The ratio of the area of ​​the upper surface of the gate to the area of ​​the lower surface of the gate is one of 1.05, 1.10, 1.15, 1.20, 1.25, 1.30, 1.35, 1.40, 1.45, 1.50, 1.55, 1.60, 1.65, 1.70, 1.75, 1.80, 1.85, 1.90, and 1.95.

[0077] See also Figure 1 and Figure 2 In one embodiment of the present application, the orthographic projection of the lower surface of the gate 30 on the substrate 10 is located within the range of the orthographic projection of the upper surface of the gate 30 on the substrate 10 .

[0078] An undercut structure 80 is formed between the outer peripheral surface of the gate 30 and the upper surface of the buffer layer 20. At this time, the undercut structure 80 is arranged around the outer peripheral surface of the gate 30 to form an annular vertical channel arranged around the outer peripheral surface of the gate 30. At this time, the width of the channel portion 51 is determined by the circumference of the side surface of the gate 30, thereby improving the width-to-length ratio of the TFT device, thereby improving the on-state current of the TFT device.

[0079] In one embodiment of the present application, the semiconductor layer 50 further includes:

[0080] a first doped portion 52 disposed on the gate insulating layer 40 and located on one side of the gate 30; and

[0081] A second doping portion 53 is disposed on the gate insulating layer 40 and above the gate 30 , and the second doping portion 53 and the first doping portion 52 are disposed in different layers;

[0082] The channel portion 51 connects the first doped portion 52 and the second doped portion 53 , the first electrode 61 is disposed on an upper surface of the first doped portion 52 , and the second electrode 62 is disposed on an upper surface of the second doped portion 53 .

[0083] See also Figure 2 , doping the source and drain regions of the semiconductor layer 50 to form a first doping portion 52 and a second doping portion 53, the first doping portion 52 and the second doping portion 53 are located at both ends of the channel portion 51, the first electrode 61 is disposed on the upper surface of the first doping portion 52, and the first electrode 61 is in ohmic contact with the first doping portion 52. The second electrode 62 is disposed on the upper surface of the second doping portion 53, and the second electrode 62 is in ohmic contact with the second doping portion 53.

[0084] In one embodiment of the present application, the orthographic projection of the channel portion 51 on the substrate 10 overlaps with the orthographic projection of the second doped portion 53 on the substrate 10 ; the orthographic projection of the channel portion 51 on the substrate 10 overlaps with the orthographic projection of the first doped portion 52 on the substrate 10 .

[0085] See also Figure 2Since the side surface of the gate 30 and the upper surface of the buffer layer 20 form an undercut structure 80, the channel portion 51 covers at least part of the side surface of the gate 30, and the first doping portion 52 and the second doping portion 53 are respectively connected to the channel portion 51. Therefore, in the direction perpendicular to the substrate 10, the channel portion 51 overlaps with the second doping portion 53, and the channel portion 51 overlaps with the first doping portion 52.

[0086] In one embodiment of the present application, the gate insulating layer 40 further includes:

[0087] a second insulating portion 42 disposed on the buffer layer 20 and located on one side of the gate 30; and

[0088] A third insulating portion 43 is provided on the upper surface of the gate 30;

[0089] The first insulating portion 41 connects the second insulating portion 42 and the third insulating portion 43 , the first doped portion 52 is disposed on the upper surface of the second insulating portion 42 , and the second doped portion 53 is disposed on the upper surface of the third insulating portion 43 .

[0090] See also Figure 2 The second insulating portion 42 and the first doped portion 52 are stacked on the upper surface of the buffer layer 20 , the first insulating portion 41 and the channel portion 51 are stacked on the side of the gate 30 , and the third insulating portion 43 and the second doped portion 53 are stacked on the upper surface of the gate 30 .

[0091] In one embodiment of the present application, the first insulating portion 41 covers the outer peripheral surface of the gate 30, the second insulating portion 42 is disposed around the periphery of the gate 30, and the third insulating portion 43 covers the upper surface of the gate 30;

[0092] The second doped portion 53 covers the upper surface of the third insulating portion 43 , and the second electrode 62 covers the upper surface of the second doped portion 53 ;

[0093] The first doped portion 52 covers the upper surface of the second insulating portion 42 , the first electrode 61 covers the upper surface of the first doped portion 52 , and the first doped portion 52 is disposed around the periphery of the gate 30 .

[0094] See also Figure 4 , Figure 5 and Figure 6The width-to-length ratio of a TFT device is an important parameter that determines whether the TFT device can effectively control current and voltage. In the present application, the width of the TFT device is determined by the length of the channel portion 51 extending in the circumferential direction of the side of the gate 30, and the length of the TFT device is determined by the length of the channel portion 51 extending in the axial direction of the side of the gate 30. In order to improve the width-to-length ratio of the TFT device, the width of the TFT device can be increased.

[0095] When the channel portion 51 is disposed around the outer peripheral surface of the gate 30 , the width of the channel portion 51 is the largest. At this time, the TFT device has the largest width, so that the gate control performance of the TFT is improved.

[0096] In an embodiment of the present application, the orthographic projection of the semiconductor layer 50 on the substrate 10 is located within the range of the orthographic projection of the second metal layer on the substrate 10 .

[0097] like Figure 1 and Figure 2 As shown, in the direction perpendicular to the substrate 10, the first electrode 61 and the second electrode 62 in the second metal layer block the first doped portion 52, the second doped portion 53 and the channel portion 51 of the semiconductor layer 50, thereby reducing the etching of the semiconductor layer 50 by the etching solution, increasing the on-state current of the TFT device, and ensuring the stability of the TFT device structure.

[0098] In one embodiment of the present application, the gate 30 includes:

[0099] A first film layer 31 is disposed on the buffer layer 20; and

[0100] A second film layer 32, disposed on the first film layer 31;

[0101] The orthographic projection of the first film layer 31 on the substrate 10 is located within the range of the orthographic projection of the second film layer 32 on the substrate 10 , and the first insulating portion 41 covers the side surfaces of the first film layer 31 and the second film layer 32 .

[0102] See also Figure 3 The gate 30 layer includes a first film layer 31 and a second film layer 32, wherein the first film layer 31 is used as a sacrificial layer. After the gate 30 is formed, the gate 30 is patterned by using an etching solution with a faster etching speed for the first film layer 31, so as to form the first film layer 31 and the second film layer 32 with different sizes after patterning. The area of ​​the upper surface of the first film layer 31 and the area of ​​the lower surface of the first film layer 31 are both smaller than the area of ​​the lower surface of the second film layer 32.

[0103] In this embodiment, the gate 30 of the stacked structure will form a step-shaped undercut structure 80 due to different etching rates. Figure 2In the undercut structure 80 with a middle bevel shape, the second metal layer is disconnected more completely at the step-shaped undercut structure 80 , thereby reducing the risk of short circuit caused by incomplete disconnection between the first electrode 61 and the second electrode 62 , and improving the yield of the display panel 100 .

[0104] In this embodiment, the material of the first film layer 31 may be tungsten (W), and the material of the second film layer 32 may be molybdenum. In the stacked gate 30 composed of tungsten and molybdenum, tungsten as a sacrificial layer makes the molybdenum metal grain size larger and the overall resistivity lower. Preferably, the thickness of the first film layer 31 made of tungsten is in the range of 50 angstroms to 300 angstroms, and the thickness of the second film layer 32 made of molybdenum is in the range of 2000 angstroms to 5000 angstroms.

[0105] Correspondingly, the first film layer 31 and the second film layer 32 may also be other materials, such as metals such as titanium and molybdenum, wherein the first film layer 31 and the second film layer 32 are made of different materials to have different etching rates.

[0106] In one embodiment of the present application, the display panel 100 further includes a light shielding layer 70 , wherein the light shielding layer 70 is disposed on the substrate 10 , and the buffer layer 20 covers the light shielding layer 70 ;

[0107] The orthographic projection of the channel portion 51 on the substrate 10 is located within the range of the orthographic projection of the light shielding layer 70 on the substrate 10 .

[0108] The material of the semiconductor layer 50 is indium gallium zinc oxide (IGZO), and preferably, the material of the semiconductor layer 50 is amorphous indium gallium zinc oxide (a-IGZO). The semiconductor layer 50 formed by amorphous indium gallium zinc oxide has the characteristics of high carrier mobility, low off-state current, high uniformity, low process temperature, etc., and has important applications in AMLCD and AMOLED displays. However, the semiconductor layer 50 formed by indium gallium zinc oxide will generate leakage current when exposed to light, which has a great impact on TFT devices. In this embodiment, a light shielding layer 70 is provided between the buffer layer 20 and the substrate 10 to shield the light incident from the backlight side to ensure the stability of the performance of the TFT device.

[0109] The material of the light shielding layer 70 can be a black color resist or a metal.

[0110] In order to enhance the gate control performance of the gate 30 , a light shielding layer 70 made of a metal material may be selected, and the gate 30 and the light shielding layer 70 are electrically connected.

[0111] See also Figure 2 and Figure 3 The light shielding layer 70 shields the light from the backlight direction, thereby reducing the leakage current of the TFT device.

[0112] See also Figure 5 and Figure 6 The light shielding layer 70 blocks the light from the backlight direction toward the channel portion 51 arranged on the outer peripheral surface of the surrounding gate 30, thereby reducing the leakage current of the TFT device.

[0113] See also Figure 7 , Figure 8 and Fig. 9 The light shielding layer 70 and the gate electrode 30 block the light from the backlight direction toward the recessed portion 90 , thereby reducing the leakage current of the TFT device.

[0114] The present application also proposes a display panel 100, comprising:

[0115] Substrate 10;

[0116] A buffer layer 20, disposed on the substrate 10;

[0117] A first metal layer, comprising a gate 30, wherein the gate 30 is disposed on the buffer layer 20, and a recess 90 is disposed on at least a portion of a side surface of the gate 30;

[0118] A gate insulating layer 40 is disposed on the buffer layer 20 and covers the outer surface of the gate 30 , wherein the gate insulating layer 40 includes a first insulating portion 41 , and the first insulating portion 41 covers the recessed portion 90 ;

[0119] a semiconductor layer 50 covering the gate insulating layer 40 , wherein the semiconductor layer 50 includes a channel portion 51 , and the channel portion 51 covers the first insulating portion 41 ; and

[0120] A second metal layer is provided on the semiconductor layer 50, and the second metal layer includes a first electrode 61 and a second electrode 62 which are arranged at intervals, wherein the first electrode 61 is located on one side of the gate 30, and the second electrode 62 is located above the gate 30, and the second electrode 62 and the first electrode 61 are arranged in different layers;

[0121] The orthographic projection of the channel portion 51 on the substrate 10 is located within the range of the orthographic projection of the second electrode 62 on the substrate 10 .

[0122] In this embodiment, at least part of the side of the gate 30 is provided with a recessed portion 90. At this time, the part of the side of the gate 30 provided with the recessed portion 90 forms an undercut structure. At this time, a conformal gate insulating layer 40 and a semiconductor layer 50 can be sequentially formed on the buffer layer 20 by a film forming method with good step coverage. Since the gate insulating layer 40 and the semiconductor layer 50 are conformal, the gate insulating layer 40 and the semiconductor layer 50 will not be disconnected at the undercut structure 80. Then, a non-conformal second metal layer is formed on the semiconductor layer 50 by a film forming method with poor step coverage. Due to the poor step coverage, the second metal layer will be automatically disconnected at the undercut structure 80 to form a first electrode 61 and a second electrode 62 arranged at intervals. In the process of patterning the second metal layer, since the first insulating portion 41 and the channel portion 51 cover the undercut structure 80, and the second electrode 62 is located above the undercut structure 80, the second electrode 62 can protect the back channel of the channel portion 51 from being etched, thereby improving the mobility of the TFT device, thereby improving the stability of the TFT device.

[0123] like Figure 7 , Figure 8 and Fig. 9 As shown, the cross-sectional shape of the recessed portion 90 may be an arc, a rectangle, or a triangle.

[0124] See also Figure 7 and Figure 8 The cross-sectional shape of the recessed portion 90 is an arc and a triangle, and the portion of the side of the gate 30 provided with the recessed portion 90 forms an undercut structure 80, and the first electrode 61 and the second electrode 62 of the second metal layer are disconnected at the undercut structure 80, and the second electrode 62 is shielded above the undercut structure 80. At this time, the channel portion 51 and the first insulating portion 41 are arranged on the inner wall of the undercut structure 80, and the second electrode 62 can protect the back channel of the channel portion 51 from damage during the patterning of the second metal layer.

[0125] See also Fig. 9 , the gate 30 includes a first film layer 31, a second film layer 32 and a third film layer 33;

[0126] A first film layer 31, disposed on the buffer layer 20;

[0127] A second film layer 32, disposed on the first film layer 31; and

[0128] The third film layer 33 is provided between the first film layer 31 and the buffer layer 20;

[0129] The orthographic projection of the first film layer 31 on the substrate 10 is within the range of the orthographic projection of the second film layer 32 on the substrate 10, and the orthographic projection of the first film layer 31 on the substrate 10 is within the range of the orthographic projection of the third film layer 33 on the substrate 10;

[0130] The first insulating portion 41 covers side surfaces of the first film layer 31 , the second film layer 32 and the third film layer 33 .

[0131] See also Fig. 9 The gate 30 of the stacked structure will form a step-shaped undercut structure 80 due to the different etching rates. Figure 2 In the undercut structure 80 with a middle bevel shape, the second metal layer is disconnected more completely at the step-shaped undercut structure 80 , thereby reducing the risk of short circuit caused by incomplete disconnection between the first electrode 61 and the second electrode 62 , and improving the yield of the display panel 100 .

[0132] In one embodiment, the material of the first film layer 31 is aluminum, the material of the second film layer 32 is titanium, and the material of the third film layer 33 is titanium.

[0133] In another embodiment, the material of the first film layer 31 is aluminum, the material of the second film layer 32 is molybdenum, and the material of the third film layer 33 is molybdenum.

[0134] In the above embodiments, the etching rate of the first film layer 31 is faster than the etching rate of the second film layer 32 , and the etching rate of the first film layer 31 is faster than the etching rate of the third film layer 33 .

[0135] The above is a detailed description of the specific implementation of the present application. The above implementation disclosed in the present application is only the preferred implementation of the present application. For ordinary technicians in this field, many modifications and improvements can be made without departing from the concept of the present application. These modifications and improvements all fall within the scope of protection defined by the claims of the present application.

Claims

1. A display panel, characterized in that: include: substrate; A buffer layer, disposed on the substrate; A first metal layer, comprising a gate, wherein the gate is disposed on the buffer layer, and an area of ​​a lower surface of the gate is smaller than an area of ​​an upper surface of the gate; a gate insulating layer, disposed on the buffer layer and covering an outer surface of the gate, the gate insulating layer comprising a first insulating portion, the first insulating portion covering at least a portion of a side surface of the gate; A semiconductor layer covering the gate insulating layer, wherein the semiconductor layer includes a channel portion, and the channel portion covers the first insulating portion; and A second metal layer is provided on the semiconductor layer, the second metal layer comprises a first electrode and a second electrode which are arranged at intervals, wherein the first electrode is located on one side of the gate, the second electrode is located above the gate, and the second electrode and the first electrode are arranged in different layers; The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the second electrode on the substrate.

2. The display panel according to claim 1, wherein: The orthographic projection of the lower surface of the gate on the substrate is located within the range of the orthographic projection of the upper surface of the gate on the substrate.

3. The display panel according to claim 2, wherein: The semiconductor layer further comprises: a first doped portion, disposed on the gate insulating layer and located on one side of the gate; and a second doping portion, disposed on the gate insulating layer and above the gate, wherein the second doping portion and the first doping portion are disposed in different layers; The channel portion connects the first doped portion and the second doped portion, the first electrode is disposed on an upper surface of the first doped portion, and the second electrode is disposed on an upper surface of the second doped portion.

4. The display panel according to claim 3, wherein: An orthographic projection of the channel portion on the substrate overlaps with an orthographic projection of the second doped portion on the substrate; An orthographic projection of the channel portion on the substrate overlaps with an orthographic projection of the first doped portion on the substrate.

5. The display panel according to claim 3, wherein: The gate insulating layer further comprises: a second insulating portion, disposed on the buffer layer and located on one side of the gate; and A third insulating portion, provided on the upper surface of the gate; The first insulating portion connects the second insulating portion and the third insulating portion, the first doped portion is disposed on an upper surface of the second insulating portion, and the second doped portion is disposed on an upper surface of the third insulating portion.

6. The display panel according to claim 5, characterized in that: The first insulating portion covers the outer peripheral surface of the gate, the second insulating portion is arranged around the periphery of the gate, and the third insulating portion covers the upper surface of the gate; Wherein, the second doped portion covers the upper surface of the third insulating portion, and the second electrode covers the upper surface of the second doped portion; The first doped portion covers an upper surface of the second insulating portion, the first electrode covers an upper surface of the first doped portion, and the first doped portion is disposed around a periphery of the gate.

7. The display panel according to claim 1, wherein: The orthographic projection of the semiconductor layer on the substrate is located within the range of the orthographic projection of the second metal layer on the substrate.

8. The display panel according to claim 1, wherein: The gate comprises: A first film layer is disposed on the buffer layer; and A second film layer, disposed on the first film layer; The orthographic projection of the first film layer on the substrate is located within the range of the orthographic projection of the second film layer on the substrate, and the first insulating portion covers the side surfaces of the first film layer and the second film layer.

9. The display panel according to any one of claims 1 to 8, characterized in that: The display panel further includes a light shielding layer, which is disposed on the substrate, and the buffer layer covers the light shielding layer; The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the light shielding layer on the substrate.

10. A display panel, characterized in that: include: substrate; A buffer layer, disposed on the substrate; A first metal layer, comprising a gate, wherein the gate is disposed on the buffer layer, and at least a portion of a side surface of the gate is provided with a recessed portion; a gate insulating layer, disposed on the buffer layer and covering an outer surface of the gate, the gate insulating layer comprising a first insulating portion, the first insulating portion covering the recessed portion; A semiconductor layer covering the gate insulating layer, wherein the semiconductor layer includes a channel portion, and the channel portion covers the first insulating portion; and A second metal layer is provided on the semiconductor layer, the second metal layer comprises a first electrode and a second electrode which are arranged at intervals, wherein the first electrode is located on one side of the gate, the second electrode is located above the gate, and the second electrode and the first electrode are arranged in different layers; The orthographic projection of the channel portion on the substrate is located within the range of the orthographic projection of the second electrode on the substrate.

Images