Compensation mark carrier and molding panel for compensating for die offset of semiconductor die generated in compression molding

Abstract

The application discloses a compensation mark carrier and a molding panel for compensating for die offset of a semiconductor die generated in compression molding. The compensation mark carrier comprises a blank carrier; and a plurality of physical carrier marks formed on the blank carrier. Wherein the physical carrier mark is formed at a compensation projection mark, the compensation projection mark is transformed from an original projection mark by applying a compensation factor in a computing device, and the original projection mark is generated by projection of an original virtual carrier mark. And the original virtual carrier mark originates from an original design file; wherein the original projection mark and the compensation projection mark are respectively used for determining an original gap and a compensation gap between two adjacent semiconductor bare chips, and the bare chip offset caused by compression molding is compensated by changing the original gap into the compensation gap when the semiconductor bare chips are bonded on the compensation mark carrier.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims the priority of Singapore application 10202301381R, filed on May 17, 2023, the disclosure of which is incorporated in its entirety into this patent application. Technical Field

[0003] The present application relates to a compensating mark carrier for compensating for die deviation of a semiconductor die during compression molding. The present application also relates to a molding panel for manufacturing a panel-level semiconductor package. Background Art

[0004] At present, there is a serious problem of die shift in the compression molding process, that is, due to various effects such as thermal-mechanical effects and mold compound fluid flow effects, the bonded semiconductor die will deviate from its originally designed position. Die shift will cause misalignment in subsequent processes after compression molding. The bonded semiconductor die may experience expansion during compression molding, that is, the die will move away from each other, so the gap between two adjacent semiconductor die will increase. Alternatively, the bonded semiconductor die may also experience contraction during compression molding, that is, the die will move closer to each other, so the gap between two adjacent semiconductor die will decrease. If the semiconductor die expands or contracts during the compression molding process, it may cause misalignment in subsequent processes. Utility Model Content

[0005] Therefore, the present application discloses a die carrier that can solve the die offset problem in compression molding, thereby improving the manufacturing yield of semiconductor packages.

[0006] As a first aspect of the present application, a compensation mark carrier for compensating for die offset generated by semiconductor die during compression molding is disclosed. The compensation mark carrier includes a blank carrier; and a plurality of physical carrier marks formed on the blank carrier. The physical carrier mark is formed at a compensation projection mark, the compensation projection mark is transformed from an original projection mark by applying a compensation factor in a computing device, the original projection mark is generated by an original virtual carrier mark through projection, and the original virtual carrier mark is derived from an original design file; the original projection mark and the compensation projection mark are respectively used to determine an original gap and a compensation gap between two adjacent semiconductor die, and the die offset caused by the compression molding is compensated by changing the original gap to a compensation gap when the semiconductor die is bonded to the compensation mark carrier.

[0007] As a second aspect of the present application, a molded panel for manufacturing panel-level semiconductor packages is disclosed. The molded panel includes a plurality of semiconductor die located on a compensation mark carrier having a physical carrier mark, and a molded layer formed by compression molding for encapsulating the semiconductor die therein. The physical carrier mark is formed at a compensation projection mark, the compensation projection mark is transformed from an original projection mark by applying a compensation factor in a computing device, the original projection mark is generated by an original virtual carrier mark by projection, and the original virtual carrier mark is derived from an original design file; the original projection mark and the compensation projection mark are used to determine the original gap and the compensation gap between two adjacent semiconductor die, respectively, and the die offset caused by the compression molding is compensated by changing the original gap to the compensation gap when the semiconductor die is bonded to the compensation mark carrier. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings show embodiments of the present application for explaining the principles disclosed in the present application. However, it should be understood that these drawings are for illustrative purposes only and are not intended to limit the scope of the present application.

[0009] Figure 1a and Figure 1b An example of a conventional marking carrier is shown.

[0010] Figure 2 FIG. 4 is a flow chart of a method S10 for manufacturing a compensation mark carrier according to an exemplary embodiment of the present application.

[0011] Figure 3a and Figure 3b Shows Figure 2 Schematic diagram of step S11 of method S10.

[0012] Figure 4a A schematic diagram of a computing device is shown.

[0013] Figure 4b A simulation diagram of the computing device-to-die offset is shown.

[0014] Figure 5a and Figure 5b Shows Figure 2 Schematic diagram of step S13 of method S10 in FIG.

[0015] Figures 6a to 6d Shows Figure 2 Schematic diagram of step S15 of method S10.

[0016] Figure 7A flow chart of a compensation method S20 for compression molding using the compensation marking carrier manufactured by the method S10 according to an exemplary embodiment of the present disclosure is shown.

[0017] Figures 8a to 8c A schematic diagram showing step S21 of the compensation method S20 is shown.

[0018] Figure 9a A schematic diagram of one embodiment of a vision device for aligning an active die onto a compensation mark carrier is shown.

[0019] Figure 9b A schematic diagram of another embodiment of a visual device is shown.

[0020] Figures 10a to 10c A schematic diagram showing a method for aligning an active die and a compensation bonding unit is shown.

[0021] Fig.11a and Fig.11b A schematic diagram of an active die and a reference die bonded to a compensation mark carrier is shown.

[0022] Fig.12a and Figure 12b A schematic diagram showing step S23 of the compensation method S20 is shown.

[0023] Fig.13 A schematic diagram showing the release process in step S24 of the compensation method S20 is shown.

[0024] Fig.14 A schematic diagram showing the transfer process in step S24 of the compensation method S20 is shown.

[0025] Fig.15 A schematic diagram of a die location check (DLC) is shown.

[0026] Fig.16a and Fig.16b Schematic diagram showing the results of die location check (DLC) of active and reference dies in a molded panel.

[0027] Fig.17a and Fig.17b A statistical graph of die misalignment before and after compression molding is shown.

[0028] Figures 18a to 18c A schematic diagram showing step S25 of the compensation method S20 is shown.

[0029] Fig.19 A schematic diagram showing step S26 of the compensation method S20 is shown.

[0030] Fig. 20A schematic diagram showing step S27 of the compensation method S20 is shown.

[0031] Fig.21a and Figure 21b A schematic diagram showing step S28 of the compensation method S20 is shown.

[0032] Fig.22a and Figure 22b A schematic diagram showing step S29 of the compensation method S20 is shown.

[0033] Fig.23 A schematic diagram showing the application of the compensation method S20 to a single chip module is shown.

[0034] Fig.24 A schematic diagram showing the division of the compensation mark carrier into a plurality of blocks and sub-blocks is shown.

[0035] Fig.25a and Fig.25b An example of a multi-chip module (MCM) is shown before and after bonding the active die to a compensating marking carrier.

[0036] Fig.26 A schematic diagram showing the application of the compensation method S20 to a multi-chip module (MCM) is shown. DETAILED DESCRIPTION

[0037] Figure 1a FIG. 6 is an example of a side top view of a conventional marking carrier 600. The conventional marking carrier 600 may carry a plurality of semiconductor dies that will undergo a variety of processes including compression molding. The conventional marking carrier 600 includes a plurality of markings 620 (e.g., Figure 1a ), which is used to provide position information for bonding a semiconductor die to a conventional marking carrier 600. Four adjacent markings 620 located at four corners can define a bonding unit 610, which can accommodate one or more semiconductor dies. Figure 1a Indicated by a dashed rectangle. Figure 1b An example of an enlarged side top view of a bonding unit 610 is shown. Four adjacent marks 620 are identified by four black dots located at the four corners of the bonding unit 610. A semiconductor die 630 is bonded at a bonding location 640 (as identified by a white dashed rectangle) located within the bonding unit 610. When compression molding is performed on a conventional mark carrier 600, the semiconductor die 630 will be as shown in FIG. Figure 1b As shown by the middle arrow, it moves from the bonding position 640 to the offset position 650 (as indicated by the white dotted rectangle).

[0038] Figure 2FIG. 1 is a flow chart of a method S10 for manufacturing a compensation mark carrier 108 according to an exemplary embodiment of the present disclosure. The method S10 includes steps S11, S13, and S15. Step S11 is as follows: Figure 3a and 3b shown.

[0039] Figure 3a A cross-sectional view of a portion of a blank carrier 100 and a schematic diagram of a computing device 110 are shown. The blank carrier 100 has a relatively flat front surface 102 without any observable marks or indentations. The computing device 110 may be a server for storing an original design file. The original design file includes information about the blank carrier 100, the distribution of original virtual carrier marks 112 on the blank carrier 100, and an original virtual distance 114 between two adjacent original virtual carrier marks 112. Based on the distribution of the original virtual carrier marks 112 stored in the computing device 110, an original projection mark 104 may be determined by projecting it onto the front surface 102 of the blank carrier 100. The projection is as shown in FIG. Figure 3a It should be noted that the original projected mark 104 is also fictitious in nature, rather than being physically formed on the blank carrier 100. Therefore, the front surface 102 remains flat and has no observable marks or indentations.

[0040] In one embodiment, the computing device 110 generates a virtual reference 1122 as the origin (0, 0) of a Cartesian coordinate system, wherein the position of the original virtual carrier mark 112 is represented by its corresponding coordinates (x, y) in the Cartesian coordinate system. The coordinate system is generated by the computing device 110. At the same time, the blank carrier 100 has a carrier reference 1002 on its front surface 102. The carrier reference 1002 may be a feature of the blank carrier 100, such as an edge or corner of the blank carrier 100. Alternatively, the carrier reference 1002 may be intentionally made on the front surface 102 of the blank carrier 100, such as a small dot made temporarily or permanently. The carrier reference 1002 may be provided with the blank carrier 100. Alternatively, the carrier reference 1002 may be made or found on the blank carrier 100 when using the method S10. Then, by superimposing the virtual reference 1122 onto the carrier reference 1002, the Cartesian coordinate system generated by the computing device 110 is copied onto the front surface 102 of the blank carrier 100. The carrier reference 1002 can be used as the origin (0, 0) of the Cartesian coordinate system replicated on the blank carrier 100. Then, the corresponding coordinates (x, y) of the original virtual carrier mark 112 in the Cartesian coordinate system remain the same as the coordinates (x, y) of the Cartesian coordinate system replicated on the blank carrier 100, which are used to indicate the position of the original projection mark 104 on the front surface 102. In this way, the original virtual carrier mark 112 is projected onto the blank carrier 100 to form the original projection mark 104. And, the original virtual distance 114 remains the same as the distance between adjacent original projection marks 104. It can be understood that the projection method described is only an exemplary embodiment, and other methods similar to the projection method described are also within the scope of the present application.

[0041] Figure 3b A portion of a blank carrier 100 and a top view of an original projection mark 104 projected from an original virtual carrier mark 112 stored in a computing device 110 onto the blank carrier 100 are shown. Therefore, the original virtual distance 114 between two adjacent original virtual carrier marks 112 stored in the computing device 110 is the same as the distance between two adjacent original projection marks 104 on the front surface 102 of the blank carrier 100. Then, Figure 3bAn original bonding unit 122 defined by four adjacent original projection marks 1042-1048 (i.e., a first original projection mark 1042, a second original projection mark 1044, a third original projection mark 1046, and a fourth original projection mark 1048) is shown, represented by a dashed rectangle. The original bonding unit 122 will accommodate one or more semiconductor dies. In order to save space on the blank carrier 100, the original projection mark 104 can be shared by adjacent original bonding units 122. As shown, the original bonding units 122, 122' adjacent in a row share the second original projection mark 1044 and the fourth original projection mark 1048; the original bonding units 122, 122" adjacent in a column share the third original projection mark 1046 and the fourth original projection mark 1048. Figure 3b This portion of the blank carrier 100 is shown to have 8 columns and 3 rows of original projection marks 104. Therefore, this portion of the blank carrier 100 has 2 rows of original bonding units 122, and 7 original bonding units 122 in each row. In general, this portion of the blank carrier 100 has 14 original bonding units 122. This portion may represent the situation of original projection marks 104 and original bonding units 122 on other portions of the blank carrier 100. Preferably, the original projection marks 104 are evenly distributed, and their intervals are the same, which are all original virtual distances 114. Therefore, the original bonding units 122 are also evenly distributed on the blank carrier 100. Similar to the original projection marks 104, the original bonding units 122 are essentially fictitious and are not physically formed on the blank carrier 100.

[0042] Figure 3b It is shown that if two semiconductor dies 156 and 157 are respectively bonded to two adjacent original bonding units 122, then an original gap 158 is correspondingly formed between the edges of the two semiconductor dies 156 and 157. The original gap 158 can be calculated according to the original virtual distance 114 and the sizes of the semiconductor dies 156 and 157. In an embodiment in which the original projection marks 104 are uniformly distributed, if the semiconductor dies 156 and 157 are located at the center of their respective original bonding units 122 and have the same size, the original gap 158 is the difference between the original virtual distance 114 and the width of the semiconductor dies 156 and 157.

[0043] Figure 4a 1 shows a schematic diagram of a computing device 110. The computing device 110 includes a storage device 1102 for storing an original design file, and a computing device 1104 for adjusting the distribution of the original virtual carrier mark 112 and the corresponding original virtual distance 114. Specifically, the computing device 1104 also includes a simulation algorithm 1106 for predicting the adjustment of the distribution of the original virtual carrier mark 112 and the original virtual distance 114. Figure 4bA simulation graph 124 of die offset by the simulation algorithm 1106 is shown. The simulation graph 124 shows that the offset of the semiconductor die increases as it is farther from the center 126 of the simulation graph 124. Therefore, the semiconductor die located at the four corners 128 of the simulation graph 124 will have the largest offset during compression molding. In particular, the simulation graph 124 shows that the offset of the semiconductor die along the blank carrier 100 is linear within the precision tolerance, which means that even after adjustment, the semiconductor die will still be evenly distributed.

[0044] The simulation diagram 124 shows that the original gap 158 between two adjacent semiconductor dies 156, 157 has a significant effect on the deviation of the semiconductor dies 156, 157. For example, the original gap 158 can largely determine whether the semiconductor dies 156, 157 expand or contract during compression molding. In the case of expansion, the semiconductor dies 156, 157 tend to move outward, that is, away from the center 126 of the simulation diagram 124, and also away from each other. On the contrary, in the case of contraction, the semiconductor dies 156, 157 tend to move inward toward the center 126 of the simulation diagram 124 during compression molding, and also move closer to each other. For another example, in the case of expansion, the larger the original gap 158, the smaller the movement of the semiconductor dies 156, 157 during compression molding.

[0045] Figure 5a and Figure 5b 1 shows a schematic diagram of step S13 of the method S10. In step S13, firstly, a compensation factor 115 is calculated according to the simulation diagram 124 by the simulation algorithm 1106 of the computing device 110, and then the compensation factor 115 is applied to the original virtual carrier mark 112 for transforming the original virtual carrier mark 112 into a compensated virtual carrier mark 116. In the computing device 110, the original virtual distance 114 between two adjacent original virtual carrier marks 112 is correspondingly converted into a compensated virtual distance 118 between two adjacent compensated virtual carrier marks 116. The compensation factor 115 is calculated according to a plurality of parameters, but mainly the original gap 158 between two adjacent semiconductor dies 156, 157.

[0046] Figure 5a A schematic diagram of the compensating virtual carrier mark 116 in the computing device 110 is shown in the case where the expansion occurs during compression molding. In order to balance the expansion, the original virtual distance 114 is reduced to a smaller compensated virtual distance 118 by applying a compensation factor 115 before compression molding, even if the compensated virtual distance 118 is smaller than the original virtual distance 114. Therefore, in the same portion of the blank carrier 100, the computing device 110 generates more compensated virtual carrier marks 116 than the original virtual carrier marks 112. For example, Figure 5a9 compensating virtual carrier marks 116 are shown in each row, compared to Figure 3a Only eight original virtual carrier marks 112 are shown in FIG. Then, the compensated virtual carrier marks 116 are projected onto the front surface 102 to form compensated projection marks 105. Figure 5a As shown by the dashed arrow in . The compensated virtual carrier mark 116 can be projected to form the compensated projection mark 105 in the same way as the original virtual carrier mark 112 is projected to form the original projection mark 104, that is, the virtual reference 1122 in the computing device 110 and the carrier reference 1002 on the front surface 102 are overlapped. Then, the Cartesian coordinate system of the computing device 110 is copied to the blank carrier 100. It should be noted that the compensated projection mark 105 is still virtual in nature and is not physically formed on the blank carrier 100. The front surface 102 is still very flat and has no observable marks or notches. Since the compensated virtual distance 118 is smaller, the semiconductor die can be bonded more tightly by applying the compensation factor 115. In this way, the same portion of the blank carrier 100 can carry more semiconductor dies for compression molding and subsequent processes.

[0047] In the case of the shrinkage, before compression molding, the compensation factor 115 is applied to increase the original virtual distance 114 to a larger compensated virtual distance, that is, the larger compensated virtual distance is greater than the original virtual distance 114, so as to balance the shrinkage during compression molding. For the manufacture of six-sided fan-in semiconductor packages, offsetting the shrinkage is particularly important because its package outline is only slightly larger than the outline of the semiconductor die embedded therein. If the package gap between the six-sided fan-in semiconductor packages is too small, especially smaller than the width of the saw blade used in the cutting process, the semiconductor die packaged inside the six-sided fan-in semiconductor package may be damaged by the saw blade during the cutting process. The following figures describe the situation in which the expansion occurs during compression molding, but it can be understood that the present application is also applicable to the situation in which the shrinkage occurs during compression molding.

[0048] Therefore, the original gap 158 between two adjacent semiconductor dies 156, 157 will change with the compensation factor 115 used to adjust the original virtual carrier mark 112 and the original virtual distance 114 to the compensated virtual carrier mark 116 and the compensated virtual distance 118, respectively. The transformation can transform the original virtual distance 114 into a smaller compensated virtual distance 118 (applicable to the case of the expansion) or a larger compensated virtual distance (applicable to the case of the contraction). Then, during the compression molding process, due to the expansion or contraction, the compensated gap 159 will increase or decrease accordingly and return to the original gap 158 in the original design file stored in the computing device 110. At the same time, the simulation diagram 124 also shows that the offset of the semiconductor die is linear during the compression molding process. Therefore, the semiconductor die after compression molding are still evenly distributed, and the distance between every two adjacent semiconductor die is restored to the original gap 158. In short, no matter the expansion or contraction that the semiconductor die may experience during compression molding, the design specifications in the original design file of the semiconductor package will be retained.

[0049] Figure 5b 1 shows a top view of the same portion of the blank carrier 100 and the compensation projection mark 105 thereon. Similarly, after the above projection, the distance between two adjacent compensation virtual carrier marks 116 in the computing device 110 and the distance between two adjacent compensation projection marks 105 on the front surface 102 of the blank carrier 100 are the same, both of which are compensation virtual distance 118. Similarly, the compensation bonding unit 130 can be defined by four adjacent compensation projection marks 1052-1058 (i.e., the first compensation projection mark 1052, the second compensation projection mark 1054, the third compensation projection mark 1056 and the fourth compensation projection mark 1058), as shown in FIG. Figure 5b As shown by the dotted rectangle in . The compensation bonding unit 130 can accommodate one or more semiconductor dies. Similarly, adjacent compensation bonding units 130, 130' in each row share the second compensation projection mark 1054 and the fourth compensation projection mark 1058; and adjacent compensation bonding units 130, 130" in each column share the third compensation projection mark 1056 and the fourth compensation projection mark 1058. Since the compensation virtual distance 118 is smaller than the original virtual distance 114, more compensation projection marks 105 can be projected onto the blank carrier 100 in each row. Accordingly, more compensation bonding units 130 can be virtually defined on this portion of the blank carrier 100, thereby accommodating more semiconductor dies. Similar to the compensation projection mark 105, the compensation bonding unit 130 is essentially fictitious and is not physically made on the blank carrier 100.

[0050] When the semiconductor dies 156 and 157 are bonded to two adjacent compensation bonding units 130, Figure 5b A compensation gap 159 between the edges of the semiconductor dies 156, 157 is also shown. Similarly, the compensation gap 159 can be calculated based on the compensation virtual distance 118 and the size of the semiconductor dies 156, 157. In one embodiment, the compensation projection marks 105 are evenly distributed. If the semiconductor dies 156, 157 are located at the center of their respective compensation bonding units 130 and have the same size, the compensation gap 159 is the difference between the compensation virtual distance 118 and the width of the semiconductor dies 156, 157.

[0051] Regardless of the expansion or contraction, compression molding will cause the semiconductor die to shift, causing problems for subsequent processes. The present disclosure overcomes this problem by applying a compensation factor 115 to transform the original projection mark 104 on the blank carrier 100 into a compensated projection mark 105, so as to change the original virtual distance 114 to a compensated virtual distance 118, thereby changing the original gap 158 between adjacent semiconductor dies 156 and 157 to a compensated gap 159. During compression molding, the expansion or contraction between adjacent semiconductor dies 156 and 157 will be offset by the compensation effect of the compensation gap 159. Therefore, the distance between adjacent semiconductor dies 156 and 157 is also restored from the compensated gap 159 before compression molding to the original gap 158 of the original design file. As described above, the conversion from the original projection mark 104 to the compensated projection mark 105 can first convert the original virtual carrier mark 112 into the compensated virtual carrier mark 116 in the computing device 110. Then the compensated virtual carrier mark 116 is projected onto the blank carrier 100 to form the compensated projection mark 105. The distance between two adjacent compensation projection marks 105 remains the same as the compensation virtual distance 118 .

[0052] Figures 6a to 6d Shows Figure 2 Step S15 of the method S10 described in the above is to form a physical carrier mark 106 on the front surface 102 of the blank carrier 100 at the compensation projection mark 105, thereby making a compensation mark carrier 108. Preferably, the physical carrier mark 106 is accurately formed at the compensation projection mark 105 with a tolerance within 3 micrometers (μm). Figure 6a A cross-sectional view of a portion of a compensating mark carrier 108 having a physical carrier mark 106 is shown, corresponding to Figure 5a The portion of the blank carrier 100 is shown. Since the physical carrier mark 106 is formed at the compensation projection mark 105, the distance between two adjacent physical carrier marks 106 on the compensation mark carrier 108 remains the same as the compensation virtual distance 118.

[0053] The physical carrier mark 106 can be a groove permanently formed on the front surface 102 by any known technique, such as laser drilling, mechanical drilling, chemical etching, or any combination thereof. In this way, the physical carrier mark 106 cannot be removed without removing the front surface 102. As shown, the physical carrier mark 106 can take the form of a cylindrical groove 109. Figure 6b 1 shows an enlarged cross-sectional view of the cylindrical recess 109, which has a rectangular shape. Thus, the top surface 109a and the bottom surface 109b of the cylindrical recess 109 have the same circular area, both of which have a diameter of about 0.15 millimeters (mm), and a depth 109c in the range of 0.02 to 0.06 millimeters (mm). Preferably, the depth 109c of the cylindrical recess 109 is about 0.025 millimeters (mm). In particular, the cylindrical recess 109 has an edge 109d (such as Figure 6b ), which is free of any burrs, so that the physical carrier mark 106 can be accurately identified before the semiconductor die is bonded to the compensation mark carrier 108.

[0054] In another embodiment, the physical carrier marking 106 may take the form of a truncated groove 109'. Figure 6c An enlarged cross-sectional view of the truncated groove 109' is shown, which has a trapezoidal shape. Therefore, the top surface 109'a of the truncated groove 109' has a larger circular area than the bottom surface 109'b. In a preferred embodiment, the area ratio of the bottom surface 109'b to the top surface 109'a is in the range of 60% to 90%. For example, if the diameter of the top surface 109'a is 0.15 millimeters (mm), the diameter of the bottom surface 109'b is in the range of 0.09 to 0.135 millimeters (mm). The depth 109'c of the truncated groove 109' is in the range of 0.02 to 0.06 millimeters (mm). Preferably, the depth 109'c of the truncated groove 109' is approximately 0.025 millimeters (mm). Similarly, the truncated groove 109' has an edge 109'd (such as Figure 6d ), which is free of any burrs, so that the physical carrier mark 106 can be accurately identified before the semiconductor die is bonded to the compensation mark carrier 108.

[0055] Alternatively, a temporary physical carrier mark 106 may be formed, which can be erased while the front surface 102 remains intact, such as by painting or other similar known techniques. After compression molding, the physical carrier mark 106 can be removed by chemical cleaning without damaging the front surface 102 of the compensation mark carrier 108. At the same time, in order to resist the higher pressure during compression molding, the compensation mark carrier 108 (i.e., the previous blank carrier 100) can be made of a material with a larger Young's modulus to prevent warping during compression molding. In one embodiment, the compensation mark carrier 108 is made of alloy 46 with a Young's modulus of about 137.5 gigapascals (GPa). Depending on the thickness of the semiconductor die, the compensation mark carrier 108 has a corresponding carrier thickness. If the compensation mark carrier 108 is too thin, it cannot provide sufficient rigidity to support the semiconductor die bonded thereon, and may also warp during compression molding; at the same time, the compensation mark carrier 108 cannot be too thick, otherwise it will be troublesome during compression molding and subsequent processes. The carrier thickness also depends on the material used. For example, when the compensation mark carrier 108 is made of Alloy 46, if the thickness of the semiconductor die is about 0.35 millimeters (mm), the carrier thickness is about 2.2 millimeters (mm).

[0056] Figure 6d A top view of the portion of the compensation mark carrier 108 with the physical carrier mark 106 is shown. Since the physical carrier mark 106 is formed at the compensation projection mark 105, the compensation bonding unit 130 can also be defined on the compensation mark carrier 108. It is worth noting that the compensation bonding unit 130 is also fictitious in nature and is not physically made on the compensation mark carrier 108. The compensation bonding unit 130 can be composed of four adjacent physical carrier marks 1062-1068 (i.e., a first physical carrier mark 1062, a second physical carrier mark 1064, a third physical carrier mark 1066 and a fourth physical carrier mark 1068) for accommodating one or more semiconductor dies. And Figure 5b Consistently, adjacent compensation bonding units 130, 130' in a row share the second physical carrier mark 1064 and the fourth physical carrier mark 1068; and adjacent compensation bonding units 130, 130" in a column share the third physical carrier mark 1066 and the fourth physical carrier mark 1068. Figure 5b Accordingly, on this portion of the compensating marking carrier 108 there are eight compensating bonding units 130 in each row.

[0057] Figure 7 A flow chart of the compensation method S20 is shown. Figure 2After the method S10 shown manufactures the compensation mark carrier 108 with the physical carrier mark 106, the compensation method S20 can then be used in a compression molding process in a panel-level semiconductor process. The compensation method S20 includes steps S21 to S29.

[0058] Step S21 is as follows Figure 8a and 8b As shown, a heat release tape (or thermal release tape) 120 is applied to the front surface 102 of the compensating mark carrier 108 . Figure 8a A cross-sectional view of the thermal release tape 120 covering the physical carrier marking 106 is shown. Figure 8b A top view of the compensation bonding unit 130 is shown with the thermal release tape 120 covering it. On the one hand, the thermal release tape 120 can be fixed to the front surface 102 of the compensation marking carrier 108; on the other hand, the thermal release tape 120 can fix the semiconductor die. However, the adhesive force of the thermal release tape 120 is not strong enough to firmly hold the semiconductor die in place during compression molding. Therefore, the semiconductor die will shift under compression or shrinkage as described above.

[0059] The heat release tape 120 may have various structures as long as the bonding purpose can be achieved. For example, the heat release tape 120 may be a double-sided tape having a single polymer layer with adhesive on both sides of the single polymer layer. In another embodiment, the heat release tape 120 may have a Figure 8c The multi-layer laminate structure shown has a first liner 1201, a foaming adhesive 1203 for fixing the thermal release tape 120 on the front surface 102, a polyester film 1205 for providing structural support for the thermal release tape 120, a base adhesive 1207 for fixing the semiconductor die on the thermal release tape 120, and a second liner 1209. Preferably, the thermal release tape 120 is transparent or translucent so that the physical carrier mark 106 is still visible or detectable. In a preferred embodiment, the thermal release tape 120 is transparent under a specific light with a wavelength of 600 nanometers (nm). The thermal release tape 120 may have a thickness that matches the thickness of the semiconductor die. For example, when the thickness of the semiconductor die is about 0.35 millimeters (mm), the thickness of the thermal release tape 120 is about 0.1 millimeters (mm).

[0060] Then, the semiconductor dies will be bonded at their respective positions on the compensation mark carrier 108. In order to perform the bonding accurately, the semiconductor dies will be aligned at their respective positions before being bonded to the compensation mark carrier 108. Figure 9aA cross-sectional view of aligning an active die 200 to a compensation mark carrier 108 is shown for precisely bonding the active die 200 to its compensation bonding unit 130. The active die 200 performs an active electronic function in a semiconductor package. In one embodiment, the active die 200 has a silicon wafer 202, a protective layer 204 applied on an active surface 208 of the silicon wafer 202, and a filled through hole 206 formed in the protective layer 204 for electrically leading a die pad 209 from the active surface 208. The filled through hole 206 can be formed by filling a conductive material into a pre-through hole 207 in the protective layer 204. Alternatively, in this step, the filled through hole 206 may not be formed first, so that the die pad 209 can be exposed from the pre-through hole 207. When exposed from the protective layer 204, the filled vias 206 or the die pads 209 can be used as special features for identifying the active die 200 when aligning the active die 200 to the compensation mark carrier 108. The vision device 300 can be used to identify the exposed filled vias 206 of the active die 200 and the physical carrier marks 106 on the compensation mark carrier 108 to determine the relative position and orientation of the active die 200 with respect to the compensation mark carrier 108. Preferably, the identification of the active die 200 and the compensation mark carrier 108 is performed simultaneously so that the active die 200 can be bonded more accurately at its bonding position within the compensation bonding unit 130.

[0061] In one embodiment, the vision device 300 has an upward camera assembly 310 and a downward camera assembly 320 for simultaneously identifying the exposed filled vias 206 (or the die pads 209 exposed by the pre-vias 207) and the physical carrier marks 106, respectively. During identification, the vision device 300 is inserted between the active die 200 and the compensation mark carrier 108. Once aligned, the vision device 300 is withdrawn; the active die 200 is then vertically lowered toward the compensation mark carrier 108 and finally bonded to the thermal release tape 120 and the front surface 102 of the compensation mark carrier 108. In one embodiment, the upward camera assembly 310 and the downward camera assembly 320 are configured in a vertical coaxial configuration to avoid any alignment errors that may be caused by the vision device 300 itself. The alignment beam 304 is emitted from a single light source 302 and then split into an upward beam 306 and a downward beam 308, entering the upward camera assembly 310 and the downward camera assembly 320, respectively. In this way, the upward camera assembly 310 and the downward camera assembly 320 can simultaneously identify the active die 200 and the corresponding compensation bonding unit 130 on the compensation mark carrier 108. The upward camera assembly 310 and the downward camera assembly 320 can have high-resolution co-linear camera units for accurately determining the positions of the active die 200 and the compensation bonding unit 130, respectively.

[0062] In another embodiment, the visual device 300 employs a side-by-side configuration of the upward-looking camera assembly 310 and the downward-looking camera assembly 320 . Figure 9b 3 shows a cross-sectional view of the visual device 300 in the side-by-side configuration. The upward camera assembly 310 and the downward camera assembly 320 respectively have a first light source 312 for emitting a first alignment light 314 and a second light source 322 for emitting a second alignment light 324. Since the first light source 312 and the second light source 322 are independent of each other, the first alignment light 314 and the second alignment light 324 are also different from each other. The first alignment light 314 and the second alignment light 324 are controlled to reach the prism 330 and then reflected upward and downward, respectively. Therefore, the upward camera assembly 310 and the downward camera assembly 320 in the side-by-side configuration can also simultaneously identify the active die 200 and its corresponding compensation bonding unit 130 on the compensation mark carrier 108, respectively. Compared with the vertical coaxial configuration that can only emit the alignment beam 304, the side-by-side configuration can independently emit the first alignment light 314 and the second alignment light 324, which can be more suitable for their respective purposes. For example, the first alignment light 314 can be specifically selected based on the conductive material filled in the through hole 206 (or the die pad 209); and the second alignment light 324 can be selected to have a specific wavelength (for example, 600 nanometers (nm)) to penetrate the thermal release tape 120 to detect the physical carrier mark 106 covered by the thermal release tape 120.

[0063] Figures 10a to 10c A method of aligning the active die 200 with the compensation bonding unit 130 on the compensation flag carrier 108 is shown. Fig.10aA top view of active surface 208 of active die 200 is shown. First, four filled vias 2061-2064 (i.e., first filled via 2061, second filled via 2062, third filled via 2063, and fourth filled via 2064) or four pre-vias 2071-2074 (i.e., first pre-via 2071, second filled via 2072, third pre-via 2073, and fourth pre-via 2074) are identified at four corners of active die 200. Then, a first diagonal virtual line 2082 is drawn between the first filling via 2061 (or the first pre-via 2071) at the upper left corner and the fourth filling via 2064 (or the fourth pre-via 2074) at the lower right corner; and a second diagonal virtual line 2084 is drawn between the second filling via 2062 (or the second pre-via 2072) at the upper right corner and the third filling via 2063 (or the third pre-via 2073) at the lower left corner. A virtual die center 212 is determined at the intersection of the first diagonal virtual line 2082 and the second diagonal virtual line 2084. Then, a first virtual die reference point 214 and a second virtual die reference point 218 are determined by moving the first die distance 216 and the second die distance 220 away from the virtual die center 212. The first and second virtual die reference points 214 and 218 are arbitrarily determined, and their distances from the virtual die center 212 are the first and second die distances 216 and 220. For example, the first virtual die reference point 214 and the second virtual die reference point 218 may be obtained from Fig.10a The position shown is rotated 90 degrees clockwise or counterclockwise. Preferably, the first virtual die reference point 214 and the second virtual die reference point 218 are opposite to each other at the same distance from the virtual die center 212, that is, the first die distance 216 and the second die distance 220 are equal. It should be understood that the first and second diagonal virtual lines 2082, 2084 can also be drawn between other filled vias 206 (or other pre-vias 207) to determine the virtual die center 212, and further determine the first and second virtual die reference points 214, 218.

[0064] Fig.10bA top view of the compensation bonding unit 130 on the compensation mark carrier 108 is shown. First, four physical carrier marks 1062-1068 are identified at the four corners of the compensation bonding unit 130; then, a first diagonal virtual line 1071 is drawn between the first physical carrier mark 1062 at the upper left corner and the fourth physical carrier mark 1068 at the lower right corner, and a second diagonal virtual line 1072 is drawn between the second physical carrier mark 1064 at the upper right corner and the third physical carrier mark 1066 at the lower left corner. The intersection of the first diagonal virtual line 1071 and the second diagonal virtual line 1072 is determined as the virtual carrier center 132. Finally, the first virtual carrier reference point 134 and the second virtual carrier reference point 138 are determined by moving the first carrier distance 136 and the second carrier distance 140 away from the virtual carrier center 132. It should be understood that the first virtual carrier reference point 134 and the second virtual carrier reference point 138 are determined based on the first virtual die reference point 214 and the second virtual die reference point 218 so as to accurately align the active die 200 to its compensation bonding unit 130. It should also be understood that other methods may be used to draw the first and second diagonal virtual lines 1071, 1072, as long as the method is consistent with the method of drawing the first and second diagonal virtual lines 2082, 2084 for the active die 200.

[0065] Then, the active die 200 and its compensation bonding unit 130 are aligned by aligning the first virtual die reference point 214 and the second virtual die reference point 218 with the first virtual carrier reference point 134 and the second virtual carrier reference point 138, respectively. The active die 200 is bonded in a face-down manner, that is, the active surface 208 will contact the front surface 102 of the compensation mark carrier 108. Fig.10c A top view of an active die 200 bonded to a compensation mark carrier 108 is shown. The active die 200 is precisely located at its bonding position within the compensation bonding unit 130; and the back surface 210 of the active die 200 faces away from the compensation mark carrier 108. Depending on the size of the active die 200, the four physical carrier marks 1062-1068 may be exposed or covered by the active die 200. Preferably, the four physical carrier marks 1062-1068 are exposed for checking the position of the active die 200 on the compensation mark carrier 108 after bonding.

[0066] Fig.11a and 11bA cross-sectional view and a top view are respectively shown of an active die 200 and a reference die 230 bonded to a compensation tag carrier 108. The reference die 230 may be different from the active die 200 so as to be more easily detected by the vision device 300. However, it should be understood that one of the plurality of active dies 200 may also be used as the reference die 230. After precise alignment as described above, the active die 200 is bonded to its respective bonding location 160 on the compensation tag carrier 108. Fig.11a and Fig.11b A compensation gap 159 is shown between two adjacent active dies 200 bonded onto the compensation flag carrier 108 prior to compression molding.

[0067] In the case of expansion, the compensation gap 159 between the bonded active dies 200 is smaller than the original gap 158 before compression molding. However, after compression molding, the compensation gap 159 will increase and return to the original gap 158. As a result, more active dies 200 can be bonded to the compensation mark carrier 108 for compression molding and subsequent processes, thereby achieving higher production efficiency. In the case of shrinkage, the compensation gap 159 between the bonded active dies 200 is larger than the original gap 158 before compression molding. However, after compression molding, the compensation gap 159 will shrink and return to the original gap 158. If the original gap 158 is not compensated, the shrinkage during the compression molding process will significantly reduce the original gap 158, making the active dies 200 so densely distributed that the active dies 200 will inevitably be damaged during the subsequent cutting process. By means of compensation, after compression molding, the compensation gap 159 will return to the original gap 158, which will facilitate the subsequent cutting process.

[0068] In short, the original gap 158 can be compensated to the compensation gap 159 in the computing device 110, that is, the original gap 158 is increased in the case of shrinkage or reduced in the case of expansion, so that the compensation gap 159 is restored to the original design of the semiconductor package in the original design file. As described above, the compensation of the original gap 158 is performed by using the compensation factor 115 in the computing device 110 to transform the original virtual carrier mark 112 and the original virtual distance 114 into the compensation virtual carrier mark 116 and the compensation virtual distance 118 accordingly. Then, based on the compensation virtual carrier mark 116, the compensation projection mark 105 is generated through the above projection to form the physical carrier mark 106. In this way, when the active die 200 is bonded to the compensation mark carrier 108, the original gap 158 is compensated to the compensation gap 159 to offset the expansion or contraction generated during compression molding.

[0069] Fig.12aand Figure 12b Step S23 of the compensation method S20 is shown, that is, compression molding is performed to form a molded panel 242. The active die 200 and the reference die 230 are encapsulated in the mold layer 240. The compression molding is performed using a molding material under high temperature (e.g., about 140° C.) and high pressure (e.g., about 6 megapascals (MPa)). The compensation mark carrier 108 may expand during the compression molding, but the expansion along the compensation mark carrier 108 is uniform or linear. Therefore, the compensation factor 115 determined using the simulation diagram 124 includes the effect of the expansion of the compensation mark carrier 108. At the same time, the compensation mark carrier 108 can be made of a material with a very low coefficient of thermal expansion (CTE) to minimize the expansion generated during compression molding. In one embodiment, the compensation mark carrier 108 is made of alloy 46, and its CTE is in the range of 7 to 11 ppm / ° C., preferably, its coefficient of thermal expansion (CTE) is about 7.8 ppm / ° C. In another preferred embodiment, the molding material has a coefficient of thermal expansion (CTE) close to that of the compensating mark carrier 108, so that the expansion of the compensating mark carrier 108 relative to the molding layer 240 is minimized. For example, the molding material can be G730, which has a coefficient of thermal expansion (CTE) of approximately 11 ppm / °C, so that when the molding layer 240 is cooled from the molding temperature to room temperature, it will shrink less than 0.06%.

[0070] Fig.12a A cross-sectional view of a molded panel 242 is shown, wherein the compensation gap 159 is restored to the original gap 158 due to various factors during the compression molding, such as thermal-mechanical effects and mold compound fluid flow effects. Figure 12b A top view of the same active die 200 is shown shifted from the bonding position 160 (indicated by the dashed rectangle) to the molding position 162. As a result, after the compression molding, the distance between adjacent active dies 200 in the molding panel 242 is restored to the original gap 158. Optionally, the molding panel 242 can be ground using a grinding wheel 258 to remove the top of the molding layer 240, thereby reducing the thickness of the molding panel 242, and also eliminating the internal stress generated during the compression molding process, while also making the back side 246 of the molding panel 242 flatter for subsequent processing. The back surface 210 of the active die 200 can be exposed from the back side 246 of the molding panel 242. The molding panel 242 also has a front side 244, which includes the active surface 208 of the active die 200 embedded in the molding panel 242.

[0071] Fig.13Step S24 of the compensation method S20, i.e., the release process, is shown. Since the thermal release tape 120 loses its adhesiveness at high temperatures (e.g., about 200° C.), the molded panel 242 will be detached from the compensation mark carrier 108. After the release, the front side 244 of the molded panel 242 including the active surface 208 of the active die 200 will be exposed from the thermal release tape 120 and the compensation mark carrier 108.

[0072] Then, if Fig.14 As shown, the molded panel 242 is transferred and placed on another thermal release tape 121 and a carrier 250 in a flipped manner, that is, the back side 246 of the molded panel 242 is in contact with the thermal release tape 121 and the carrier 250. The front side 244 faces away from the thermal release tape 121 and the carrier 250, so that the front side 244 including the active surface 208 of the active die 200 is exposed. Similar to the thermal release tape 120, the thermal release tape 121 is adhered to the carrier 250 on the one hand, and the molded panel 242 is also adhered on the other hand. Therefore, the thermal release tape 121 can have a similar structure to the thermal release tape 120; at a high temperature (for example, about 200°C), the molded panel 242 will be detached from the thermal release tape 121 and the carrier 250. The carrier 250 also has a relatively flat front surface 252, so that it can be used in conjunction with the back side 246 of the molded panel 242, because as shown in FIG. Fig.12a As shown, back side 246 is ground flat. Carrier plate 250 may be made of the same material as blank carrier 100 (or compensating marking carrier 108), such as Alloy 46.

[0073] As described above, the compensation can usually be applied before the compression molding, so that the original gap 158 is restored after the compression molding. However, during the bonding process and / or compression molding, there may be small displacements and / or misalignments in orientation compared to the original design file. Therefore, a die location check is optionally performed on the front side 244 of the mold panel 242 to determine the true position of the active die 200 and the reference die 230 in the mold panel 242. Fig.15 As shown, the die position check can be performed by detecting special features (e.g., pre-via 207 or filled via 206) of the active die 200 and the reference die 230. The die position check can be performed by using the top-view camera assembly 320 of the vision device 300. Alternatively, the die position check can be performed by an independent camera, or by other similar devices suitable for detecting special features of the active die 200 and the reference die 230.

[0074] Fig.16aA top view of a die position inspection result is shown. Therein, the active die 200 and the reference die 230 in the mold panel 242 have only translational misalignment, but no orientation misalignment. The reference die 230 has reference features 232 at the four corners, so the reference center 234 of the reference die 230 can be further determined. Then, the reference center 234 can be used as the origin (0, 0) of the Cartesian coordinate system of the mold panel 242 to determine the position of the active die 200 in the mold panel 242. In the absence of orientation misalignment, the position of the active die 200 in the coordinate system can be represented by the coordinates (x, y) of its respective virtual die center 212. As described above, when performing a die position check, the die pad 209 exposed from the filled through holes 2061-2064 or the pre-through holes 2071-2074 can be first identified, and then the first diagonal virtual line 2082 and the second diagonal virtual line 2084 are drawn. Finally, the intersection of the first diagonal virtual line 2082 and the second diagonal virtual line 2084 is the virtual die center 212.

[0075] Fig.16b A top view of another die position inspection result is shown, wherein the active die 200 and the reference die 230 in the mold panel 242 have an orientation misalignment. Similarly, the reference center 234 can be used as the origin (0, 0) of the Cartesian coordinate system of the mold panel 242 to determine the orientation misalignment. However, in addition to the virtual die center 212, a first virtual die reference point 214 and a second virtual die reference point 218 can also be used to represent the position of the active die 200 in the Cartesian coordinate system. As described above. The first and second virtual die reference points 214, 218 can be determined by offsetting the first and second die distances 216, 220 from the virtual die center 212, respectively. A virtual orientation line 2086 (such as 2086) can be drawn by connecting the first virtual die reference point 214 and the second virtual die reference point 218. Fig.16b 2806); then determine the angle α between the Y axis of the Cartesian coordinate system and the virtual orientation line 2806. The orientation misalignment of the active die 200 can be measured by the angle α. If there is no orientation misalignment, the angle α is zero. It should be understood that the angle β between the X axis of the Cartesian coordinate system and the virtual orientation line 2806 can also represent the orientation misalignment.

[0076] Then, the die position check result may be input into the computing device 110. Currently, due to the presence of translation misalignment and / or orientation misalignment, the original design file stored in the storage device 1102 may not match the die position check result. The computing device 110 has a matching algorithm 1108 for comparing and / or matching the original design file with the die position check result, thereby updating the position and orientation of the active die 200 in the mold panel 242 and storing it in the storage device 1102. Then, the computing device 110 generates and outputs a circuit file based on the updated original design file (i.e., the updated design file) to perform step S25 of the compensation method S20.

[0077] Fig.17a and 17b A statistical graph 260 of die misalignment before (generated during the bonding process) and after (generated during the compression molding process) compression molding from the front side 244 of the molding panel 242 is shown. The die position check as described above can be performed on the active surface 208 of the active die 200 to identify translational and / or orientational misalignment of the die before compression molding. Fig.11a The top-view camera assembly 320 of the vision device 300 can be used to detect the misalignment.

[0078] Fig.17a and 17b The black dots shown in the dashed circles indicate that the misalignment of the active die 200 is greater than the position misalignment tolerance, the orientation misalignment tolerance, or both. Fig.17a In the example, a small number of black dots are scattered in the first area 262 and the second area 263. Meanwhile, few black dots can be observed in other areas. Fig.17b In the figure, a larger number of black spots can be observed. The black spots are concentrated in the third area 264, the fourth area 266 and the fifth area 268. However, the black spots are rarely observed in the first area 262 and the second area 263. Therefore, the statistical data before and after compression molding show that the die offset generated in compression molding can eliminate the misalignment of the active die 200 generated in the bonding process; but in other areas, the die offset in compression molding will cause more active dies 200 to be misaligned. Therefore, the present application aims to correct the die offset generated during compression molding, because the die offset is the main reason for the translational misalignment and / or orientation misalignment of the active die 200.

[0079] Therefore, first, the misalignment of the translation and / or orientation of the semiconductor die from the die position inspection process is compared with the misalignment tolerance by the matching algorithm 1108 of the computing device 110, thereby updating the original design file (i.e., generating the updated design file). Then, the semiconductor die whose translation and / or orientation misalignment is greater than the misalignment tolerance are marked in the statistical graph 260, for example, with black dots. Finally, the translation and / or orientation of the marked semiconductor die in the updated design file are adjusted. At the same time, the semiconductor die whose translation and / or orientation misalignment is less than the misalignment tolerance is not marked in the statistical graph 260. Accordingly, the position and / or orientation of the unmarked semiconductor die will remain unchanged in the updated design file.

[0080] Figures 18a to 18c A schematic diagram showing step S25 of the compensation method S20 is shown. Fig.18a A cross-sectional view of molded panel 242 and circuit layer 270 formed on front side 244 thereof is shown. Fig.18b An enlarged cross-sectional view of a circuit layer 270 formed on the active die 200 is shown. The circuit layer 270 is coupled to a filled via 206 in the protection layer 204 for leading out to a die pad 209 on the silicon die 202. Fig.18cAn enlarged cross-sectional view of a circuit layer 270' formed on a reference die 230 is shown. The circuit layer 270' has a different structure from the circuit layer 270, so that the reference die 230 can be easily distinguished from the active die 200. The circuit layer 270 of the active die 200 may have a redistribution layer 272 coupled to the filled via 206, which may extend beyond the active die outline 430 of the active die 200 (i.e., a fan-out circuit layer); and a plurality of conductive studs 274 formed on the redistribution layer 272 and coupled to the redistribution layer 272. Therefore, the circuit file may include a redistribution layer file for forming the redistribution layer 272 coupled to the die pad 209, and a stud file for forming the conductive studs 274. A die position check may be performed to update the redistribution layer file associated with the circuit layer 270, 270'; and update the stud file associated with the redistribution layer 272. The circuit layer 270' of the reference die 230 may be confined within the reference die outline 440 (i.e., a fan-in circuit layer). Alternatively, if one of the plurality of active die 200 is used as the reference die 230, the circuit layer 270' of the reference die 230 may be the same as the circuit layer 270 of the active die 200. As described above, the circuit layer 270 of the active die 200 and the circuit layer 270' of the reference die 230 are formed precisely in accordance with the circuit file, which is consistent with the updated design file. If the filled via 206 is not formed before this step, the pre-via 207 in the protective layer 204 should be filled with a conductive material before step S25 to form the filled via 206.

[0081] Fig.19 A schematic diagram of step S26 of compensation method S20 is shown. Dielectric layer 280 is formed of a dielectric material and is used to encapsulate circuit layers 270, 270' so as to protect circuit layers 270, 270' from moisture and other environmental hazards. Dielectric layer 280 can be formed by any suitable method, such as by applying a film of dielectric material to circuit layers 270, 270'. Preferably, dielectric layer 280 is formed by compression molding of the same molding material as molding layer 240, so that molding layer 240 and dielectric layer 280 can have better compatibility at their interface 282, thereby making the semiconductor package more stable in structure.

[0082] Fig. 20 A schematic diagram of step S27 of compensation method S20 is shown. The top of dielectric layer 280 may be removed by grinding wheel 258 to expose circuit layers 270, 270'. Therefore, active die 200 may be electrically connected to external devices through the exposed circuit layers 270, 270'.

[0083] Fig.21a Schematic diagram of step S28 of compensation method S20 is shown. An external connection layer 290 is formed on the dielectric layer 280 remaining after grinding. The external connection layer 290 may include a plurality of solder balls 292 coupled to the exposed circuit layer 270. The solder balls 292 are made of a conductive material such as copper (Cu) and are used to lead the active die 200 through the circuit layer 270. According to the circuit file, the computing device 110 first generates and exports an external connection file for forming the external connection layer 290; then the exported external connection file is transmitted to a stencil device to form the solder balls 292.

[0084] Fig.22a A schematic diagram of step S29 of the compensation method S20 is shown. The mold panel 242 having the circuit layer 270 and the solder balls 292 as the external connection layer 290 is divided into individual semiconductor packages. Fig.23 Four adjacent single chip modules 400 (ie, a first single chip module 402 , a second single chip module 404 , a third single chip module 406 , and a fourth single chip module 408 ) are shown in top view (left) and perspective view (right). The single chip modules 400 include only a single active die 200 . Fig.23 The package outline 410 of the single chip module 400 is shown, which shows the size of the semiconductor package. The external connection layer 290 of the single chip module 400 is formed according to the circuit layer 270, and the solder balls 292 are formed within the circuit outline 420. Since the circuit outline 420 extends outside the active die outline 430, Fig.23 The illustrated single chip module 400 is a fan-out semiconductor package. It should be understood that the single chip module 400 may also be a fan-in semiconductor package, where the circuit outline 420 is located within the active die outline 430.

[0085] Fig.23Also shown is a first package gap 4102 along the X-axis direction between the first package center 412 of the first single chip module 402 and the second package center 414 of the second single chip module 404, or between the third package center 416 of the third single chip module 406 and the fourth package center 418 of the fourth single chip module 408. Similarly, a second package gap 4104 along the Y-axis direction between the first package center 412 and the third package center 416, or between the second package center 414 and the fourth package center 418. In one embodiment, in the original design file, the first package gap 4102 and the second package gap 4104 are 1.835 and 3.035 millimeters (mm) in the X-axis direction and the Y-axis direction, respectively. The simulation diagram 124 shows that due to expansion during compression molding, the first package gap 4102 and the second package gap 4104 will increase by 0.060% and 0.056% to 1.8361 and 3.0367 millimeters (mm), respectively. In order to keep consistent with the provisions of the first package gap 4102 and the second package gap 4104 in the original design file, before compression molding, the first package gap 4102 and the second package gap 4104 need to be reduced by 0.060% and 0.056% in the X-axis direction and the Y-axis direction, respectively. The reduction of the first package gap 4102 and the second package gap 4104 can be performed by the compensation method S20 as described above, that is, before compression molding, the original gap 158 between the semiconductor dies is compensated to the compensation gap 159. Then, as the compensation gap 159 is restored to the original gap 158 during compression molding, the first package gap 4102 and the second package gap 4104 are also restored to the specifications specified in the original design file. Specifically, the simulation diagram 124 predictively calculates the compensation factor 115 for converting the original gap 158 into the compensation gap 159, so as to reduce the first package gap 4102 and the second package gap 4104 between the semiconductor packages of the single chip module in the X-axis direction and the Y-axis direction by 0.060% and 0.056%, respectively. Alternatively, the simulation algorithm 1106 of the computing device 110 may generate another simulation graph (not shown) similar to the simulation graph 124. Figure 4bThe simulation diagram 124 shown shows that the offset of the semiconductor die is different, and the other simulation diagram is performed for the offset of the semiconductor package of the single chip module 400. Since the virtual die center 212 is generally defined as the package center 412-418 of the semiconductor package of the single chip module 402-408, the compensation gap 159 between the active dies 200 can also be calculated according to the expansion or contraction of the first package gap 4102 and the second package gap 4104 of the single chip module 402-408. Therefore, when the compensation gap 159 is restored to the original gap 158 in the original design file by expansion or contraction during compression molding, the first package gap 4102 and the second package gap 4104 will also be restored to their values ​​specified in the original design file.

[0086] Replacement solder ball 292, Figure 21b It is shown that the external connection layer 290 may also include a surface finish layer 294 formed on the exposed circuit layer 270, which is used to provide a very flat surface for input / output (I / O) so as to be connected to external components such as a PCB. The surface finish layer 294 may be made of a single layer of metal such as tin or a single layer of metal composite such as nickel / gold. Alternatively, the surface finish layer 294 may also be made of multiple layers of metal or metal composite. In some embodiments, the surface finish layer 294 is made of electroless nickel immersion gold, which has a 2-layer metal surface treatment, wherein the first layer of nickel is plated on the exposed circuit layer 270 using a chemical reaction, and then a very thin layer of gold is plated on the nickel layer. In other embodiments, the surface treatment layer 294 may be made of electroless nickel electroless palladium immersion gold, which is formed by first depositing chemical nickel onto the exposed circuit layer 270, then chemically depositing palladium, and finally depositing immersion gold flash. The surface treatment layer 294 is compatible with the input / output (I / O) chemistry to improve the connection stability with external components (such as PCBs). The thickness of the surface treatment layer 294 can be in the range of 1 micron (μm) to 10 microns (μm), preferably in the range of 1 micron (μm) to 5 microns (μm), or more preferably in the range of 1 micron (μm) to 3 microns (μm).

[0087] Continue Figure 21b , Figure 22b As shown in Fig.22aThus, a semiconductor package similar to the single chip module 400 will be produced. Instead of solder balls 292, the similar single chip module 400 has a surface finish layer 294 for electrical connection to an external component such as a PCB.

[0088] Compared to semiconductor dies (e.g., active die 200 and reference die 230), compensation tag carrier 108 is usually larger in size, so it can accommodate hundreds or even thousands of semiconductor dies, thereby improving production efficiency. However, the larger the compensation tag carrier 108 is, the more likely the semiconductor dies accommodated thereon will produce the misalignment during the bonding process. Therefore, compensation tag carrier 108 can be divided into a plurality of blocks 170, each block 170 having its own reference die 230; and then active die 200 is bonded to the block 170. Fig.24 A schematic diagram of a compensation mark carrier 108 divided into nine blocks 170 is shown, and the blocks 170 may have the same or different sizes. Each block 170 has a reference die 230 that can serve as an origin (0,0) for more accurately determining the position of the active die 200 located in that particular block 170. The reference die 230 can be located at a block corner 172 of the block 170. Alternatively, the reference die 230 can also be located at a block center 174 of the block 170. Similarly, the block 170 can be further divided into a plurality of sub-blocks 180 (e.g., Fig.24 ); each sub-block 180 may have a reference die 230 as the origin (0, 0) for more accurately determining the position of the active die 200 located in the specific sub-block 180. The reference die 230 may be located at a sub-block corner 182 of the sub-block 180. Alternatively, the reference die 230 may also be located at a sub-block center 184 of the sub-block 180. The sub-blocks 180 may have the same or different sizes within their blocks 170. Similarly, the sub-blocks 180 may be further divided into a plurality of smaller units, each of which has a reference die 230 as the origin (0, 0) of the specific smaller unit. However, the more reference die 230 are placed on the compensation mark carrier 108, the fewer active die 200 can be accommodated thereon; and the lower the production efficiency of the compression molding and subsequent processes.

[0089] Fig.25a and 25b An example of a multi-chip module (MCM) 500 including two or more active dies 200 in a single semiconductor package is shown. Fig.25aAn example of a top view of a compensation bonding unit 130 is shown, with four physical carrier marks 106 at four corners on a compensation mark carrier 108. The compensation bonding unit 130 has three compensation bonding subunits 510, 520, 530 for accommodating three active dies 514, 524, 534, respectively. It should be understood that the compensation bonding unit 130 may also have any number of compensation bonding subunits (e.g., in addition to the three compensation bonding subunits 510, 520, 530, it may have two, four or more compensation bonding subunits), depending on the number of active dies 200. Multiple active dies 200 will be accommodated in the compensation bonding unit 130 to manufacture a multi-chip module (MCM) 500. Each compensation bonding subunit 510 , 520 , 530 also has its own physical carrier sub-mark 512 , 522 , 532 for determining the position of the active die 514 , 524 , 534 in the respective compensation bonding subunit 510 , 520 , 530 when the active die 514 , 524 , 534 is bonded inside the compensation bonding unit 130 located on the compensation mark carrier 108 . Fig.25b A top view of active dies 514, 524, 534 bonded to the compensation mark carrier 108 is shown. Therein, the active dies 514, 524, 534 cover their respective physical carrier sub-marks 512, 522, 532. However, it should be understood that the physical carrier sub-marks 512, 522, 532 may be exposed from the active dies 514, 524, 534.

[0090] like Fig.25b As shown, after being bonded to the compensation bonding unit 130, the active dies 514, 524, 534 on the compensation mark carrier 108 will undergo compression molding and subsequent processes as described above. During the die position check, one of the active dies 514, 524, 534 (e.g., the first active die 514) can be used as the origin (0, 0) of the coordinate system of the multi-chip module (MCM) 500. For example, the first die center 5142 of the first active die 514 can be used as the origin (0, 0) of the coordinate system. Then, the relative positions of other active dies (e.g., the second active die 524 and the third active die 534) within the multi-chip module (MCM) 500 can be determined relative to the origin (0, 0) of the coordinate system. The origin (0, 0) may be arbitrarily determined and may be located anywhere within the multi-chip module (MCM) 500, such as the second die center 5144 of the second active die 524, the third die center 5146 of the third active die 534, or the module center 5148 of the multi-chip module (MCM) 500, which may not fall within any active die 514, 524, 534 in the multi-chip module (MCM) 500. Fig.24In addition to the coordinate system of block 170 or sub-block 180 described in the above, whose origin (0,0) is located at reference die 230, a more accurate die position check can also be performed by using a coordinate system within multi-chip module (MCM) 500. Fig.26 As shown, after the segmentation, separate multi-chip modules (MCM) 500 are generated. The active dies 514, 524, and 534 may have different electronic functions; and they may also communicate internally to realize the electronic functions of the multi-chip module (MCM) 500 as a whole. For example, the active die 514 may be responsible for storing information, the active die 524 may be used to process information, and the active die 534 may first receive information from an external electronic device and then send the processed information to the external electronic device.

[0091] The present disclosure may be implemented in other specific forms without departing from the spirit or essential characteristics of the present disclosure. Therefore, the foregoing embodiments are considered to be illustrative in all respects and not intended to limit the present disclosure. Therefore, the scope of the present disclosure is described by the appended claims rather than the foregoing description, and all changes within the meaning and scope of the claims are included in the present disclosure. In this application, unless otherwise stated, the terms "comprises", "including" and their grammatical variants are intended to represent "open" or "comprising" language, such that they include the listed elements, but also allow for the inclusion of additional, non-explicitly recited elements.

Claims

1. A compensation mark carrier for compensating for die offset of a semiconductor die during compression molding, wherein: include: a blank carrier; as well as a plurality of physical carrier marks formed on the blank carrier, wherein the physical carrier mark is formed at the compensated projection mark, and the compensated projection mark is transformed from the original projection mark by applying a compensation factor in a computing device, The original projection mark is generated by projecting the original virtual carrier mark, and The original virtual carrier mark is derived from the original design file; The original projection mark and the compensation projection mark are used to determine the original gap and the compensation gap between two adjacent semiconductor dies, respectively; and The die shift caused by the compression molding is compensated by changing an original gap to a compensation gap when bonding the semiconductor die to the compensation marking carrier.

2. The compensation mark carrier according to claim 1, wherein: The calculation device has a simulation algorithm and can calculate the compensation factor through a simulation diagram.

3. The compensation mark carrier according to claim 1, wherein: Also includes: The compensation mark carrier is divided into a plurality of compensation bonding units by the compensation projection marks, wherein each compensation bonding unit is configured to accommodate at least one semiconductor die.

4. The compensation mark carrier according to claim 3, wherein The compensation bonding unit is divided into a plurality of compensation bonding sub-units by means of a physical carrier sub-mark in the compensation bonding unit; and The semiconductor dies are respectively bonded to the compensation bonding sub-units within the compensation bonding unit to form a multi-chip module (MCM).

5. The compensation mark carrier according to claim 1, wherein: The compensation mark carrier includes a plurality of blocks, each block having at least one reference die as the origin of a coordinate system of the block for more accurately determining the position of the semiconductor die within the block.

6. The compensation mark carrier according to claim 1, wherein: The physical carrier mark includes: A groove is formed at the position of the compensation projection mark on the front surface of the compensation mark carrier, wherein the groove is a cylindrical groove or a truncated groove.

7. A molded panel for manufacturing a panel-level semiconductor package, wherein: include: a plurality of semiconductor die on a compensating marking carrier having physical carrier markings, wherein the physical carrier mark is formed at the compensated projection mark, and the compensated projection mark is transformed from the original projection mark by applying a compensation factor in a computing device, The original projection mark is generated by projecting the original virtual carrier mark, and The original virtual carrier mark is derived from the original design file; a molding layer formed by compression molding, for encapsulating the semiconductor die therein; The original projection mark and the compensation projection mark are used to determine the original gap and the compensation gap between two adjacent semiconductor dies, respectively; and The die shift caused by the compression molding is compensated by changing an original gap to a compensation gap when bonding the semiconductor die to the compensation marking carrier.

8. The molded panel according to claim 7, wherein: The semiconductor die may be checked for misalignment in the molding panel by a die position check DLC.

9. The molded panel according to claim 8, wherein: Also includes A circuit layer is formed on the mold panel according to the misalignment condition, and is used to electrically lead out the semiconductor bare chip.

10. The molded panel according to claim 9, wherein: The circuit layer includes a redistribution layer coupled to the semiconductor die, and conductive studs coupled to the redistribution layer.

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