Pixel driving circuit, driving substrate and display device

Abstract

The utility model provides a pixel driving circuit, a driving substrate and display equipment. The circuit comprises a reset unit which comprises a first N-type transistor and a second N-type transistor; a drain electrode of the first N-type transistor and a source electrode of the second N-type transistor are connected to a first connection point, and the first N-type transistor and the second N-type transistor are configured to be opened in a reset stage of a refresh frame, so that a reset voltage is accessed to the source electrode of the first N-type transistor from the outside of the pixel driving circuit, and the voltage of the first connection point is reset according to the reset voltage; and a second transistor configured to hold a source-drain voltage of the first N-type transistor when holding a frame.

Description

Technical Field

[0001] Embodiments of the present application relate to the technical field of pixel circuits, and in particular, to a pixel driving circuit, a driving substrate, and a display device. Background Art

[0002] In the relevant pixel driving circuit, since the PMOS (P-type transistor) therein has leakage behavior, the voltage of the holding frame is inconsistent with the voltage of the refresh frame, and thus the brightness is unstable at VRR (variable refresh rate).

[0003] Based on this, a solution is needed to solve the brightness instability caused by PMOS leakage. Utility Model Content

[0004] In view of this, the purpose of the present application is to provide a pixel driving circuit, a driving substrate and a display device.

[0005] Based on the above purpose, the present application provides a pixel driving circuit, including:

[0006] A reset unit, the reset unit comprising a first N-type transistor and a second N-type transistor;

[0007] The drain of the first N-type transistor and the source of the second N-type transistor are connected to a first connection point, and are configured to remain turned on during a reset phase of a refresh frame, so that the source of the first N-type transistor is connected to a reset voltage from outside the pixel driving circuit, and the voltage of the first connection point is reset according to the reset voltage; and

[0008] The device is configured to maintain the source-drain voltage of the first N-type transistor when maintaining the frame.

[0009] Further, the reset unit further includes a first P-type transistor, a drain of the first P-type transistor and the first N-type transistor and the second N-type transistor are connected to the first connection point, and a gate of the first P-type transistor and the drain of the second N-type transistor are connected to a second connection point;

[0010] The second N-type transistor is configured to remain turned on during a reset phase of a refresh frame, and to apply the voltage of the first connection point to the second connection point to reset the gate-source voltage of the first P-type transistor and turn on the first P-type transistor;

[0011] The first P-type transistor is configured to reset a drain voltage of the first P-type transistor according to a voltage of the first connection point during a reset phase of a refresh frame.

[0012] Furthermore, the pixel driving circuit further includes:

[0013] a writing unit connected to the source of the first P-type transistor at a third connection point;

[0014] The writing unit is configured to, during a writing phase of a refresh frame, access a writing voltage from outside the pixel driving circuit and apply the writing voltage to the third connection point;

[0015] The second N-type transistor is also configured to remain turned on during the write phase of the refresh frame and form a diode connection with the first P-type transistor that remains turned on, applying the write voltage of the third connection point to the second connection point to adjust the voltage of the second connection point.

[0016] Further, the writing unit includes a second P-type transistor connected to the first P-type transistor at the third connection point;

[0017] The second P-type transistor is configured to remain turned on during the writing phase of the refresh frame, to connect a writing voltage from outside the pixel driving circuit, and to apply the writing voltage to the source of the first P-type transistor.

[0018] Furthermore, the pixel driving circuit further comprises: a reset unit connected to the writing unit at the third connection point, and a driving unit connected to the reset unit at a fourth connection point;

[0019] The reset unit is configured to, in a reset phase, connect a first reset voltage and a second reset voltage from outside the pixel driving circuit, apply the first reset voltage to the third connection point to reset the voltages of the first connection point and the third connection point according to the reset voltage, and apply the second reset voltage to the fourth connection point;

[0020] The driving unit is configured to, during a driving phase, access a source voltage from outside the pixel driving circuit and apply the source voltage to the third connection point to adjust the gate-source voltage of the first P-type transistor and drive the pixel based on the adjusted gate-source voltage of the first P-type transistor.

[0021] Furthermore, the driving unit comprises:

[0022] a third P-type transistor, wherein the drain of the third P-type transistor is connected to the third connection point, and is configured such that, in a driving stage, the source of the third P-type transistor is connected to the source voltage from outside the pixel driving circuit, and the gate of the third P-type transistor is connected to the first driving signal from outside the pixel driving circuit, so as to turn on the third P-type transistor and apply the source voltage to the third connection point;

[0023] The first P-type transistor is further configured to apply the source voltage of the third connection point to the first connection point;

[0024] a fourth P-type transistor, wherein the source of the fourth P-type transistor is connected to the first connection point, the drain of the fourth P-type transistor is connected to the fourth connection point, and is configured such that, in a driving stage, the gate of the fourth P-type transistor is connected to a second driving signal from outside the pixel driving circuit to turn on the fourth P-type transistor and apply the source voltage of the first connection point to the fourth connection point;

[0025] and a light emitting diode having an anode connected to the fourth connection point and configured to light up in response to application of the source voltage.

[0026] Furthermore, the reset unit includes:

[0027] a fifth P-type transistor, the drain of which is connected to the third connection point, and configured to remain turned on during a reset phase of a refresh frame, access a first reset voltage from outside the pixel driving circuit, and apply the reset voltage to the third connection point, and remain turned on during a reset phase of a hold frame, access a first reset voltage from outside the pixel driving circuit, and apply the reset voltage to the third connection point;

[0028] A sixth P-type transistor, wherein the drain of the sixth P-type transistor is connected to the fourth connection point, and is configured to remain turned on during the reset phase of the refresh frame, connect a second reset voltage from outside the pixel drive circuit, apply the reset voltage to the fourth connection point, and remain turned on during the reset phase of the hold frame, connect a second reset voltage from outside the pixel drive circuit, and apply the reset voltage to the fourth connection point.

[0029] Furthermore, the pixel driving circuit further includes:

[0030] The first storage capacitor has one end connected to the source voltage and the other end connected to the second connection point, and is configured to be charged with the source voltage before the refresh frame and discharged to the second connection point.

[0031] Furthermore, the pixel driving circuit further includes:

[0032] A second storage capacitor has one end connected to the source voltage and the other end connected to the third connection point, and is configured to be charged with the source voltage before the refresh frame and discharged to the third connection point, so that the second storage capacitor and the first storage capacitor can jointly charge the first P-type transistor in advance.

[0033] Furthermore, the pixel driving circuit further includes:

[0034] A third storage capacitor has one end connected to the first reset voltage and the other end connected to the third connection point, and is configured to be charged with the first reset voltage and discharged to the third connection point in a refresh frame and a hold frame to maintain the voltage of the third connection point consistent in the refresh frame and the hold frame.

[0035] Furthermore, the pixel driving circuit further includes:

[0036] A fourth storage capacitor has one end connected to the first reset voltage and the other end connected to the first connection point, and is configured to be charged with the first reset voltage and discharged to the first connection point in a refresh frame and a hold frame to maintain the voltage of the first connection point consistent in the refresh frame and the hold frame.

[0037] Based on the same concept, the present application also provides a driving substrate, which includes the pixel driving circuit as described in any of the above items.

[0038] Based on the same concept, the present application also provides a display device, which includes the driving substrate as described above.

[0039] From the above, it can be seen that the pixel driving circuit, driving substrate and display device provided by the present application are based on setting the MOS tube (field effect transistor) connected to the reset voltage as a first N-type transistor, and connecting it to the second N-type transistor at the first connection point, so that when the first N-type transistor is connected to the reset voltage, the voltage of the first connection point connecting the first N-type transistor and the second N-type transistor is reset, and the leakage of the P-type transistor is avoided when the frame is maintained, so that the voltage of the N1 point is maintained consistent with the refresh frame in the maintenance frame, thereby avoiding the problem of unstable brightness during VRR. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 A first circuit diagram of a pixel driving circuit according to an embodiment of the present application;

[0042] Figure 2 is a timing diagram of a pixel driving circuit according to an embodiment of the present application;

[0043] Figure 3 A second circuit diagram of the pixel driving circuit according to an embodiment of the present application;

[0044] Figure 4 is a third circuit diagram of the pixel driving circuit according to an embodiment of the present application;

[0045] Figure 5 is a fourth circuit diagram of the pixel driving circuit according to an embodiment of the present application;

[0046] Figure 6 is a fifth circuit diagram of the pixel driving circuit according to an embodiment of the present application;

[0047] Figure 7 This is a sixth circuit diagram of the pixel driving circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0049] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0050] As described in the background technology section, the related pixel driving circuits are still difficult to meet the needs of actual use.

[0051] In the process of implementing the present application, the applicant discovered that the main problem with the relevant pixel driving circuit is that in the relevant pixel driving circuit, due to the leakage behavior of the PMOS (P-type transistor) therein, the voltage of the maintaining frame is inconsistent with the voltage of the refreshing frame, and thus the brightness is unstable at VRR (variable refresh rate).

[0052] Based on this, one or more embodiments of the present application provide a pixel driving circuit based on an N-type transistor and an increased storage capacitor to maintain the voltage when holding a frame, thereby maintaining the stability of the VRR.

[0053] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0054] refer to Figure 1 , a pixel driving circuit 1 according to an embodiment of the present application comprises:

[0055] A reset unit 101, wherein the reset unit 101 includes a first N-type transistor and a second N-type transistor;

[0056] The drain of the first N-type transistor and the source of the second N-type transistor are connected to a first connection point, and are configured to remain turned on during a reset phase of a refresh frame, so that the source of the first N-type transistor is connected to a reset voltage from outside the pixel driving circuit, and the voltage of the first connection point is reset according to the reset voltage; and

[0057] The device is configured to maintain the source-drain voltage of the first N-type transistor when maintaining the frame.

[0058] In this embodiment, the pixel driving circuit 1 includes a reset unit 101, and the reset unit 101 is used to access an external reset voltage and perform a reset phase in a refresh frame.

[0059] in, Figure 2 FIG. 1 shows the working sequence of the pixel driving circuit 1. It can be seen that when the pixel driving circuit 1 is working, each cycle includes a refresh frame and a hold frame. The refresh frame is Figure 2 In the stages 1 to 5, when refreshing the frame, the Rest (reset) stage is performed in sequence, that is, Figure 2 Phases 1 and 2 in the write phase, i.e. Figure 2 The 3 stages in the reset phase, i.e. Figure 2 The 4 stages in the process; the driving stage, i.e. Figure 2 5 stages in; keep the frame Figure 2 From the 6th to the 10th stage, when the frame is held, the 9th stage is the reset stage and the 10th stage is the drive stage.

[0060] In this embodiment, if Figure 1 As shown, the reset unit 101 includes a first N-type transistor T1 and a second N-type transistor T2.

[0061] It can be seen that the gate of T1 is connected to the first pulse signal NSTV_n-1, the source thereof is connected to the reset voltage Vinit1, and the drain thereof is connected to T2 at the first connection point N1.

[0062] Furthermore, the source of T2 and the drain of T1 are connected to N1, the gate thereof is connected to the second pulse signal NSTV_n, and the drain thereof is connected to Figure 2 The second connection point N2 in.

[0063] Based on this, when entering the reset phase of the refresh frame, such as Figure 2As shown, the NSTV_n-1 signal is input to T1 during the 1-2 phase to turn on T1 during the reset phase; the NSTV_n signal is input to T2 during the 2-phase to turn on T2 during the reset phase.

[0064] Further, based on the turned-on T1, the reset voltage is applied to N1 after it is connected; after T2 is turned on, the reset voltage is connected from N1 and then applied to N2.

[0065] Further, in Figure 2 When holding the frame, since both T1 and T2 are NMOS (N-type transistors), their leakage when holding the frame is much smaller than that of PMOS (P-type transistor). Therefore, the source-drain voltage between the source and drain of each of T1 and T2 can be kept stable.

[0066] It can be seen that the pixel driving circuit 1 in the embodiment of the present application is based on setting the MOS tube (field effect transistor) connected to the reset voltage in the reset unit 101 as a first N-type transistor, and connecting it to the second N-type transistor at the first connection point, so that when the first N-type transistor is connected to the reset voltage, the voltage of the first connection point connecting the first N-type transistor and the second N-type transistor is reset, and the leakage of the P-type transistor is avoided when the frame is maintained, so that the voltage of the N1 point is maintained consistent with the refresh frame in the maintenance frame, thereby avoiding the problem of unstable brightness during VRR.

[0067] In another embodiment of the present application, Figure 1 As shown, the reset unit 101 also includes a first P-type transistor T3.

[0068] In this embodiment, the gate of T3 is connected to N2 , and the drain is connected to N1 , that is, the gate of T3 is connected to T2 , and the drain is connected to T1 .

[0069] Based on this, in the reset phase of the refresh frame, since T2 is turned on, the reset voltage connected to it can be applied to the gate of T3 through N2 to turn on T3 and reset the gate-source voltage maintained on T3 in the previous frame.

[0070] Furthermore, after T3 is turned on, the voltage at point N1, that is, the drain voltage of T3, is reset.

[0071] It can be seen that in the embodiment of the present application, by setting the first P-type transistor T3 connected to T1 and T2, the gate-source voltage of T3 is reset by turning on T2 in the reset phase, and T3 is turned on. At the same time, the drain voltage of T3 is also reset by turning on T2 in the reset phase.

[0072] In another embodiment of the present application, the pixel driving circuit 1 further includes a writing unit 102 .

[0073] Among them, Figure 3 As shown, the writing unit 102 and the source of T1 are connected to N3 , and are connected to the writing voltage Vdata outside the pixel driving circuit 1 .

[0074] Based on this, after completing the reset phase, entering the write phase, the write unit 102 will access Vdata from outside the pixel driving circuit 1 and apply Vdata to N3, that is, the source of T3, wherein T3 remains turned on during the write phase.

[0075] Furthermore, if Figure 2 As shown, during the write phase of the refresh frame, the NSTV_n signal is still maintained, so T2 remains turned on during the write phase, and then T2 that remains turned on forms a diode connection with T3 that remains turned on, and Vdata is added to N2, thereby adjusting the voltage of N2.

[0076] It can be seen that this embodiment is based on the set write unit, and during the write phase of the refresh frame, the write voltage is connected, and the voltage of N3 is adjusted using the write voltage, and the voltage of N2 is adjusted by turning on T2 to reach Vdata+Vth.

[0077] In another embodiment of the present application, Figure 3 As shown, the writing unit 102 includes a second P-type transistor T4.

[0078] Among them, Figure 2 As shown, when writing a frame, the gate of T4 is connected to the third pulse signal GSTV and remains turned on during the writing phase. The source of T4 is connected to Vdata from the outside of the pixel driving circuit 1, and Vdata is applied to N3, that is, the source of T3, through the turned-on T4.

[0079] Furthermore, if the opening time of T4 is sufficient, the voltage of N2 can be adjusted to Vdata+Vth, where Vth represents a threshold voltage.

[0080] It can be seen that in this embodiment, the write voltage Vdata is connected based on T4 set in the write unit 102, and the write voltage is applied to T1 by connecting T4 to N3.

[0081] In another embodiment of the present application, Figure 4 As shown, the pixel driving circuit 1 further includes a reset unit 103 and a driving unit 104 .

[0082] Among them, a part of the reset unit 103 is connected to the write unit 102 at N3, and is connected to a part of the driving unit 104; another part of the driving unit 104 and another part of the reset unit 103 are connected to the fourth connection point N4, and are connected to the reset DNA element at N1.

[0083] Furthermore, if Figure 2 As shown, after completing the writing phase of the refresh frame, the refresh frame enters the reset phase, and the reset unit 103 is started in the reset phase, and the first reset voltage Vinit3 and the second reset voltage Vinit2 are connected from outside the pixel driving circuit 1.

[0084] Part of the reset unit 103 is connected to Vinit3, and applies Vinit3 to N3, and applies Vinit3 to N1 through T3 which is still in the on state, so as to reset the voltages of N1 and N2.

[0085] Furthermore, the reset unit 103 of another part is connected to Vinit2 and applies Vinit2 to N4 connected to the driving unit 104 .

[0086] Furthermore, if Figure 2 As shown, after completing the reset phase of the refresh frame, the drive phase of the refresh frame is entered, as shown in FIG. Figure 2 As shown, the driving unit 104 receives the driving signal ESTV in both the driving phases of the refresh frame and the hold frame. After entering the driving phase of the refresh frame, as shown in FIG. Figure 4 As shown, the driving unit 104 receives the source voltage ELVDD from outside the pixel driving circuit 1 and is started based on the received ESTV signal.

[0087] Based on this, the driving unit 104 applies the connected ELVDD to N3, so that the voltage at N3 is adjusted to ELVDD. At this time, the voltage at N2 is still Vdata+Vth, and it can be determined that the gate-source voltage of T3 is adjusted to VGS=Vdata+Vth-ELVDD, where VGS represents the gate-source voltage of T3, so it can be determined that VGS-Vth=(Vdata+Vth-ELVDD)-Vth=Vdata-ELVDD.

[0088] Further, after the refresh frame is completed and the hold frame is entered, in the reset phase of the hold frame, the reset unit 103 is started again, and the first reset voltage Vinit3 and the second reset voltage Vinit2 are connected from outside the pixel driving circuit 1 .

[0089] Part of the reset unit 103 is connected to Vinit3 and applies Vinit3 to N3, and applies Vinit3 to N1 through T3 in the turned-on state, so as to reset the voltages of N1 and N2.

[0090] Furthermore, the reset unit 103 of another part is connected to Vinit2 and applies Vinit2 to N4 connected to the driving unit 104 .

[0091] It can be seen that in this embodiment, based on the set reset unit 103, Vinit3 and Vinit2 can be connected from the outside during the reset stage of the refresh frame and the hold frame, so that the reset unit 103 can use Vinit3 to reset the voltage of N3 during the reset stage of the refresh frame and the hold frame; based on the set driving unit 104, it is achieved that in the driving stage, the source voltage is connected, so that the voltage of N3 and the gate-source voltage of T3 are adjusted according to the source voltage, and the pixel is lit.

[0092] In another embodiment of the present application, Figure 4 As shown, the driving unit 104 includes a third P-type transistor T5, a fourth P-type transistor T6 and a light emitting diode.

[0093] In this embodiment, T5 serves as a part of the driving unit 104, a source thereof is connected to ELVDD from outside the pixel driving circuit 1, a drain thereof is connected to N3, and a gate thereof is connected to the first driving signal ESTV.

[0094] Based on this, in the driving phase of refreshing frame and holding frame, as Figure 2 As shown, T5 is turned on based on the connected ESTV, and after being turned on, T5 applies the source-connected ELVDD to N3, so that the voltage at N3 is adjusted to ELVDD.

[0095] Furthermore, during the driving phase of the refresh frame, T3 remains turned on to apply the ELVDD at N3 to N1.

[0096] Further, T6 and the light emitting diode serve as another part of the driving unit 104, the source of T6 is connected to N1, the drain thereof is connected to N4, the gate thereof is connected to the second driving signal, and the second driving signal is also ESTV.

[0097] Based on this, in the driving phase of refreshing frame and holding frame, as Figure 2 As shown, T6 is turned on based on the connected ESTV, and after being turned on, T6 applies the source-connected ELVDD to N4.

[0098] Furthermore, the anode of the light emitting diode is connected to N4, so that the light emitting diode is lit when ELVDD is connected during the driving phase of the refresh frame.

[0099] It can be seen that based on T5, T6 and the light-emitting diode set in the driving unit 104, the source voltage is introduced by T5, and T5 and T6 are turned on when the driving signal is input, so that the source voltage is applied to the light-emitting diode, thereby lighting it.

[0100] In another embodiment of the present application, Figure 4 As shown, the reset unit 103 includes a fifth P-type transistor T8 and a sixth P-type transistor T7.

[0101] In this embodiment, T8 serves as a part of the reset unit 103 , with its source connected to the first reset voltage Vinit3 , its drain connected to N3 , and its gate connected to the first reset signal RSTV_H.

[0102] Based on this, Figure 2 As shown, after the writing phase of the refresh frame ends, it enters the reset phase, and after the reset phase of the refresh frame ends, it enters the driving phase of the refresh frame.

[0103] Further, when entering the reset phase of the refresh frame, if Figure 2 As shown, T8 is turned on based on the connected RSTV_H signal. After being turned on, T8 applies Vinit3 connected to its source to N3, thereby resetting the voltage at N3.

[0104] Further, T7 serves as another partial reset unit 103, with its source connected to the second reset voltage Vinit2, its drain connected to N4, and its gate connected to the second reset signal, and the second reset signal is also the RSTV_H signal.

[0105] Further, when entering the reset phase of the refresh frame, if Figure 2 As shown, T7 is turned on based on the connected RSTV_H signal. After being turned on, T7 applies Vinit2 connected to its source to N4, thereby resetting the voltage at N4.

[0106] In this embodiment, after the refresh frame ends, when entering the hold frame, when entering the reset phase of the hold frame, that is, Figure 2 There are 9 stages in it.

[0107] Based on this, when entering the reset phase of the holding frame, if Figure 2 As shown, T8 is turned on again based on the connected RSTV_H signal. After being turned on, T8 applies Vinit3 connected to its source to N3, thereby resetting the voltage at N3.

[0108] Furthermore, during the reset phase of the refresh frame, if Figure 2As shown, T7 is turned on again based on the RSTV_H signal connected. After being turned on, T7 applies Vinit2 connected to its source to N4, thereby resetting the voltage at N4.

[0109] It can be seen that in this embodiment, based on setting T8 in the reset unit 103, access to Vinit3 is implemented in the reset phase, and based on setting T7 in the reset unit 103, access to Vinit2 is implemented in the reset phase, and N3 is connected based on T8, so that the connected Vinit3 can reset N3, and N4 is connected based on T7, so that the connected Vinit2 can reset N4.

[0110] In another embodiment of the present application, the pixel driving circuit 1 further includes a first storage capacitor Cst1 .

[0111] In this embodiment, if Figure 4 As shown, one end of Cst1 is connected to the source voltage ELVDD, and the other end is connected to N2.

[0112] Based on this, Cst1 can start to access ELVDD before the refresh frame to charge in advance and discharge to N2 during the refresh frame and the hold frame.

[0113] It can be seen that in this embodiment, based on setting Cst1 connected to ELVDD, Cst1 can be charged according to ELVDD, and based on the connection between Cst1 and N2, Cst1 can be discharged to N2.

[0114] In another embodiment of the present application, the pixel driving circuit 1 further includes a second storage capacitor Cst2.

[0115] In this embodiment, if Figure 5 As shown, on the basis of Cst1, Cst2 is added, one end of Cst2 is connected to the source voltage ELVDD, and the other end is connected to N3.

[0116] Based on this, Cst2 can start to access ELVDD together with Cst1 before the refresh frame to charge in advance and discharge to N3 during the refresh frame and the hold frame.

[0117] It can be seen that after Cst2 and Cst1 are charged in advance together, based on the discharge to N2 and N3, they can charge T3 in advance together.

[0118] It can be seen that in this embodiment, based on Cst2 set on the basis of Cst1, Cst1 and Cst2 can jointly charge T3 in advance to maintain its gate-source voltage, and the charging and discharging amounts can be finely adjusted by adjusting the capacities of Cst1 and Cst2 respectively.

[0119] In another embodiment of the present application, the pixel driving circuit 1 further includes a third storage capacitor Cst3.

[0120] In this embodiment, if Figure 6 As shown, on the basis of Cst1, Cst3 is added, one end of Cst3 is connected to Vinit3, and the other end is connected to N3.

[0121] Based on this, Cst3 can be connected to Vinit3 in the refresh frame and the hold frame for charging, and discharge to N3 at the same time, so as to maintain the voltage of N3 in the hold frame consistent with the voltage in the refresh frame.

[0122] It can be seen that in this embodiment, based on Cst3 connected to Vinit3 set on the basis of Cst1, Cst3 can be charged according to Vinit3, and based on the connection between Cst3 and N3, Cst3 can be discharged to N3, thereby maintaining the voltage of N3 in the hold frame consistent with the refresh frame.

[0123] In another embodiment of the present application, the pixel driving circuit 1 further includes a fourth storage capacitor Cst4.

[0124] In this embodiment, if Figure 7 As shown, on the basis of Cst1, Cst3 is added, one end of Cst3 is connected to Vinit3, and the other end is connected to N1.

[0125] Based on this, Cst3 can be connected to Vinit3 in the refresh frame and the hold frame for charging, and discharge to N1 at the same time, so as to maintain the voltage of N1 in the hold frame consistent with the voltage in the refresh frame.

[0126] It can be seen that in this embodiment, based on Cst4 connected to Vinit3 set on the basis of Cst1, Cst4 can be charged according to Vinit3, and based on the connection between Cst4 and N1, Cst4 can be discharged to N1, thereby maintaining the voltage of N1 in the hold frame consistent with the refresh frame.

[0127] For the convenience of description, the above circuits are described by functions divided into various modules and / or units. Of course, when implementing the embodiments of the present application, the functions of each module and / or unit can be implemented in the same or multiple software and / or hardware.

[0128] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0129] Based on the same concept, corresponding to the pixel driving circuit in any of the above embodiments, the present application also provides a driving substrate, and the driving substrate includes the pixel driving circuit as described in any of the above embodiments.

[0130] Based on the same concept, corresponding to the driving substrate in the above embodiments, the present application also provides a display device, which includes the driving substrate as described in any of the above embodiments.

[0131] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0132] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0133] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0134] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the protection scope of the present application.

Claims

1. A pixel driving circuit, characterized in that: include; A reset unit, the reset unit comprising a first N-type transistor and a second N-type transistor; The drain of the first N-type transistor and the source of the second N-type transistor are connected to a first connection point, and are configured to remain turned on during a reset phase of a refresh frame, so that the source of the first N-type transistor is connected to a reset voltage from outside the pixel driving circuit, and the voltage of the first connection point is reset according to the reset voltage; and The device is configured to maintain the source-drain voltage of the first N-type transistor when maintaining the frame.

2. The pixel driving circuit according to claim 1, characterized in that: The reset unit further includes a first P-type transistor, a drain of the first P-type transistor and the first N-type transistor and the second N-type transistor are connected to the first connection point, and a gate of the first P-type transistor and the drain of the second N-type transistor are connected to a second connection point; The second N-type transistor is configured to remain turned on during a reset phase of a refresh frame, and the voltage of the first connection point is applied to the second connection point to reset the gate-source voltage of the first P-type transistor and turn on the first P-type transistor; The first P-type transistor is configured to reset a drain voltage of the first P-type transistor according to a voltage of the first connection point during a reset phase of a refresh frame.

3. The pixel driving circuit according to claim 2, characterized in that: Also includes: a writing unit connected to the source of the first P-type transistor at a third connection point; The writing unit is configured to, during a writing phase of a refresh frame, connect a writing voltage from outside the pixel driving circuit and apply the writing voltage to the third connection point; The second N-type transistor is also configured to remain turned on during the write phase of the refresh frame and form a diode connection with the first P-type transistor that remains turned on, applying the write voltage of the third connection point to the second connection point to adjust the voltage of the second connection point.

4. The pixel driving circuit according to claim 3, characterized in that: The writing unit includes a second P-type transistor connected to the first P-type transistor at the third connection point; The second P-type transistor is configured to remain turned on during the writing phase of the refresh frame, to connect a writing voltage from outside the pixel driving circuit, and to apply the writing voltage to the source of the first P-type transistor.

5. The pixel driving circuit according to claim 3, characterized in that: Also includes: a reset unit connected to the writing unit at the third connection point, and a driving unit connected to the reset unit at a fourth connection point; The reset unit is configured to, in a reset phase, connect a first reset voltage and a second reset voltage from outside the pixel driving circuit, apply the first reset voltage to the third connection point to reset the voltages of the first connection point and the third connection point according to the reset voltage, and apply the second reset voltage to the fourth connection point; The driving unit is configured to, during a driving phase, access a source voltage from outside the pixel driving circuit and apply the source voltage to the third connection point to adjust the gate-source voltage of the first P-type transistor, and drive the pixel based on the adjusted gate-source voltage of the first P-type transistor.

6. The pixel driving circuit according to claim 5, characterized in that: The driving unit comprises: a third P-type transistor, wherein the drain of the third P-type transistor is connected to the third connection point, and is configured such that, in a driving stage, the source of the third P-type transistor is connected to the source voltage from outside the pixel driving circuit, and the gate of the third P-type transistor is connected to the first driving signal from outside the pixel driving circuit, so as to turn on the third P-type transistor and apply the source voltage to the third connection point; The first P-type transistor is further configured to apply the source voltage of the third connection point to the first connection point; a fourth P-type transistor, wherein the source of the fourth P-type transistor is connected to the first connection point, the drain of the fourth P-type transistor is connected to the fourth connection point, and is configured such that, in a driving stage, the gate of the fourth P-type transistor is connected to a second driving signal from outside the pixel driving circuit to turn on the fourth P-type transistor, so as to apply the source voltage of the first connection point to the fourth connection point; and a light emitting diode having an anode connected to the fourth connection point and configured to light up in response to application of the source voltage.

7. The pixel driving circuit according to claim 5, characterized in that: The reset unit comprises: a fifth P-type transistor, the drain of which is connected to the third connection point, and configured to remain turned on during a reset phase of a refresh frame, access a first reset voltage from outside the pixel driving circuit, and apply the reset voltage to the third connection point, and remain turned on during a reset phase of a hold frame, access a first reset voltage from outside the pixel driving circuit, and apply the reset voltage to the third connection point; A sixth P-type transistor, wherein the drain of the sixth P-type transistor is connected to the fourth connection point, and is configured to remain turned on during the reset phase of the refresh frame, connect a second reset voltage from outside the pixel drive circuit, apply the reset voltage to the fourth connection point, and remain turned on during the reset phase of the hold frame, connect a second reset voltage from outside the pixel drive circuit, and apply the reset voltage to the fourth connection point.

8. The pixel driving circuit according to claim 3, characterized in that: Also includes: The first storage capacitor has one end connected to the source voltage and the other end connected to the second connection point, and is configured to be charged with the source voltage before the refresh frame and discharged to the second connection point.

9. The pixel driving circuit according to claim 8, characterized in that: Also includes: A second storage capacitor has one end connected to the source voltage and the other end connected to the third connection point, and is configured to be charged with the source voltage before the refresh frame and discharged to the third connection point, so that the second storage capacitor and the first storage capacitor can jointly charge the first P-type transistor in advance.

10. The pixel driving circuit according to claim 5, characterized in that: Also includes: A third storage capacitor has one end connected to the first reset voltage and the other end connected to the third connection point, and is configured to be charged with the first reset voltage and discharged to the third connection point in a refresh frame and a hold frame to maintain the voltage of the third connection point consistent in the refresh frame and the hold frame.

11. The pixel driving circuit according to claim 5, characterized in that: Also includes: A fourth storage capacitor has one end connected to the first reset voltage and the other end connected to the first connection point, and is configured to be charged with the first reset voltage and discharged to the first connection point in a refresh frame and a hold frame to maintain the voltage of the first connection point consistent in the refresh frame and the hold frame.

12. A driving substrate, characterized in that: The method comprises a plurality of pixel driving circuits according to any one of claims 1 to 11.

13. A display device, characterized in that: Includes the driving substrate as claimed in claim 12.

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