Ultra-low power consumption oscillator with power-on reset function

Abstract

The utility model discloses an ultra-low power consumption oscillator with a power-on reset function, which is characterized in that a POR circuit generates reference voltage by a transistor, the initial state of a POR signal is set to be zero by charging and discharging of an MOS (Metal Oxide Semiconductor) capacitor, and most of the POR circuit is cut off after a reset signal is released, so that quiescent current is greatly reduced. The oscillator circuit controlled by the POR signal is turned on and turned off in a matched mode, and stable oscillation output waveforms are generated within a specified voltage range. According to the utility model, the POR signal for detecting the power supply voltage range is provided while the stable oscillator signal is output, the power consumption of the circuit is extremely low, a resistance-free structure is adopted, the occupied area of the chip is small, and the circuit is suitable for a low-power SoC chip.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor integrated circuits, in particular to an ultra-low power consumption oscillator with a power-on reset function. Background Art

[0002] Devices used in the medical, Internet of Things, and wearable fields have achieved rapid development and widespread application, often requiring the chips used in the devices to be able to work continuously for months or even years, thus placing higher requirements on static power consumption, and the average power consumption of the circuits used is often limited to the nW level. Such devices are mainly used to detect signals that do not change rapidly, such as biological signals, and can still obtain relatively accurate measurement results when using interval sampling methods to collect signals.

[0003] In the low-power mode of the circuit, most of the circuit will be turned off during the measurement interval and turned on at intervals. The off time is controlled by the recording unit in the circuit. In the circuit, the oscillator as the clock signal generator and the power-on-reset circuit that controls the entire system to enter the initial working state by detecting the change in the power supply voltage need to work continuously, so controlling the power consumption of the two is the key to designing a low-power system. Utility Model Content

[0004] Based on the above background, the utility model provides an ultra-low power consumption oscillator with a power-on reset function, wherein the POR circuit uses a transistor to generate a reference voltage, uses the charge and discharge of a MOS capacitor to reset the initial state of the POR signal to zero, and cuts off most of the POR circuit after the reset signal is released, thereby greatly reducing the static current. The oscillator circuit controlled by the POR signal is turned on and off to generate a stable oscillation output waveform within a specified voltage range. The utility model provides a POR signal for detecting the power supply voltage range while outputting a stable oscillator signal. The circuit has extremely low power consumption, adopts a resistor-free structure, and occupies a small chip area, making it suitable for low-power SoC chips.

[0005] In the technical solution, the ultra-low power consumption oscillator provided by the utility model includes a power-on reset circuit and an oscillator circuit, wherein the power-on reset circuit includes a POR main circuit, an initial preset module, a voltage reference module and a power-off detection module.

[0006] The output end of the POR main circuit outputs a power-on reset signal; the initial preset module is used to ensure that the initial value of the output POR is 0 when the circuit is powered on, ensuring the normal operation of the POR circuit; the voltage reference module can generate a reference voltage VF related to the power supply voltage to drive the subsequent circuit; the power-off detection module can reset the POR voltage to zero when the power supply voltage drops to a certain level. The oscillator uses an oscillator circuit controlled by the POR signal to turn on and off, and generates a stable oscillation output waveform within the specified voltage range.

[0007] The voltage reference module includes four PMOS transistors MP1, MP2, MP3 and MP4, and two NMOS transistors MN1 and MN2. Among them: the source of MP1 is connected to the gate of MP3 and the drain of MP3; the drain of MP1, the drain of MN1, the gate of MN1 and the gate of MN2 are connected to each other; the sources of MN1 and MN2 are connected to the ground GND; the source of MP2 is connected to the gate of MP4 and the drain of MP4.

[0008] The POR main circuit includes six PMOS tubes MP5, MP6, MP7, MP8, MP9 and MP10, five NMOS tubes MN3, MN4, MN5, MN6 and MN7, three inverters INV3, INV4 and INV7, and a three-input NAND gate NAND. Among them: the sources of MP5, MP6, MP7, MP8, and MP10 are all connected to the power supply VDD; the drain of MP5, the gate of MP1, the source of MP3, and the source of MP4 are connected to each other; the gates of MP5, MP6, and MP9 are connected to the output terminal POR; the gate of MN3, the drain of MN2, the drain of MP2, and the gate of MP2 are connected to each other; the drain of MN3 is connected to the drain of MP6; the source of MN3, the drain of MN4, the gate of MN4, and the gate of MN5 are connected to each other; the source of MN4 and the source of MN5 are connected to the ground GND; the drain of MN5, the drain of MP7, the gate of MP7, and the gate of MP8 are connected to each other; the drain of MP8, the drain of MP9, the gate of MN6, and the drain of MN7 are connected to the node N1. The source and drain of MN6 are connected to the ground GND; the gate of MN7, the gate of MP10, the output of the NAND gate NAND and the input of the inverter INV7 are connected to each other; the source of MP9, the drain of MP10, the source of MN7 and the input of the inverter INV3 are connected to each other; the output of the inverter INV3 and the input of the inverter INV4 are connected to each other; the output of the inverter INV2 and the first input of the NAND gate NAND are connected to each other. The inverter INV7 outputs a POR signal.

[0009] The initial preset module includes a PMOS tube MP17 and an NMOS tube MN10, two inverters INV1 and INV2, wherein INV1 is a Schmitt inverter. The source of MP17 is connected to the power supply VDD; the gate of MP17, the drain of MN10, and the source of MN10 are connected to the ground GND; the drain of MP17, the gate of MN10 and the input end of the inverter INV1 are connected to each other; the output end of the inverter INV1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the third input end of the NAND gate NAND.

[0010] The power-off detection module includes 6 PMOS tubes MP11, MP12, MP13, MP14, MP15 and MP16, 3 NMOS tubes MN8, MN9 and MN11, and 2 inverters INV5 and INV6. The sources of MP11 and MP15 are connected to the power supply VDD; the gate of MP11, the drain of MP11 and the source of MP12 are connected to each other; the gate of MP12, the drain of MP12 and the source of MP13 are connected to each other; the gate of MP13, the drain of MP13, the source of MP14, the gate of MP16 and the gate of MN9 are connected to each other; the gate of MP14, the drain of MP14, the source of MN8, the drain of MN8, the source of MN9 and the source of MN11 are connected to the ground GND. The gate of MP15, the drain of MP15, the source of MP16 and the gate of MN8 are interconnected; the drain of MP16, the drain of MN9 and the input of INV5 are interconnected; the output of INV5, the input of INV6 and the second input of the NAND gate NAND are interconnected; the output of INV6 and the gate of MN11 are interconnected; the drain of MN11 is connected to the node N1.

[0011] The oscillator circuit may adopt an existing oscillator circuit whose opening and closing are controlled by a POR signal. The utility model also provides a preferred oscillator circuit.

[0012] The preferred oscillator circuit includes 8 PMOS tubes MP18, MP19, MP20, MP21, MP22, MP23, MP24 and MP25, 8 NMOS tubes MN12, MN13, MN14, MN15, MN16, MN17, MN18 and MN19, and 3 inverters INV8, INV9 and INV10. Among them: the gate of MP18 and the gate of MN16 are connected to the output signal POR; the sources of MP18, MP19, MP23 and MP25 are all connected to the power supply VDD; the sources of MN16, MN18 and MN19 are all connected to the ground GND. The gates of MP19, MP20, MP21, MP22, MN12, MN13, MN14, MN15, the drain of MN19, the drain of MP25 and the input terminal of the inverter INV8 are connected to each other; the gates of MP23, MP24, MN17, MN18 and the drains of MP18, MP22, MN12 are connected to each other; the drain of MP19 and the source of MP20 are connected to each other; the drain of MP20 and the source of MP21 are connected to each other; the drain of MP21 and the source of MP22 are connected to each other; the drain of MP23 and the source of MP24 are connected to each other; The drains of MP24, MP25, MN17, and MN19 are connected to each other; the source of MN12 is connected to the drain of MN13; the source of MN13 is connected to the drain of MN14; the source of MN14 is connected to the drain of MN15; the source of MN15 is connected to the drain of MN16; the source of MN17 is connected to the drain of MN18; the output of inverter INV8 is connected to the input of inverter INV9; the output of inverter INV9 is connected to the input of inverter INV10; the output oscillation signal V of inverter INV10 is connected to each other. CLK . BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a schematic block diagram of the utility model;

[0014] Figure 2 It is a schematic diagram of a power-on reset (POR) circuit in the utility model;

[0015] Figure 3 This is a schematic diagram of the oscillator circuit in the utility model;

[0016] Figure 4 A schematic diagram of a power-on reset voltage waveform generated in the utility model;

[0017] Figure 5 The test results of the oscillation frequency and circuit power consumption of the utility model are described. DETAILED DESCRIPTION

[0018] The technical solution of the present utility model is described in detail below with reference to the accompanying drawings and embodiments for better understanding.

[0019] Figure 2 As shown, the POR circuit uses the delay of power supply to shut down to minimize the static current. In the voltage reference module, the intrinsic transistor MP1 is used as a current generator. MP5, MP6, MP9, MP10, and MN7 are used as digital switches to control the circuit state. MP1, MP2, MP3, and MP4 are in the subthreshold region, and the current of transistor MP1 is: The current of transistor MP3 is: Because I MP1 =I MP3 , the voltage at point V1 is:

[0020] MN1 and MN2 form a current mirror to copy the current. The currents of MP2 and MP4 are equal to MP3, so the current of MP4 is: Since MP3 and MP4 have the same size, and I MP3 =I MP4 , so the voltage at point V2 can be approximately expressed as:

[0021] The current of MP2 can be expressed as, since MP2 and MP3 have the same size and I MP2 =I MP3 , so the reference voltage V f It can be approximately expressed as:

[0022]

[0023] In order to ensure that the initial value of the POR signal is 0 when the circuit is powered on, the working process of the initial preset module is as follows: when the power supply voltage starts to rise, the transistor MP17 starts to charge the transistor MN10 connected as a capacitor. Before the node N2 rises to the turn-on voltage of the Schmitt inverter INV1, the output of the initial preset module remains 0, and the initial preset POR is 0. After the initial preset, the node N2 voltage is slowly charged to VDD.

[0024] Since POR=0, PORN=1, transistors MP5, MP6, MP9 and MN7 are turned on, and the POR circuit starts to work. The voltage reference module starts to generate a reference voltage. When the reference voltage V F Greater than the threshold voltage VTH of MN3 MN3 When MN3 is turned on and works in the subthreshold region, the output POR jumps from 0 to VDD.

[0025] Before the power supply voltage rises to the trip voltage, MN3 is turned off, MN4, MN5, MP7, and MP8 are all turned off, node N1 remains at a low level, and the INV3 output remains at a high level, causing the POR to remain at a low level. When the power supply voltage is higher than the trip voltage, MN3 is turned on, MP8 charges the transistor MN6 connected as a capacitor, and the voltage at node N1 rises. After node N2 rises to the turn-on voltage of inverter INV3, the INV3 output becomes a low level, and POR becomes VDD. After POR becomes VDD, MP5, MP6, MP9, and MN7 are turned off, most of the circuits are cut off, and the transmission gates (MP9 and MN7) work as isolation units. At this time, MP10 is in the on state to maintain the voltage at point N3 to avoid large leakage current caused by floating nodes.

[0026] The power-off detection module is designed for reset operation when the power supply voltage drops. When the power supply voltage rises, VDD charges MN8 through MP15, and the voltage of node N4 is temporarily stored by MN 8. Stacked PMOS transistors (MP11-MP14) are selected as voltage dividers to divide VDD to reduce area and power overhead, and input to the input of the inverter composed of MP 17 and MN 11. When the power supply voltage decreases, when the voltage at point N5 decreases to below the switching voltage of the inverter composed of MP 17 and MN 11, the voltage of node N6 decreases from VDD to 0. Then, the voltage of POR drops to 0, and node N1 is fully discharged through MN 11.

[0027] The voltage reference module of the POR circuit of this embodiment uses a PMOS intrinsic transistor to generate a reference voltage related to VDD. The power-on reset trip voltage in the POR circuit is related to the threshold voltage of the NMOS tube turned on by the reference voltage, and the power-off detection voltage is related to the VTH of the inverter NMOS tube. The threshold voltage of the transistor changes with different processes, temperatures, and power supplies, thereby affecting the trip voltage of the POR circuit. Therefore, the proposed improved structure enables VPOR and VBOD to change together when the NMOS tube changes under the influence of PVT, which is more conducive to circuit design and application.

Claims

1. An ultra-low power oscillator with a power-on reset function, comprising a power-on reset circuit and an oscillator circuit whose opening and closing are controlled by a POR signal, characterized in that: The power-on reset circuit comprises: PMOS tubes MP1-MP17, NMOS tubes MN1-MN11, inverters INV1-INV7, wherein INV1 is a Schmitt inverter; The source of MP1 is connected to the gate of MP3 and the drain of MP3; the drain of MP1 is connected to the drain of MN1, the gate of MN1 and the gate of MN2; the sources of MN1, MN2, MN4 and MN5 are all connected to the ground GND; the source of MP2 is connected to the gate of MP4 and the drain of MP4; The sources of MP5, MP6, MP7, MP8, and MP10 are all connected to the power supply VDD; the drain of MP5, the gate of MP1, the source of MP3, and the source of MP4 are connected to each other; the gates of MP5, MP6, and MP9 are all connected to the output terminal POR; the gate of MN3, the drain of MN2, the drain of MP2, and the gate of MP2 are connected to each other; the drain of MN3 is connected to the drain of MP6; the source of MN3, the drain of MN4, the gate of MN4, and the gate of MN5 are connected to each other; the drain of MN5, the drain of MP7, the gate of MP7, and the gate of MP8 are connected to each other; 9. The drains of MN7 and MN11 and the gate of MN6 are all connected to the node N1; the source and drain of MN6, the source and drain of MN10 are all connected to the ground GND; the gates of MN7 and MP10, the output of the NAND gate NAND, and the input of the inverter INV7 are connected to each other; the sources of MN7 and MP9, the drain of MP10 and the input of the inverter INV3 are connected to each other; the output of the inverter INV3 is connected to the input of the inverter INV4; the output of the inverter INV2 is connected to the first input of the NAND gate NAND; the inverter INV7 outputs a POR signal; The source of MP17 is connected to the power supply VDD; the gate of MP17 is connected to the ground GND; the drain of MP17, the gate of MN10 and the input of the inverter INV1 are connected to each other; the output of the inverter INV1 is connected to the input of the inverter INV2; the output of the inverter INV2 is connected to the third input of the NAND gate NAND; The sources of MP11 and MP15 are connected to the power supply VDD; the gate and drain of MP11 and the source of MP12 are connected to each other; the gate and drain of MP12 and the source of MP13 are connected to each other; the gate and drain of MP13 and the source of MP14, the gate of MP16, and the gate of MN9 are connected to each other; the gate and drain of MP14, the source and drain of MN8, and the sources of MN9 and MN11 are connected to the ground GND; the gate and drain of MP15, the source of MP16, and the gate of MN8 are connected to each other; the drain of MP16, the drain of MN9, and the input end of the inverter INV5 are connected to each other; the output end of the inverter INV5, the input end of the inverter INV6, and the second input end of the NAND gate NAND are connected to each other; the output end of the inverter INV6 is connected to the gate of MN11.

2. The ultra-low power consumption oscillator according to claim 1, characterized in that: The oscillator circuit includes: PMOS tubes MP18-MP25, NMOS tubes MN12-MN19, and inverters INV8-INV10; The gate of MP18 and the gate of MN16 are connected to the POR signal terminal; the sources of MP18, MP19, MP23 and MP25 are connected to the power supply VDD; the sources of MN16, MN18 and MN19 are connected to the ground GND; the gates of MP19, MP20, MP21, MP22, MN12, MN13, MN14 and MN15, the drain of MN19, the drain of MP25 and the input terminal of the inverter INV8 are connected to each other; the gates of MP23, MP24, MN17 and MN18, and the drains of MP18, MP22 and MN12 are connected to each other; the drain of MP19 is connected to the source of MP20; the drain of MP20 is connected to the input terminal of MP The source of MN12 is connected to the drain of MN13; the drain of MN13 is connected to the drain of MN14; the source of MN14 is connected to the drain of MN15; the source of MN15 is connected to the drain of MN16; the source of MN17 is connected to the drain of MN18; the output end of inverter INV8 is connected to the input end of inverter INV9; the output end of inverter INV9 is connected to the input end of inverter INV10; the output end of inverter INV10 outputs the oscillation signal V CLK .

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