Inter-service board excitation signal collaboration device and test machine

Abstract

The utility model relates to an excitation signal collaboration device between service boards and a test machine, the collaboration device comprises a communication board and more than two service boards; the communication board comprises a phase-locked loop module, a control module and a fan-out module, the phase-locked loop module is connected with the control module and each service board, and the phase-locked loop module outputs a system clock to the control module and each service board; the control module is connected with the fan-out module, the fan-out module is connected with each service board, and the control module outputs a low-speed clock signal to the fan-out module, so that the fan-out module outputs the aligned low-speed clock signal to each service board; the control module is connected with each service board and outputs an excitation signal to each service board. Hardware excitation is cooperated with each service board, compared with a soft excitation scheme, the time delay is small, the real-time performance is good, and the service operation efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to an inter-service board excitation signal coordination device and a testing machine. Background Art

[0002] Semiconductor automated testing refers to the use of automatic test equipment (ATE) to test various parameters of the device under test (DUT) to eliminate defective products and control the factory quality of semiconductor devices. Traditional testers use soft stimulus solutions to coordinate between business boards. Message packets are sent through the high-speed communication bus between the communication board and the business board. The stimulus message type is defined in advance in the communication protocol, and it is agreed that after the business board receives the stimulus message packet, it will delay the preset time to start executing the business scenario corresponding to the stimulus message packet. This has the disadvantage of low business operation efficiency. Utility Model Content

[0003] Based on this, it is necessary to provide a service board excitation signal coordination device and a test machine to improve service operation efficiency in order to solve the above problems.

[0004] An inter-service board excitation signal coordination device comprises a communication board and a service board, wherein the number of the service boards is more than two; the communication board comprises a phase-locked loop module, a control module and a fan-out module, wherein the phase-locked loop module is connected to the control module and each service board, and the phase-locked loop module outputs a system clock to the control module and each service board; the control module is connected to the fan-out module, and the fan-out module is connected to each service board, and the control module outputs a slow clock signal to the fan-out module, so that the fan-out module outputs an aligned slow clock signal to each service board; the control module is connected to each service board, and outputs an excitation signal to each service board.

[0005] In one of the embodiments, the inter-service board excitation signal coordination device further includes a backplane, and the phase-locked loop module, the fan-out module, and the control module are respectively connected to each of the service boards through the backplane.

[0006] In one of the embodiments, the control module includes a clock manager and an excitation generator, the clock manager is connected to the phase-locked loop module, the excitation generator and the fan-out module, and the excitation generator is connected to each of the service boards through the backplane.

[0007] In one embodiment, the control module further includes a frequency re-division unit, and the clock manager is connected to the stimulus generator via the frequency re-division unit.

[0008] In one of the embodiments, the clock manager is a mixed mode clock manager.

[0009] In one of the embodiments, the service board includes a service control module, and the service control module is connected to the phase-locked loop module, the excitation generator and the fan-out module through the backplane.

[0010] In one of the embodiments, the service control module includes a sampling module and a service module, the sampling module is connected to the service module and is connected to the excitation generator and the fan-out module through the backplane, and the service module is connected to the phase-locked loop module through the backplane.

[0011] In one embodiment, the control module is a FPGA.

[0012] A testing machine comprises the above-mentioned inter-service board excitation signal coordination device.

[0013] In one of the embodiments, the test machine further includes a host computer, which is connected to a communication board of the inter-service board excitation signal coordination device.

[0014] In the above-mentioned inter-service board excitation signal coordination device and test machine, the phase-locked loop module of the communication board outputs the system clock to the control module and each service board, the control module outputs the excitation signal to each service board, and also outputs the slow clock signal to the fan-out module, so that the fan-out module outputs the aligned slow clock signal to each service board. The slow clock signal is aligned and output to each service board through the fan-out module, so that the service board samples the excitation signal according to the received slow clock signal, realizing hardware excitation coordination with each service board, which has a small delay and good real-time performance compared to the soft excitation scheme, and improves the service operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structure of an inter-service board excitation signal coordination device in one embodiment;

[0016] Figure 2 is a schematic diagram of the structure of a control module in one embodiment;

[0017] Figure 3 is a schematic diagram of the structure of a control module in another embodiment;

[0018] Figure 4 is a schematic diagram of the structure of a service control module in an embodiment;

[0019] Figure 5 A timing diagram of a communication board stimulating a service board in one embodiment;

[0020] Figure 6 FIG. 1 is a timing diagram for the use of excitation signal expansion in one embodiment. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0023] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0024] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.

[0025] The current test machine adopts a soft excitation scheme to coordinate between business boards. The message packet is sent through the high-speed communication bus (such as Aurora protocol bus) between the communication board and the business board. After the business board receives the excitation message packet, it delays the preset time and then starts to execute the business scenario corresponding to the excitation message packet together. This brings two problems: 1. If the preset time is defined too long, it will affect the efficiency of business operation; if the preset time is defined too short, due to the difference in communication delay between different business boards, some business boards may not receive the message, and the other part of the business boards may have started to execute the business; 2. The excitation message packet and the business message packet share a communication bus, and it is inevitable that they will be coupled with each other, competing for communication bus resources, and the software processing flow may be blocked, resulting in reduced efficiency and even operation errors. Based on this, the present application provides an excitation signal coordination device between business boards, the phase-locked loop module of the communication board outputs the system clock to the control module and each business board, the control module outputs the excitation signal to each business board, and also outputs the slow clock signal to the fan-out module, so that the fan-out module outputs the aligned slow clock signal to each business board. The slow clock signal is aligned through the fan-out module and then output to each business board, so that the business board can sample the excitation signal according to the received slow clock signal, realizing hardware excitation coordination among the business boards. Compared with the soft excitation solution, it has small delay, good real-time performance, and improves business operation efficiency.

[0026] In one embodiment, Figure 1 As shown, an inter-service board excitation signal coordination device is provided, including a communication board 100 and a service board 200, the number of which is more than two; the communication board 100 includes a phase-locked loop module PLL, a control module 120 and a fan-out module 140, the phase-locked loop module PLL connects the control module 120 and each service board 200, and the phase-locked loop module PLL outputs a system clock to the control module 120 and each service board 200; the control module 120 is connected to the fan-out module 140, the fan-out module 140 is connected to each service board 200, the control module 120 outputs a slow clock signal to the fan-out module 140, so that the fan-out module 140 outputs an aligned slow clock signal to each service board 200; the control module 120 is connected to each service board 200, and outputs an excitation signal to each service board 200. In addition, the inter-service board excitation signal coordination device also includes a backplane 300, and the phase-locked loop module PLL, the fan-out module 140, and the control module 120 are respectively connected to each service board 200 through the backplane 300. The specific number of the service boards 200 can be set according to actual needs. For ease of understanding, the following explanation is given using two service boards 200 as an example.

[0027] Specifically, the type of the control module 120 is not unique, and can be a device such as FPGA (Field-Programmable Gate Array), MCU (Micro Control Unit), CPU (Central Processing Unit), etc. In this embodiment, the control module 120 uses FPGA. The control module 120 controls a group of excitation signals and a group of slow clock signals of the service board 200 in each slot of the test machine. The excitation signal can be a single-ended or differential signal. The communication board 100 and the two service boards 200 communicate through the backplane 300. The phase-locked loop module PLL on the communication board 100 outputs the system clock to the control module 120 and the service board 200, namely, the system clock ①, the system clock ④ and the system clock ⑦, as the main clock of the control module 120 and the service board 200. The control module 120 divides the system clock ①, for example, by 100, and the obtained slow clock signal is sent to the fan-out module 140 for alignment. The fan-out module 140 outputs the slow clock signal ⑤ and the slow clock signal ⑧ to the corresponding service board 200. The control module 120 also generates the excitation signal ③ and the excitation signal ⑥ according to the slow clock signal obtained by the frequency division and sends them to the corresponding service board 200. Each service board 200 samples the received excitation signal according to the received slow clock signal, and performs corresponding service processing according to the sampling result. The slow clock signal is aligned through the fan-out module 140 and then output to each business board 200, thereby reducing the delay error of each business board 200 receiving the slow clock signal. After receiving the slow clock signal, the business board 200 can directly sample the excitation signal and then perform corresponding business processing, thereby realizing hardware excitation coordination with each business board 200. Compared with the soft excitation scheme, it has the advantages of small delay and good real-time performance.

[0028] In one embodiment, Figure 2 As shown, the control module 120 includes a clock manager 122 and an excitation generator 124. The clock manager 122 is connected to the phase-locked loop module PLL, the excitation generator 124 and the fan-out module 140. The excitation generator 124 is connected to each service board 200 through the backplane 300. Among them, the clock manager 122 can adopt a mixed mode clock manager (MMCM). The clock manager 122 generates a slow clock signal ② according to the system clock ① output by the phase-locked loop module PLL, and sends it to the excitation generator 124 and the fan-out module 140. The excitation generator 124 generates excitation signals ③ and ⑥ according to the falling edge of the slow clock signal, and sends them to the corresponding service board 200 through the backplane 300. In addition, as Figure 1As shown, the service board 200 may specifically include a service control module 220. The service control module 220 is connected to the phase-locked loop module PLL, the excitation generator 124 and the fan-out module 140 through the backplane 300, and receives the system clock, the excitation signal and the slow clock signal. The service control module 220 may be a device such as FPGA, MCU, CPU, etc. In this embodiment, the service control module 220 also uses FPGA.

[0029] Further, in one embodiment, if Figure 3 As shown, the control module 120 further includes a re-dividing unit 126, and the clock manager 122 is connected to the excitation generator 124 via the re-dividing unit 126. The slow clock signal ② obtained by the frequency division of the clock manager 122 is transmitted to the re-dividing unit 126 and the fan-out module 140. The re-dividing unit 126 re-divides the slow clock signal ②, for example, divides it into two, and then transmits it to the excitation generator 124. The excitation generator 124 generates an excitation signal carrying a frame header and an excitation type according to the re-divided clock signal.

[0030] The specific structure of the service control module 220 is not unique. In one embodiment, Figure 4 As shown, the service control module 220 includes a sampling module 222 and a service module 224. The sampling module 222 is connected to the service module 224 and is connected to the excitation generator 124 and the fan-out module 140 through the backplane 300. The service module 224 is connected to the phase-locked loop module PLL through the backplane 300. The service module 224 receives the system clock ④ output by the phase-locked loop module PLL through the backplane 300, and the sampling module 222 receives the excitation signal ③ output by the excitation generator 124 and the slow clock signal ⑤ output by the fan-out module 140 through the backplane 300. The sampling module 222 samples the received excitation signal ③ according to the received slow clock signal ⑤.

[0031] It can be understood that, according to the different ways in which the control module 120 outputs the excitation signal ③, the sampling module 222 will also sample the received excitation signal ③ in different ways. When the control module 120 does not include the re-dividing unit 126, and the excitation generator 124 generates the excitation signal ③ according to the falling edge of the slow clock signal ②, the sampling module 222 samples the received excitation signal ③ according to the rising edge of the received slow clock signal ⑤, and generates a start signal to input to the service module 224 when the excitation signal ③ is sampled as a high level. The service module 224 performs corresponding service processing when the start signal is received and the next rising edge of the system clock ④. When the control module 120 includes the re-dividing unit 126, and the excitation generator 124 generates the excitation signal ③ carrying the frame header and the excitation type according to the re-divided clock signal, the sampling module 222 samples the received excitation signal ③ according to the rising edge of the received slow clock signal ⑤ to obtain the excitation type, and the service module 224 performs corresponding service processing according to the excitation type obtained by sampling.

[0032] Specifically, Figure 5 As shown, the communication board 100 excites the service board 200 including the following steps:

[0033] 1. The communication board 100 divides the system clock by 100: system clock ①→slow clock signal ②, and provides slow clock signals (which are the same source as the system clock ① of the communication board 100) to multiple business boards 200 (taking 2 business boards 200 as an example): system clock ①→slow clock signal ⑤, system clock ①→slow clock signal ⑧.

[0034] 2. The falling edge of the slow clock signal ② after the frequency division of the communication board 100 generates the excitation signal of the business board 200: slow clock signal ②→excitation signal ③, slow clock signal ②→excitation signal ⑥.

[0035] 3. The excitation signal is sampled by the rising edge of the slow clock signal of the service board 200, and the high level is effective. Figure 5 As shown by the blue dotted line in the middle, the rising edge of the slow clock signal ⑤ is used to sample the excitation signal ③, and the rising edge of the slow clock signal ⑧ is used to sample the excitation signal ⑥.

[0036] 4. When the service board 200 samples the high level of the excitation signal, the next rising edge of the system clock starts the service process. Figure 5 As shown by the red arrow in the middle, when the high level of the excitation signal ③ is sampled, the next rising edge of the system clock ④ starts the business process; when the high level of the excitation signal ⑥ is sampled, the next rising edge of the system clock ⑦ starts the business process.

[0037] Among them, the offset time Skew1 of the system clock on different business boards 200 is determined by the inter-channel offset time skew (about 30ps) of the phase-locked loop module PLL itself and the difference in the length of the routing line (±5mil, the deviation is less than 2ps), so the offset time Skew1 can be controlled within 100ps. The offset time Skew2 of the excitation signal on different business boards 200 is determined by the length of the internal routing line of the FPGA and the total length of the routing line of the entire board. The length of the internal routing line of the FPGA can be easily controlled within 2ns, and the skew of 10ns. The total length of the routing line of the entire board (communication board 100+backplane 300+business board 200) is calculated according to the 8ns margin and the inner layer routing 166ps / inch, and the deviation can be easily controlled within 48 inches. Therefore, the offset time Skew2 can be controlled within 100ps.

[0038] In addition, the excitation signal can be extended, such as Figure 6 As shown, the divided slow clock signal on the communication board 100 is further divided by two to generate an excitation signal ③. In the excitation signal ③, the high level 1 is used as the frame header, and the following M bits are the agreed excitation types. The number of excitation types can be expanded according to actual needs. The rising edge of the slow clock signal ② is used on the service board 200 to sample the excitation signal ③, and the corresponding service process is processed according to the corresponding excitation type.

[0039] The above-mentioned inter-service board excitation signal coordination device adopts hardware excitation to coordinate each service board 200. The hardware uses an independent channel, which has fast speed, large timing margin and high reliability. Compared with message excitation, hardware excitation has small delay, good real-time performance and high efficiency. The hardware excitation control process is simple, and the architecture is scalable and can adapt to various excitation types. In addition, the excitation signal output from the communication board 100 to the service board 200 does not need to be strictly constrained to be equal length, and the wiring of the entire board is simple.

[0040] In one embodiment, a test machine is provided, including the above-mentioned inter-service board excitation signal coordination device. In addition, the test machine also includes a host computer, which is connected to a communication board of the inter-service board excitation signal coordination device. The host computer can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers and portable wearable devices, and the portable wearable devices can be smart watches, smart bracelets, head-mounted devices, etc.

[0041] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0042] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the utility model patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A device for coordinating excitation signals between service boards, characterized in that: It includes a communication board and a business board, and the number of the business boards is more than two; the communication board includes a phase-locked loop module, a control module and a fan-out module, the phase-locked loop module is connected to the control module and each of the business boards, and the phase-locked loop module outputs a system clock to the control module and each of the business boards; the control module is connected to the fan-out module, and the fan-out module is connected to each of the business boards, and the control module outputs a slow clock signal to the fan-out module, so that the fan-out module outputs an aligned slow clock signal to each of the business boards; the control module is connected to each of the business boards, and outputs an excitation signal to each of the business boards.

2. The device according to claim 1, characterized in that It also includes a backplane, and the phase-locked loop module, the fan-out module, and the control module are respectively connected to each of the service boards through the backplane.

3. The device according to claim 2, characterized in that The control module includes a clock manager and an excitation generator. The clock manager is connected to the phase-locked loop module, the excitation generator and the fan-out module. The excitation generator is connected to each of the service boards through the backplane.

4. The device according to claim 3, characterized in that The control module further comprises a re-frequency division unit, and the clock manager is connected to the stimulus generator via the re-frequency division unit.

5. The device according to claim 3, characterized in that The clock manager is a mixed mode clock manager.

6. The device according to any one of claims 3 to 5, characterized in that: The service board includes a service control module, and the service control module is connected to the phase-locked loop module, the excitation generator and the fan-out module through the backplane.

7. The device according to claim 6, characterized in that The service control module includes a sampling module and a service module. The sampling module is connected to the service module and is connected to the excitation generator and the fan-out module through the backplane. The service module is connected to the phase-locked loop module through the backplane.

8. The device according to any one of claims 1 to 5, characterized in that: The control module is FPGA.

9. A testing machine, characterized in that: It includes the inter-service board excitation signal coordination device as described in any one of claims 1-8.

10. The testing machine according to claim 9, characterized in that: It also includes a host computer, which is connected to the communication board of the inter-service board excitation signal coordination device.

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