Chip power supply circuit, chip and electronic equipment

Abstract

The utility model provides a chip power supply circuit, a chip and electronic equipment. The chip power supply circuit comprises a DC-DC module, a first LDO module, a second LDO module and a main control module. The DC-DC module is connected with the enabling end of the first LDO module and the enabling end of the second LDO module, so that whether the first LDO module and the second LDO module are in the enabling state or not is controlled through the DC-DC module, whether the first LDO module supplies power to an IO port of the main control module or not is controlled, and whether the second LDO module supplies power to an inner core of the main control module or not is controlled. Power supply protection on the core of the main control module in the power supply process is realized, and the use safety and reliability of the chip power supply circuit are effectively improved.

Description

Technical Field

[0001] The present application relates to the technical field of electronic circuits, and in particular to a chip power supply circuit, a chip and an electronic device. Background Art

[0002] FLASH FPGA chips are widely used in military, aerospace and other fields due to their non-volatile programs, high reliability and reprogrammability. FPGA chips usually require two voltages to operate, one is the "core power supply voltage" and the other is the "IO power supply voltage (input and output voltage)". Each voltage is provided through an independent power pin. The core power supply voltage (VCCINT) of the FPGA chip is used to provide voltage to the logic gates and triggers inside the FPGA chip. This voltage is getting lower and lower with the development of FPGA. The core power supply voltage is generally fixed and determined according to the mode of the FPGA used. The IO power supply voltage (VCCIO) of the FPGA chip is the voltage used for the input and output modules (IO pins) of the FPGA. This voltage should match the voltage of other devices connected to the FPGA.

[0003] When the external power is on, the core power and IO power of the FPGA chip are powered on normally, and the logic circuit inside the FPGA chip starts to work normally; when the external power is off, the core power and IO power of the chip are powered off, and the logic circuit inside the chip stops working. However, when the existing FLASH-type FPGA chip is powered on by the IO power and the core power is off, the IO power will leak to the core power, causing the logic circuit of the core of the FPGA chip to partially enter the working state under the leakage voltage, which will cause the program initialization abnormality when the core of the FPGA chip is powered on normally again, and it cannot start running normally or burns out, thereby damaging the system circuit and reducing the circuit safety.

[0004] Therefore, how to provide a chip power supply circuit, a chip, and an electronic device that can ensure the circuit safety of the chip during power-off has become one of the problems that urgently need to be solved in the field. Utility Model Content

[0005] The present application aims to solve one of the technical problems in the related art at least to some extent.

[0006] To this end, the first purpose of the present application is to propose a chip power supply circuit, a chip and an electronic device, which can improve the safety of the chip power supply circuit and ensure normal initialization operation after the signal is powered on.

[0007] To achieve the above-mentioned purpose, the first aspect of the present application proposes a chip power supply circuit, which includes a DC-DC module, a first LDO module, a second LDO module and a main control module, wherein the first output end of the DC-DC module is connected to the input end of the first LDO module, the output end of the first LDO module is respectively connected to the first input end of the main control module and the input end of the second LDO module, and the output end of the second LDO module is connected to the second input end of the main control module; the second output end of the DC-DC module is respectively connected to the enable end of the first LDO module and the second LDO module, so that the first LDO module is in an enabled state and can supply power to the IO port of the main control module and the second LDO module, and the second LDO module is in an enabled state and can supply power to the core of the main control module.

[0008] In a possible embodiment, the voltage of the external input power supply connected to the DC-DC module is 12V, and is converted into a 5.2V voltage through an internal step-down circuit to power the first LDO module, and is converted into a 5V voltage to provide an enable signal for the first LDO module and the second LDO module; the first LDO module converts the input 5.2V voltage into a 3.3V voltage to power the second LDO module and the IO port of the main control module; the second LDO module converts the input 3.3V voltage into a 1.5V voltage to power the core of the control module.

[0009] In a possible embodiment, the DC-DC module is configured as an LTM4644 chip, the first LDO module and the second LDO module are configured as an LT3033 chip, and the main control module is configured as an A3P1000 chip.

[0010] To achieve the above-mentioned purpose, a second embodiment of the present application proposes a chip, which includes the chip power supply circuit described in any one of the above-mentioned embodiments.

[0011] To achieve the above-mentioned purpose, a third aspect of the present application provides an electronic device, which comprises the chip power supply circuit and the chip as described in any one of the above-mentioned embodiments.

[0012] The chip power supply circuit, chip and electronic device provided by the present application have at least the following beneficial effects:

[0013] The present application provides a chip power supply circuit, a chip and an electronic device, wherein the chip power supply circuit includes a DC-DC module, a first LDO module, a second LDO module and a main control module. The first output end of the DC-DC module is connected to the input end of the first LDO module, the output end of the first LDO module is respectively connected to the first input end of the main control module and the input end of the second LDO module, and the output end of the second LDO module is connected to the second input end of the main control module; the second output end of the DC-DC module is respectively connected to the enable end of the first LDO module and the second LDO module. By using the DC-DC module to control whether the first LDO module and the second LDO module are in an enabled state, whether the first LDO module supplies power to the IO port of the main control module, and whether the second LDO module supplies power to the core of the main control module, the power supply protection of the core of the main control module is realized during the power supply process, and the use safety and reliability of the chip power supply circuit are effectively improved.

[0014] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0016] Figure 1 It is a schematic diagram of the structure of a chip power supply circuit according to an embodiment of the present application.

[0017] 101 DC-DC module; 102 first LDO module; 103 second LDO module; 104 main control module. DETAILED DESCRIPTION

[0018] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0019] The core power supply voltage of the FLASH FPGA chip is used to provide voltage to the logic gates and triggers inside the FPGA chip. This voltage is getting lower and lower with the development of FPGA. The core power supply voltage is generally fixed and determined according to the mode of the FPGA used. The IO power supply voltage of the FPGA chip is the voltage used for the input and output modules of the FPGA. This voltage should match the voltage of other devices connected to the FPGA.

[0020] However, the applicant discovered that the core power supply voltage of the existing FLASH-type FPGA chip is input by the core power supply LDO, and the voltage of the core power supply LDO is generated by the IO power supply input end. When the core power supply of the FPGA chip is not powered on, the IO power supply input end will provide a leakage voltage of about 0.8V to the core power supply LDO, enable the core power supply LDO, and provide a voltage of about 0.6V to the core power supply, so that the FPGA chip enters a certain working state, resulting in the FPGA chip being unable to start normally when it is powered on normally later.

[0021] Based on the above problems, the first embodiment of the present application provides a chip power supply circuit, such as Figure 1 As shown, the chip power supply circuit includes a DC-DC module 101, a first LDO module 102, a second LDO module 103 and a main control module 104. Among them, the first output end (OUT1 in the figure) of the DC-DC module 101 is connected to the input end (IN in the figure) of the first LDO module 102, the output end (OUT in the figure) of the first LDO module 102 is respectively connected to the first input end (IO Bank in the figure) of the main control module 104 and the input end of the second LDO module 103, and the output end (OUT in the figure) of the second LDO module 103 is connected to the second input end (Core in the figure) of the main control module 104; the second output end (OUT2 in the figure) of the DC-DC module 101 is respectively connected to the enable end (SHDN# in the figure) of the first LDO module 102 and the second LDO module 103.

[0022] It is understandable that the DC-DC module 101 is used to connect to an external power supply, and its internal step-down circuit can output the DC high voltage input by the external power supply as a stable DC low voltage, and different output ports output different voltage values.

[0023] Since the first output end of the DC-DC module 101 is connected to the input end of the first LDO module 102, and the second output end of the DC-DC module 101 is connected to the input end of the first LDO module 102, the first LDO module 102 can be in an enabled state under the voltage drive of the DC-DC module 101, and further step down the voltage input to the first output end of the DC-DC module 101 for output.

[0024] Since the input end of the second LDO module 103 is connected to the output end of the first LDO module 102, and the enable end of the second LDO module 103 is connected to the second output end of the DC-DC module 101, the second LDO module 103 can be in an enabled state under the voltage drive of the DC-DC module 101, and further compress the voltage input to the output end of the first LDO module 102 for output.

[0025] Since the first input end of the main control module 104 is connected to the output end of the first LDO module 102, the first LDO module 102 can supply power to the IO port of the main control module 104 through the first input end of the main control module 104, and when supplying power, the first LDO module 102 needs to be in an enabled state.

[0026] The second input end of the main control module 104 is connected to the output end of the second LDO module 103, so that the second LDO module 103 can supply power to the core of the main control module 104 through the second input end of the main control module 104, and when supplying power, the first LDO module 102 and the second LDO module 103 need to be in an enabled state together.

[0027] Thus, the IO port of the main control module 104 is powered by the first LDO module 102, while the core of the main control module 104 is powered by the second LDO module 103, and whether the first LDO module 102 and the second LDO module 103 are in an enabled state is completely controlled by the DC-DC module 101, so that when the first LDO module 102 is in an enabled state and supplies power to the IO port of the main control module 104, it is also necessary to control whether the second LDO module 103 is in an enabled state through the DC-DC module 101 to control whether the second LDO module 103 supplies power to the core of the main control module 104. That is to say, when the first LDO module 102 is in an enabled state, the first LDO module 102 can supply power to the IO port of the main control module 104 and the input end of the second LDO module 103; conversely, when the first LDO module 102 is in a shut-down state, the first LDO module 102 cannot supply power to the IO port of the main control module 104 and the input end of the second LDO module 103; further, when the second LDO module 103 is also in an enabled state, the second LDO module 103 can supply power to the core of the main control module 104; conversely, when the LDO module is in a shut-down state, the second LDO module 103 cannot supply power to the core of the main control module 104.

[0028] Therefore, the chip power supply circuit in the present application can protect the core power supply of the main control module 104104 during the power supply process, so that the core will not be affected by the power supply of the IO port, and effectively solves the problem in the prior art that when the IO port of the main control module 104 leaks electricity to the second LDO module 103, the second LDO module 103 will be in a partially enabled state, thereby avoiding the core of the main control module 104 from being in a partially working state and failing to initialize correctly, thereby improving the safety and reliability of the chip power supply circuit.

[0029] In some embodiments, the voltage of the external input power source connected to the DC-DC module 101 is 12V, and is converted into a DC voltage output of 5.2V and 5V through an internal step-down circuit. The 5.2V DC voltage is output from the first output terminal of the DC-DC module 101 to the input terminal of the first LDO module 102 to power the first LDO module 102. The 5V DC voltage is output from the second output terminal of the DC-DC module 101 to the enable terminals of the first LDO module 102 and the second LDO module 103, providing an enable signal for the first LDO module 102 and the second LDO module 103, so that the first LDO module 102 can, in the enabled state, convert the input 5.2V DC voltage into 3.3V and output it to the first input terminal of the main control module 104 to power the IO port of the main control module 104; at the same time, the first LDO module 102 can also output the converted 3.3V DC voltage to the input terminal of the second LDO module 103, so that the first LDO module 102 can, in the enabled state, further convert the 3.3V DC voltage into 1.5V and output it to the second input terminal of the main control module 104 to power the core of the main control module 104.

[0030] Specifically, the DC-DC module 101 is configured as an LTM4644 chip, the first LDO module 102 and the second LDO module 103 are configured as LT3033 chips, and the main control module 104 is configured as an A3P1000 chip.

[0031] It should be noted that the reference environment of the above chip protection circuit includes but is not limited to FLASH type FPGA chip.

[0032] A second aspect of the present application provides a chip, which includes any one of the chip protection circuits described above.

[0033] The corresponding embodiments of the chip of the embodiment of the present application are similar to the specific embodiments of the power supply circuit of the embodiment of the present application. Please refer to the description of the power supply circuit part for details. In order to reduce redundancy, it will not be repeated here.

[0034] A third aspect of the present application provides an electronic device, which includes the chip protection circuit and chip described in any one of the above items.

[0035] The corresponding embodiments of the electronics in the embodiment of the present application are similar to the specific embodiments of the power supply circuit in the embodiment of the present application. Please refer to the description of the power supply circuit for details. In order to reduce redundancy, they will not be repeated here.

[0036] In summary, the present application provides a chip power supply circuit, a chip and an electronic device, wherein the chip power supply circuit comprises a DC-DC module 101, a first LDO module 102, a second LDO module 103 and a main control module 104. The first output end of the DC-DC module 101 is connected to the input end of the first LDO module 102, the output end of the first LDO module 102 is respectively connected to the first input end of the main control module 104 and the input end of the second LDO module 103, and the output end of the second LDO module 103 is connected to the second input end of the main control module 104; the second output end of the DC-DC module 101 is respectively connected to the enable ends of the first LDO module 102 and the second LDO module 103. By using the DC-DC module 101 to control whether the first LDO module 102 and the second LDO module 103 are in an enabled state, whether the first LDO module 102 supplies power to the IO port of the main control module 104, and whether the second LDO module 103 supplies power to the core of the main control module 104, power supply protection for the core of the main control module 104 is achieved during the power supply process, and the use safety and reliability of the chip power supply circuit are effectively improved.

[0037] In the description of the aforementioned embodiments, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Claims

1. A chip power supply circuit, characterized in that: The power supply circuit includes a DC-DC module, a first LDO module, a second LDO module and a main control module, wherein a first output end of the DC-DC module is connected to an input end of the first LDO module, an output end of the first LDO module is respectively connected to a first input end of the main control module and an input end of the second LDO module, and an output end of the second LDO module is connected to a second input end of the main control module; and a second output end of the DC-DC module is respectively connected to enable ends of the first LDO module and the second LDO module, so that the first LDO module is in an enabled state and can supply power to an IO port of the main control module and the second LDO module, and the second LDO module is in an enabled state and can supply power to a core of the main control module.

2. The chip power supply circuit according to claim 1, characterized in that: The voltage of the external input power supply connected to the DC-DC module is 12V, and is converted into a 5.2V voltage through an internal step-down circuit to power the first LDO module, and is converted into a 5V voltage to provide an enable signal for the first LDO module and the second LDO module; the first LDO module converts the input 5.2V voltage into a 3.3V voltage to power the second LDO module and the IO port of the main control module; the second LDO module converts the input 3.3V voltage into a 1.5V voltage to power the core of the main control module.

3. The chip power supply circuit according to claim 1, characterized in that: The DC-DC module is configured as an LTM4644 chip, the first LDO module and the second LDO module are configured as LT3033 chips, and the main control module is configured as an A3P1000 chip.

4. A chip, characterized in that: The chip comprises the chip power supply circuit according to any one of claims 1 to 3.

5. An electronic device, characterized in that: The electronic device comprises the chip according to claim 4.

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