Quantum chip test circuit, layout structure, quantum chip and quantum computer
By introducing synthetic signals and signal reflection ports into the quantum chip test line, the design layout pressure problem caused by the increase in the number of ports in the quantum chip test line is solved, and the effect of reducing the number of ports is achieved, reducing the layout difficulty of quantum chips is reduced.
Patent Information
- Application Number
- CN202420357988.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-02-27
- Publication Date
- 2025-02-14
- Estimated Expiration
- 2034-02-27
AI Technical Summary
With the increase in the number of qubits, the number of control lines and read buses in the test lines of quantum chips has increased rapidly, resulting in a sharp increase in the number of external connection ports, resulting in huge pressure on chip design and layout, making it difficult to effectively reduce the number of ports.
A quantum chip test line is proposed, which inputs a synthetic signal (including XY signal, Z signal and read input signal) through the signal input port, and outputs the output signal through the signal output port, and uses the signal reflection port to reflect the output signal. Implement the read operation of the qubit unit to reduce the number of ports required during the measurement process.
Through this solution, the test of quantum chips is completed by using only the signal input port and the signal output port, which greatly reduces the number of ports required during the measurement process and reduces the difficulty of layout of superconducting quantum chips.
Smart Images
Figure CN222483380U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of quantum chips, in particular to a quantum chip test circuit, a layout structure, a quantum chip and a quantum computer. Background Art
[0002] The current test circuit of superconducting quantum chips is basically: one bit is configured with an X control line, a Z control line, and a read resonant cavity, and multiple read resonant cavities are inductively coupled or capacitively coupled to the same read bus. Each read bus is equipped with two ports, corresponding to the signal input port and the signal output port respectively.
[0003] As the number of quantum bits increases, the number of control lines and read buses for quantum bits gradually increases, and the corresponding number of external connection ports also increases dramatically. Under limited chip processing and packaging processing conditions, the design and layout of quantum chips are under tremendous pressure.
[0004] Therefore, reducing the number of ports required for quantum chip testing is an urgent problem to be solved. Utility Model Content
[0005] The purpose of the utility model is to provide a quantum chip test circuit, a layout structure, a quantum chip and a quantum computer to solve the deficiencies in the prior art, and it can reduce the number of ports required in quantum chip testing.
[0006] The solution of this application example is implemented through the following contents.
[0007] In a first aspect, an example of the present application proposes a quantum chip test circuit, including a quantum bit unit, wherein the quantum bit unit is coupled to a read bus and a signal transmission line, respectively, wherein the signal transmission line includes a signal input port provided by one end and a ground port provided by the other end, and the read bus includes a signal output port provided by one end and a signal reflection port provided by the other end;
[0008] The signal input port is used to input a composite signal to the quantum bit unit, wherein the composite signal includes an XY signal, a Z signal, and a read input signal for performing a read operation on the quantum bit unit;
[0009] The signal reflection port is used to reflect the read output signal fed back by the quantum bit unit to the signal output port, and the signal output port is used to output the read output signal.
[0010] According to some examples of the present application, the signal reflection port is open-circuited or short-circuited to the ground.
[0011] According to some examples of the present application, the quantum chip test circuit further includes:
[0012] A signal synthesizer is connected to the signal input port and is used to synthesize the XY signal, the Z signal and the read input signal which are independently provided into the synthesized signal.
[0013] According to some examples of the present application, the quantum chip test circuit further includes a vector network analyzer;
[0014] The vector network analyzer comprises:
[0015] An output terminal, connected to the signal synthesizer, for generating the XY signal, the Z signal and the read input signal;
[0016] The input end is connected to the signal output port and is used to obtain the test result according to the read output signal.
[0017] According to some examples of the present application, the quantum chip test circuit further includes a low noise amplifier;
[0018] The low noise amplifier is connected to the input end and the signal output port respectively, and is used for amplifying the read output signal and outputting the amplified read output signal to the input end.
[0019] According to some examples of the present application, the coupling mode between the read bus and the quantum bit unit is capacitive coupling or inductive coupling;
[0020] The coupling mode between the signal transmission line and the quantum bit unit is inductive coupling, or inductive coupling and capacitive coupling.
[0021] According to some examples of the present application, the quantum chip test circuit includes a plurality of the quantum bit units, a plurality of the signal transmission lines and a read bus;
[0022] Each of the quantum bit units is connected to a corresponding signal transmission line, and all of the quantum bit units are connected to the read bus.
[0023] In a second aspect, the examples of the present application propose a layout structure, such as the quantum chip test circuit described in the first aspect.
[0024] In a third aspect, an example of the present application proposes a quantum chip, comprising: a quantum chip test circuit as described in the first aspect, wherein the quantum chip test circuit is made using the layout structure described in the second aspect.
[0025] In a fourth aspect, an example of the present application proposes a quantum computer, comprising the quantum chip described in the third aspect.
[0026] In the quantum chip test circuit of the aforementioned example of the present application, a composite signal including an XY signal, a Z signal and a read input signal is input to the quantum bit unit through the signal input port, and a read operation can be performed on the quantum bit unit, and the signal output port outputs the read output signal fed back by the quantum bit unit. Therefore, in the process of measuring the quantum chip, it is only necessary to use the signal input port to input the composite signal and use the signal output port to output the read output signal, which greatly reduces the number of ports required in the measurement process and reduces the difficulty of superconducting quantum chip layout.
[0027] A layout structure, a quantum chip and a quantum computer provided by the utility model have the same beneficial effects, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] For a clearer explanation, the following briefly introduces the drawings required for the description.
[0029] Figure 1 This is a block diagram of the quantum chip test circuit structure in an example of this application;
[0030] Figure 2 This is a block diagram of the quantum chip test circuit structure in another example of this application;
[0031] Figure 3 A graph showing a read output signal output by a quantum bit test circuit in an example of the present application.
[0032] Figure Number:
[0033] Quantum bit unit 100; quantum bit 110; resonant cavity 120; read bus 200; signal output port 210; signal reflection port 220; signal transmission line 300; signal input port 310; ground port 320; signal synthesizer 400; low noise amplifier 500. DETAILED DESCRIPTION
[0034] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application. The embodiments described below with reference to the drawings are exemplary and are only used to explain the present application, and cannot be interpreted as limitations on the present application.
[0035] In the description of the present invention, it should be understood that the terms "center", "up", "down", "left", "right", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present invention.
[0036] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present utility model, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.
[0037] The current test circuit of superconducting quantum chips is basically: one bit is configured with an X control line, a Z control line, and a read resonant cavity, and multiple read resonant cavities are inductively coupled or capacitively coupled to the same read bus. Each read bus is equipped with two ports, corresponding to the signal input port and the signal output port respectively.
[0038] In the prior art, the quantum state of a quantum bit in a superconducting quantum chip is usually obtained by inferring the state of the resonant cavity coupled to the quantum bit. As long as there is a suitable coupling strength between the (read) resonant cavity and the corresponding quantum bit, the quantum state of the quantum bit can be read in engineering by detecting the operating frequency of the (read) resonant cavity. In the superconducting quantum chip testing process, XY control signals and Z control signals are applied to the quantum bit through the XY control line and the Z control line. For each read bus, the test signal is input to the signal input end of the read bus, and then the read output signal is obtained from the signal output port. Therefore, in the existing testing technology, for quantum chips, XY control signal and Z control signal input ports, test signal input ports, and output signal ports are required. As the number of quantum bits increases, the number of read buses for quantum bits gradually increases, and the corresponding number of external connection ports also increases dramatically. Under limited chip processing and packaging processing conditions, the design layout of quantum chips is under tremendous pressure.
[0039] Based on this, Figure 1As shown, in one embodiment of the present invention, a quantum chip test circuit is provided, including a quantum bit unit 100, the quantum bit unit 100 is coupled to a read bus 200 and a signal transmission line 300, respectively, the signal transmission line 300 includes a signal input port 310 provided by one end and a ground port 320 provided by the other end, and the read bus 200 includes a signal output port 210 provided by one end and a signal reflection port 220 provided by the other end;
[0040] The signal input port 310 is used to input a composite signal to the quantum bit unit 100, where the composite signal includes an XY signal, a Z signal, and a read input signal for performing a read operation on the quantum bit unit 100;
[0041] The signal reflection port 220 is used to reflect the read output signal fed back by the quantum bit unit 100 to the signal output port 210 , and the signal output port 210 is used to output the read output signal.
[0042] Among them, the Z signal is a current signal, and the signal transmission line needs to be set in the circuit loop. Therefore, the other end of the signal transmission line needs to be set as a ground port to ensure that the Z signal can be transmitted normally.
[0043] Specifically, during the operation of the quantum chip test circuit, the composite signal including the XY signal, the Z signal and the read input signal is first transmitted to the quantum bit unit 100 through the signal transmission line 300. The XY signal and the Z signal can enable the quantum bit 110 to operate normally, and the read input signal can read the operating frequency of the resonant cavity 120 coupled to the quantum bit 110. After receiving the read input signal, the quantum bit 110 transmits the read output signal to the read bus 200, and the signal reflection port 220 of the read bus 200 totally reflects the read output signal to the signal output port 210. The read output signal curve is generated by obtaining the read output signal output from the signal output port 210 (wherein the read output signal curve is composed of the read output signal intensity magnitude and the read output signal frequency, and the curve can be directly generated by the read output signal output from the signal output port 210), and the quantum state of the quantum bit 110 is read.
[0044] In the quantum chip test circuit provided in the present application, it is only necessary to input a composite signal including an XY signal, a Z signal and a read input signal through the signal input port 310 of the signal transmission line 300, and obtain a read output signal through the signal output port 210 of the read bus 200, so as to complete the test of the quantum chip. In the above-mentioned quantum chip test circuit, only the signal input port 310 and the signal output port 210 need to be used. Compared with the prior art, which needs to use the XY control signal input port, the Z control signal input port and the two ports of the read bus during the test, the signal input port in the test circuit provided in the present application integrates the functions of the XY control signal input port, the Z control signal input port and the read bus read input signal port in the prior art, and completes the corresponding functions of the above three ports through one port, which greatly reduces the number of ports required in the measurement process and reduces the difficulty of layout of the superconducting quantum chip.
[0045] In one embodiment of the present application, the signal reflection port 220 is open-circuited or short-circuited to the ground.
[0046] Specifically, when the read output signal fed back by the quantum bit unit 100 is transmitted to the signal reflection port 220 on the read bus 200, it will be completely reflected to the signal output port 210. Since in a lossless transmission line, when the terminal is short-circuited or open-circuited, the electromagnetic wave reaching the terminal of the transmission line cannot be absorbed and will be completely reflected out, therefore, in the embodiment of the present application, the signal reflection port 220 is set to be open-circuited or short-circuited to the ground, so as to achieve the effect of reflecting all the read output signals to the signal output port 210, so as to ensure that the signal output port 210 can output all the read output signals.
[0047] In one embodiment of the present application, the quantum chip test circuit further includes:
[0048] The signal synthesizer 400 is connected to the signal input port 310 and is used to synthesize the XY signal, the Z signal and the read input signal which are independently provided into a synthesized signal.
[0049] In one embodiment of the present application, the quantum chip test circuit further includes a vector network analyzer;
[0050] Vector Network Analyzer includes:
[0051] An output terminal connected to the signal synthesizer 400, used to generate XY signals, Z signals and read input signals;
[0052] The input end is connected to the signal output port 210 and is used to obtain the test result according to the read output signal.
[0053] Specifically, Figure 2As shown, a vector network analyzer (not shown) generates independent XY signals, Z signals and a read input signal for performing a read operation on the quantum bit unit 100 and transmits them to the signal synthesizer 400. The signal synthesizer 400 synthesizes the XY signals, Z signals and the read input signal into a synthesized signal and transmits it to the quantum bit unit 100 via the signal transmission line 300.
[0054] It should be noted that in order to transmit the Z (low frequency) signal to the qubit unit 100 through the signal transmission line 300, the coupling mode between the signal transmission line 300 and the qubit unit 100 needs to be set to inductive coupling, or a combination of inductive coupling and capacitive coupling. The coupling mode between the signal transmission line 300 and the qubit unit 100 can be selected according to actual needs.
[0055] Furthermore, if the frequency of the read input signal is the same as the operating frequency of the resonant cavity 120 of the quantum bit 110, the read input signal will be coupled into the resonant cavity 120 to form resonance; if the frequency of the read input signal is different from the operating frequency of the resonant cavity 120, the read input signal will not be able to enter the resonant cavity 120. Based on this, the operating frequency corresponding to the resonant cavity 120 can be determined by the position of the peak or trough in the read output signal curve graph output by the signal output port 210, so as to determine the quantum state of the quantum bit 110 according to the operating frequency of the resonant cavity 120. In one embodiment of the present application, the curve graph of the read output signal output by the signal output port 210 is as follows: Figure 3 As shown, the horizontal axis represents the frequency of the read output signal, and the vertical axis represents the magnitude of the read output signal intensity (it should be noted that the magnitude in the figure is only for illustration, not the intensity during actual testing), and the frequency corresponding to the peak or trough in the figure represents the operating frequency of the six resonant cavities 120. Based on the quantum chip test circuit described in the present application, it is only necessary to use the signal input end for synthesized signal input and the signal output port 210 for read output signal output, thereby reducing the number of ports required for measurement and reducing the difficulty of superconducting quantum chip layout.
[0056] In one embodiment of the present application, the quantum chip test circuit further includes a low noise amplifier 500;
[0057] The low noise amplifier 500 is connected to the input terminal and the signal output port 210 respectively, and is used to amplify the read output signal and output the amplified read output signal to the input terminal of the vector network analyzer.
[0058] Specifically, the low noise amplifier 500 is respectively connected to the input port of the vector network analyzer and the signal output port 210 of the read bus 200 , and can amplify the read output signal while reducing noise interference, which is beneficial for the vector network analyzer to accurately read the quantum state of the quantum bit 110 .
[0059] In one embodiment of the present application, the coupling mode between the read bus 200 and the quantum bit unit 100 is capacitive coupling or inductive coupling.
[0060] It should be noted that the coupling method between the read bus 200 and the quantum bit 110 can be selected according to actual needs.
[0061] In one embodiment of the present application, a quantum chip test circuit includes a plurality of quantum bit units 100, a plurality of signal transmission lines 300, and a read bus 200;
[0062] Each quantum bit unit 100 is connected to a corresponding signal transmission line 300 , and all quantum bit units 100 are connected to a read bus 200 .
[0063] Furthermore, the quantum chip test circuit includes multiple read buses 200, each read bus 200 is coupled to multiple quantum bit units 100, each quantum bit unit 100 is coupled to its corresponding signal transmission line 300, and there is a one-to-one correspondence between the quantum bit unit 100 and the signal transmission line 300.
[0064] In one embodiment of the present application, the utility model provides a layout structure, including: the quantum chip test circuit as above.
[0065] In one embodiment of the present application, the utility model provides a quantum chip, including: the quantum chip test circuit as above, wherein the quantum chip test circuit is made using the above-mentioned layout structure.
[0066] In one embodiment of the present application, the utility model provides a quantum computer, comprising the above-mentioned quantum chip.
[0067] Regarding the technical effects of the layout structure, quantum chip and quantum computer of the above-mentioned embodiments, reference can be made to other embodiments of this specification for comparative explanation and no further details will be given here.
[0068] In the description of this specification, the description with reference to the terms "some embodiments" or "examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.
[0069] The above are only preferred embodiments of the present invention and do not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, may make any equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which shall be deemed as the content of the technical solution of the present invention and still fall within the protection scope of the present invention.
Claims
1. A quantum chip test circuit, characterized in that: The qubit unit comprises a qubit unit, wherein the qubit unit is coupled to a read bus and a signal transmission line, respectively, wherein the signal transmission line comprises a signal input port provided by one end and a ground port provided by the other end, and the read bus comprises a signal output port provided by one end and a signal reflection port provided by the other end; The signal input port is used to input a composite signal to the quantum bit unit, wherein the composite signal includes an XY signal, a Z signal, and a read input signal for performing a read operation on the quantum bit unit; The signal reflection port is used to reflect the read output signal fed back by the quantum bit unit to the signal output port, and the signal output port is used to output the read output signal.
2. The quantum chip test circuit according to claim 1, characterized in that: The signal reflection port is open-circuited or short-circuited to the ground.
3. The quantum chip test circuit according to claim 1, characterized in that: The quantum chip test circuit also includes: A signal synthesizer is connected to the signal input port and is used to synthesize the XY signal, the Z signal and the read input signal which are independently provided into the synthesized signal.
4. The quantum chip test circuit according to claim 3, characterized in that: The quantum chip test circuit also includes a vector network analyzer; The vector network analyzer comprises: An output terminal, connected to the signal synthesizer, for generating the XY signal, the Z signal and the read input signal; The input end is connected to the signal output port and is used to obtain the test result according to the read output signal.
5. The quantum chip test circuit according to claim 4, characterized in that: The quantum chip test circuit also includes a low noise amplifier; The low noise amplifier is connected to the input end and the signal output port respectively, and is used for amplifying the read output signal and outputting the amplified read output signal to the input end.
6. The quantum chip test circuit according to claim 1, characterized in that: The coupling mode between the read bus and the quantum bit unit is capacitive coupling or inductive coupling; The coupling mode between the signal transmission line and the quantum bit unit is inductive coupling, or inductive coupling and capacitive coupling.
7. The quantum chip test circuit according to claim 1, characterized in that: The quantum chip test circuit includes a plurality of the quantum bit units, a plurality of the signal transmission lines and a read bus; Each of the quantum bit units is connected to a corresponding signal transmission line, and all of the quantum bit units are connected to the read bus.
8. A layout structure, characterized in that: include: A quantum chip test circuit as described in any one of claims 1 to 7.
9. A quantum chip, characterized in that: include: The quantum chip test circuit according to any one of claims 1 to 7, wherein the quantum chip test circuit is made using the layout structure according to claim 8.
10. A quantum computer, characterized in that: Comprising the quantum chip as described in claim 9.