Signal distribution circuit and distributor capable of adaptively adjusting gain

Abstract

The utility model discloses a signal distribution circuit and distributor capable of adaptively adjusting gain, the circuit comprises a first switching processing module, a second switching processing module and a signal output module, the first switching processing module is used for receiving a target input signal transmitted by a signal input module, and the second switching processing module is used for outputting the target input signal; the first switching processing module is used for receiving a target input signal and executing a first target processing operation on the target input signal to obtain a first target signal and transmitting the first target signal to the second switching processing module, and the second switching processing module is used for executing a second target processing operation on the first target signal to obtain a second target signal and transmitting the second target signal to the signal output module; and the signal output module is used for transmitting the received second target signal to preset target equipment. According to the utility model, the quality and the adaptive adjustment capability of the output signal can be improved, and the distribution output capability and the output definition of the HDMI signal can be improved, thereby facilitating the improvement of the user experience.

Description

Technical Field

[0001] The utility model relates to the technical field of distributors, in particular to a signal distribution circuit and a distributor for adaptively adjusting gain. Background Art

[0002] With the continuous development of science and technology, digital electronic devices have become an indispensable part of our lives today. More and more digital electronic devices use HDMI interface as the main audio and video signal transmission interface. Various signal source output devices and display devices need to be connected via HDMI cable to transmit high-quality and stable audio and video signals.

[0003] A multi-channel HDMI distributor is an electronic device that can distribute the high-definition signal generated by a high-definition signal source to multiple output display devices that support high-definition signals. At present, the multi-channel HDMI distributors on the market do not process the output signals. If the HDMI versions and resolutions of different display devices used by the user end are inconsistent, only the lowest resolution can be output, which cannot provide users with a high-definition, high-quality visual experience. In addition, the multi-channel HDMI distributors on the market have fewer output ports, and the output clarity supported by the ports is low, resulting in poor user experience. Therefore, it is particularly important to propose a new signal distribution circuit to improve the distribution and output capacity of HDMI signals, increase the output clarity, and increase the number of output ports, thereby improving the user experience. Utility Model Content

[0004] The utility model provides a signal distribution circuit and distributor with adaptive gain adjustment, which can improve the distribution output capability and output clarity of HDMI signals and increase the number of output ports.

[0005] In order to solve the above technical problems, the utility model discloses a signal distribution circuit for adaptively adjusting gain in the first aspect, characterized in that the circuit comprises a first switching processing module, a second switching processing module and a signal output module, wherein:

[0006] The first end of the first switching processing module is used to electrically connect to the signal input module, the second end of the first switching processing module is electrically connected to the first end of the second switching processing module, and the second end of the second switching processing module is electrically connected to the first end of the signal output module;

[0007] The first switching processing module is used to receive the target input signal transmitted by the signal input module, perform a first target processing operation on the target input signal, obtain a first target signal, and transmit the first target signal to the second switching processing module;

[0008] The second switching processing module is used to perform a second target processing operation on the first target signal to obtain a second target signal and transmit the second target signal to the signal output module;

[0009] The signal output module is used to transmit the received second target signal to a preset target device.

[0010] As an optional implementation, in the first aspect of the utility model, the circuit further includes a signal processing module, wherein:

[0011] The first end of the signal processing module is used to be electrically connected to the signal input module, and the second end of the signal processing module is electrically connected to the first end of the first switching processing module;

[0012] The signal processing module is used to receive the target input signal transmitted by the signal input module, perform signal processing operations on the target input signal, obtain the target input signal after signal processing, and transmit the target input signal after signal processing to the first switching processing module.

[0013] As an optional implementation, in the first aspect of the utility model, the circuit further includes a control module, wherein:

[0014] The first end of the control module is electrically connected to the third end of the first switching processing module, and the second end of the control module is electrically connected to the third end of the second switching processing module;

[0015] The control module is used to manage the working modes of the first switching processing module, the second switching processing module and the signal processing module.

[0016] As an optional implementation, in the first aspect of the utility model, the first switching processing module includes a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit and a first P_MODE circuit, wherein:

[0017] A first end of the first processing chip is electrically connected to a second end of the signal processing module, a second end of the first processing chip is electrically connected to a first end of the second switching processing module, a third end of the first processing chip is electrically connected to a first end of the control module, a fourth end of the first processing chip is electrically connected to a first end of the first JTAG circuit, a fifth end of the first processing chip is electrically connected to a first end of the first I2C circuit, a sixth end of the first processing chip is electrically connected to a first end of the first QSPI circuit, and a seventh end of the first processing chip is electrically connected to a first end of the first P_MODE circuit.

[0018] As an optional implementation, in the first aspect of the utility model, the second switching processing module includes a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second P_MODE circuit and an AUDIO circuit, wherein:

[0019] A first end of the second processing chip is electrically connected to a second end of the first switching processing module, a second end of the second processing chip is electrically connected to a first end of the signal output module, a third end of the second processing chip is electrically connected to a second end of the control module, a fourth end of the second processing chip is electrically connected to a first end of the second JTAG circuit, a fifth end of the second processing chip is electrically connected to a first end of the second I2C circuit, a sixth end of the second processing chip is electrically connected to a first end of the second QSPI circuit, a seventh end of the second processing chip is electrically connected to a first end of the second P_MODE circuit, and an eighth end of the second processing chip is electrically connected to a first end of the AUDIO circuit.

[0020] As an optional implementation, in the first aspect of the utility model, the control module includes a control chip and an EDID dialing circuit, wherein:

[0021] The first end of the control chip is electrically connected to the third end of the first switching processing module, the second end of the control chip is electrically connected to the third end of the second switching processing module, and the third end of the control chip is electrically connected to the first end of the EDID dialing circuit;

[0022] The EDID dial circuit is used to control the signal format of the second target signal output by the signal output module.

[0023] As an optional implementation, in the first aspect of the utility model, the circuit further includes the signal input module, the signal input module includes a target input chip, an input ESD processing circuit, an input DDC processing circuit and an input HPD processing circuit, wherein:

[0024] The first end of the target input chip is electrically connected to the first end of the signal processing module, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

[0025] As an optional implementation, in the first aspect of the utility model, the signal output module includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit and a current limiting protection circuit, wherein:

[0026] The first end of the target output chip is electrically connected to the second end of the second switching processing module, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output chip is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output chip is electrically connected to the first end of the current limiting protection circuit.

[0027] As an optional implementation, in the first aspect of the utility model, the signal processing module includes a signal processing chip, wherein:

[0028] The first end of the signal processing chip is electrically connected to the first end of the signal input module, and the second end of the signal processing chip is electrically connected to the first end of the first switching processing module.

[0029] The first aspect of the utility model discloses a distributor, which includes an input port for receiving an HDMI signal, a signal distribution circuit for adaptively adjusting gain as disclosed in the first aspect of the utility model, and an output port for outputting a second target signal.

[0030] Compared with the prior art, the implementation of the utility model has the following beneficial effects:

[0031] The implementation of the utility model can perform corresponding adaptive gain adjustment operations on the input HDMI signal through two switching processing modules, improve the quality and adaptive adjustment capability of the output signal, and can convert one-channel HDMI video signal input into multiple-channel HDMI video signal output, and can realize multiple-channel 8K video signal output, improve the distribution output capability and output clarity of the HDMI signal, which is beneficial to improving the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 It is a structural schematic diagram of a signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0034] Figure 2 It is a structural schematic diagram of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0035] Figure 3It is a structural schematic diagram of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0036] Figure 4 It is a structural schematic diagram of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model;

[0037] Figure 5 It is a structural schematic diagram of an LED indication circuit disclosed in an embodiment of the utility model;

[0038] Figure 6 It is a structural schematic diagram of a first processing chip disclosed in an embodiment of the utility model;

[0039] Figure 7 It is a structural schematic diagram of a first JTAG circuit disclosed in an embodiment of the utility model;

[0040] Figure 8 It is a structural schematic diagram of a first I2C circuit disclosed in an embodiment of the utility model;

[0041] Fig. 9 It is a structural schematic diagram of a first QSPI circuit disclosed in an embodiment of the utility model;

[0042] Fig.10 It is a structural schematic diagram of a first P_MODE circuit disclosed in an embodiment of the utility model;

[0043] Fig.11 It is a structural schematic diagram of a second processing chip disclosed in an embodiment of the utility model;

[0044] Fig.12 It is a structural schematic diagram of a second JTAG circuit disclosed in an embodiment of the utility model;

[0045] Fig.13 It is a structural schematic diagram of a second I2C circuit disclosed in an embodiment of the utility model;

[0046] Fig.14 It is a structural schematic diagram of a second QSPI circuit disclosed in an embodiment of the utility model;

[0047] Fig.15 It is a structural schematic diagram of a second P_MODE circuit disclosed in an embodiment of the utility model;

[0048] Fig.16 It is a structural schematic diagram of an AUDIO circuit disclosed in an embodiment of the utility model;

[0049] Fig.17 It is a structural schematic diagram of a control chip disclosed in an embodiment of the utility model;

[0050] Fig.18 It is a structural schematic diagram of an EDID dial code circuit disclosed in an embodiment of the utility model;

[0051] Fig.19 It is a schematic diagram of the structure of a target input chip disclosed in an embodiment of the utility model;

[0052] Fig. 20 It is a structural schematic diagram of an input ESD processing circuit disclosed in an embodiment of the utility model;

[0053] Fig.21 It is a structural schematic diagram of an input DDC processing circuit disclosed in an embodiment of the utility model;

[0054] Fig. 22 It is a structural schematic diagram of an input HPD processing circuit disclosed in an embodiment of the utility model;

[0055] Fig.23 It is a schematic diagram of the structure of a target output chip disclosed in an embodiment of the utility model;

[0056] Fig.24 It is a structural schematic diagram of an output ESD processing circuit disclosed in an embodiment of the utility model;

[0057] Fig.25 It is a structural schematic diagram of an output DDC processing circuit disclosed in an embodiment of the utility model;

[0058] Fig.26 It is a structural schematic diagram of an output HPD processing circuit disclosed in an embodiment of the utility model;

[0059] Fig. 27 It is a structural schematic diagram of a current limiting protection circuit disclosed in an embodiment of the utility model;

[0060] Fig.28 It is a structural schematic diagram of a signal processing chip disclosed in an embodiment of the utility model;

[0061] Fig.29 It is a structural schematic diagram of a dispenser disclosed in an embodiment of the utility model. DETAILED DESCRIPTION

[0062] For better understanding and implementation, the technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] It should be noted that, unless otherwise clearly specified and limited, the term "electrical connection" in the specification and claims of the utility model and the above-mentioned drawings should be understood in a broad sense. For example, it can be a fixed electrical connection, a detachable electrical connection, or an integral electrical connection; it can be a mechanical electrical connection, an electrical electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, the terms "first", "second", etc. in the specification and claims of the utility model and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. The terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For those of ordinary skill in the art, the specific meanings of the above terms in the utility model can be understood according to specific circumstances.

[0064] The utility model discloses a signal distribution circuit and distributor with adaptive gain adjustment, which can improve the quality and adaptive adjustment capability of output signals, improve the distribution output capability and output clarity of HDMI signals, and thus help improve user experience. Detailed descriptions are given below.

[0065] Embodiment 1

[0066] See also Figure 1 , Figure 1 : is a schematic diagram of a signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model. Figure 1 The signal distribution circuit for adaptively adjusting gain shown can not only adaptively adjust gain to improve the quality of output signals, but also output multiple channels of high-resolution HDMI signals and support EDID management functions of HDMI signals, which is not limited in the embodiments of the present utility model. Figure 1 As shown, the signal distribution circuit for adaptively adjusting the gain may include a first switching processing module 101, a second switching processing module 102 and a signal output module 103, wherein:

[0067] The first end of the first switching processing module 101 is used to electrically connect to the signal input module 104, the second end of the first switching processing module 101 is electrically connected to the first end of the second switching processing module 102, and the second end of the second switching processing module 102 is electrically connected to the first end of the signal output module 103;

[0068] The first switching processing module 101 is used to receive the target input signal transmitted by the signal input module 104, perform a first target processing operation on the target input signal, obtain a first target signal and transmit the first target signal to the second switching processing module 102;

[0069] The second switching processing module 102 is used to perform a second target processing operation on the first target signal to obtain a second target signal and transmit the second target signal to the signal output module 103;

[0070] The signal output module 103 is used to transmit the received second target signal to a preset target device.

[0071] In the embodiment of the utility model, optionally, the first switching processing module 101 may include a one-input and two-output video switching processing module, wherein the one-input and two-output video switching processing module may include a GSV6502 chip with equalizer gain control and adaptive gain adjustment, and the first switching processing module 101 may be used to connect one HDMI input signal, that is, the target input signal received by the first switching processing module 101 may include one HDMI input signal, and perform a first target processing operation on the received one HDMI input signal to obtain a first target signal, and the first target signal may include two HDMI signals that are the same as the received one HDMI input signal. Further, the first target processing operation may include a gain adjustment operation, and may also include an input signal one-input and two-output projection operation.

[0072] In the embodiment of the utility model, optionally, the second switching processing module 102 may include a one-input four-output video switching processing module, wherein the one-input four-output video switching processing module may include a GSV6505 chip with equalizer gain control and adaptive gain adjustment and peripheral circuits. Further optionally, the signal distribution circuit for adaptive gain adjustment may include multiple identical second switching processing modules 102, such as Figure 2 As shown, Figure 2 It is a structural schematic diagram of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model. Among them, two second switching processing modules 102 are used to process two HDMI signals output by the first switching processing module 101 respectively, that is, one second switching processing module 102 is connected to one HDMI signal output by the first switching processing module 101, and performs a second target processing operation on the HDMI signal to obtain four output HDMI signals, and another second switching processing module 102 is connected to another HDMI signal output by the first switching processing module 101, and performs a second target processing operation on the HDMI signal to obtain four output HDMI signals. Further, the second target processing operation may include a gain adjustment operation, and may also include a one-input and four-output projection operation of the input signal.

[0073] In an embodiment of the utility model, optionally, the preset target device may include a smart phone, a smart tablet, a smart computer, a smart laptop, a smart watch, a television, a monitor, a game console, or the like that can be used to display video signals and / or can be used to play sound signals.

[0074] In an embodiment of the utility model, optionally, the second target signal may include an 8K video signal.

[0075] It can be seen that the implementation Figure 1 The described signal distribution circuit for adaptively adjusting gain receives the target input signal transmitted by the signal input module through the first switching processing module, and transmits the obtained first target signal to the second switching processing module after performing the first target processing operation on the target input signal, and transmits the obtained second target signal to the signal output module through the second switching processing module, and transmits it to the target device through the signal output module. It can perform corresponding adaptive gain adjustment operations on the input HDMI signal through the two switching processing modules, improve the quality and adaptive adjustment capability of the output signal, and can convert one HDMI video signal input into multiple HDMI video signal outputs, and can realize multiple 8K video signal outputs, improve the distribution output capability and output clarity of the HDMI signal, which is beneficial to improving the user experience.

[0076] In an optional embodiment, if Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model. Figure 3 The signal distribution circuit for adaptively adjusting the gain shown further includes a signal processing module 105, wherein:

[0077] The first end of the signal processing module 105 is used to electrically connect to the signal input module 104, and the second end of the signal processing module 105 is electrically connected to the first end of the first switching processing module 101;

[0078] The signal processing module 105 is used to receive the target input signal transmitted by the signal input module 104, perform signal processing operations on the target input signal, obtain the target input signal after signal processing, and transmit the target input signal after signal processing to the first switching processing module 101.

[0079] In this optional embodiment, optionally, the signal processing module 105 can be composed of an HDMI2.1 video processing chip PS8419 with a Redriver and peripheral circuits. The signal processing module 105 is used to receive the target input signal transmitted by the signal input module 104, and perform a signal processing operation on the target input signal to obtain the target input signal after signal processing, and transmit the target input signal after signal processing to the first switching processing module 101, wherein the signal processing operation may include gain control of the compensating insertion loss of the target input signal transmitted by the received signal input module 104.

[0080] It can be seen that the implementation of this optional embodiment can perform gain control on the compensation insertion loss of the target input signal transmitted by the received signal input module through the signal processing module, thereby improving the quality and stability of the HDMI signal.

[0081] In another optional embodiment, Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of another signal distribution circuit for adaptively adjusting gain disclosed in an embodiment of the utility model. Figure 4 The signal distribution circuit for adaptively adjusting the gain shown also includes a control module 106, wherein:

[0082] A first end of the control module 106 is electrically connected to a third end of the first switching processing module 101 , and a second end of the control module 106 is electrically connected to a third end of the second switching processing module 102 ;

[0083] The control module 106 is used to manage the working modes of the first switching processing module 101 , the second switching processing module 102 and the signal processing module 105 .

[0084] In this optional embodiment, the control module 106 may include an MCU control chip, and the electrical connection between the control module 106 and the first switching processing module 101 may include connection through an IIC bus connection; the electrical connection between the control module 106 and the second switching processing module 102 may include connection through an IIC bus connection. Among them, IIC, also known as Inter-Integrated Circuit, is a two-wire serial bus developed by Philips for connecting microcontrollers and their peripherals. It is a synchronous, half-duplex, bidirectional two-wire serial bus consisting of two buses: a serial clock line SCL and a serial data line SDA. The SCL line is responsible for generating synchronous clock pulses, while the SDA line is responsible for transmitting serial data between devices.

[0085] In this optional embodiment, further optionally, the third end of the control module 106 is electrically connected to the first end of the LED indication circuit, wherein:

[0086] The LED indication circuit is used to indicate the access port position of the target device connected to the signal input module.

[0087] In this optional embodiment, optionally, as Figure 5 As shown, Figure 5 is a schematic diagram of a structure of an LED indicator circuit disclosed in an embodiment of the utility model, wherein the components included in the LED indicator circuit and the connection method between the components can be as follows Figure 5 shown.

[0088] In this optional embodiment, optionally, when the signal distribution circuit for adaptively adjusting gain disclosed in the embodiment of the utility model includes eight outputs, the signal input module includes eight output ports, each output port can be connected to a target device, and if the target device is connected to the second output port, the LED indicator corresponding to the second output port lights up to indicate that the second output port is connected to the target device.

[0089] In this optional embodiment, the control module 106 is optionally used to simultaneously manage the working modes of the first switching processing module 101 , the second switching processing module 102 and the signal processing module 105 .

[0090] It can be seen that the implementation of this optional embodiment can simultaneously manage the working modes of the first switching processing module, the second switching processing module and the signal processing module through the control module, thereby improving the automation and intelligence level of the circuit. The control module controls the first switching processing module, the second switching processing module and the signal processing module to process, map and transmit the input video signal, thereby converting one input into multiple outputs, and improving the quality and clarity of the output video signal.

[0091] In yet another optional embodiment, the first switching processing module 101 includes a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit, and a first P_MODE circuit, wherein:

[0092] The first end of the first processing chip is electrically connected to the second end of the signal processing module 105, the second end of the first processing chip is electrically connected to the first end of the second switching processing module 102, the third end of the first processing chip is electrically connected to the first end of the control module 106, the fourth end of the first processing chip is electrically connected to the first end of the first JTAG circuit, the fifth end of the first processing chip is electrically connected to the first end of the first I2C circuit, the sixth end of the first processing chip is electrically connected to the first end of the first QSPI circuit, and the seventh end of the first processing chip is electrically connected to the first end of the first P_MODE circuit.

[0093] In this optional embodiment, optionally, as Figure 6 As shown, Figure 6 is a schematic diagram of the structure of a first processing chip disclosed in an embodiment of the utility model, wherein the components included in the first processing chip and the connection method between the components can be as follows Figure 6 shown.

[0094] Further, such as Figure 7 As shown, Figure 7: is a schematic diagram of a first JTAG circuit disclosed in an embodiment of the utility model, wherein the components included in the first JTAG circuit and the connection method between the components can be as follows Figure 7 shown.

[0095] Further, such as Figure 8 As shown, Figure 8 : is a schematic diagram of a first I2C circuit disclosed in an embodiment of the utility model, wherein the components included in the first I2C circuit and the connection method between the components can be as follows: Figure 8 shown.

[0096] Further, such as Fig. 9 As shown, Fig. 9 : is a schematic diagram of the structure of a first QSPI circuit disclosed in an embodiment of the utility model, wherein the components included in the first QSPI circuit and the connection method between the components can be as follows: Fig. 9 shown.

[0097] Further, such as Fig.10 As shown, Fig.10 : is a schematic diagram of a structure of a first P_MODE circuit disclosed in an embodiment of the utility model, wherein the components included in the first P_MODE circuit and the connection method between the components can be as follows: Fig.10 shown.

[0098] In this optional embodiment, optionally, the first processing chip can map one input HDMI signal into two output HDMI signals, that is, realize one input and two outputs. The first processing chip can include a GSV6502 chip, wherein the GSV6502 is a one-input and two-output HDMI2.1 distributor. This chip integrates an enhanced microcontroller based on RISC-V and is suitable for various application scenarios that require high-quality HDMI signal processing and transmission.

[0099] In this optional embodiment, optionally, the first JTAG circuit includes a JTAG circuit, wherein the JTAG circuit is a standard test access and boundary scan circuit designed by the Joint Test Action Group. The JTAG circuit is composed of a series of hardware components, such as test data input (TDI), test data output (TDO), etc., which are connected and communicated through the JTAG interface. The main functions of the JTAG circuit include chip-level testing, boundary scanning, copyright protection, integrated circuit debugging and troubleshooting, and configuration and programming. By inserting an interface on the chip pin, JTAG can detect and diagnose chip errors, support functional testing, boundary scanning testing, and code coverage testing, and ensure the normal operation and quality control of the chip. Further, all operations of the JTAG circuit must be synchronized with the JTAG clock signal (TCK). The test controller can send test data to the test target through the JTAG interface and receive response data from the test target to verify the function and performance of the circuit. In the debug mode, the test controller can also read and modify the internal state and registers of the test target.

[0100] In this optional embodiment, optionally, the first I2C circuit includes an I2C circuit, wherein the I2C circuit, whose full name is Inter-Integrated Circuit (interconnected integrated circuit) circuit, is a hardware circuit used for short-distance data transmission between integrated circuits, and is mainly composed of two lines, SDA (data bus) and SCL (clock bus). Through these two lines, the master device can communicate with the slave device bidirectionally.

[0101] In this optional embodiment, optionally, the first QSPI circuit includes a QSPI circuit, wherein QSPI is the abbreviation of QueuedSPI, and the QSPI circuit is a dedicated communication interface circuit for connecting single, dual or quad (data lines) SPI Flash storage media; the biggest feature of the QSPI circuit is that an 80-byte RAM is used to replace the SPI's transmit and receive data registers. The 80-byte RAM is divided into three parts: a 16-word transmit RAM, a 16-word receive RAM, and a 16-byte command RAM. These three parts together form a transmission queue with 16 QSPI transmission control groups, each QSPI transmission control group containing a command RAM, a transmit RAM, and a receive RAM. The data length, chip select, and other information of each QSPI transmission can be determined separately by the command RAM of the corresponding QSPI transmission control group.

[0102] In this optional embodiment, optionally, the first P_MODE circuit includes a P_MODE circuit, which is a circuit with a specific working mode. According to different P_MODE settings, the P_MODE circuit will enter different working states. For example, when the working mode corresponding to P_MODE is 0, the P_MODE circuit is in an internal startup state; and when the working mode corresponding to P_MODE is 1, the P_MODE circuit enters a QSPI circuit startup state.

[0103] It can be seen that the implementation of this optional embodiment can process the HDMI signal input to the signal processing module through the first processing chip and output it to the second switching processing module, and through the coordinated operation of the first JTAG circuit, the first I2C circuit, the first QSPI circuit and the first P_MODE circuit, it can process one HDMI input signal into two HDMI output signals, simplify the design and wiring of the entire system, help reduce hardware complexity and cost, and at the same time be able to output multiple HDMI high-definition signals, synchronously display the same content on different devices, and improve user experience.

[0104] In yet another optional embodiment, the second switching processing module 102 includes a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second P_MODE circuit and an AUDIO circuit, wherein:

[0105] A first end of the second processing chip is electrically connected to a second end of the first switching processing module 101, a second end of the second processing chip is electrically connected to a first end of the signal output module 103, a third end of the second processing chip is electrically connected to a second end of the control module 106, a fourth end of the second processing chip is electrically connected to a first end of the second JTAG circuit, a fifth end of the second processing chip is electrically connected to a first end of the second I2C circuit, a sixth end of the second processing chip is electrically connected to a first end of the second QSPI circuit, a seventh end of the second processing chip is electrically connected to a first end of the second P_MODE circuit, and an eighth end of the second processing chip is electrically connected to a first end of the AUDIO circuit.

[0106] In this optional embodiment, optionally, as Fig.11 As shown, Fig.11 is a schematic diagram of the structure of a second processing chip disclosed in the utility model, wherein the components included in the second processing chip and the connection method between the components can be as follows Fig.11 As shown;

[0107] Further, such as Fig.12 As shown, Fig.12 The utility model discloses a second JTAG circuit structure diagram, wherein the second JTAG circuit includes components and the connection between the components can be as follows Fig.12 As shown;

[0108] Further, such as Fig.13 As shown, Fig.13 : is a schematic diagram of the structure of a second I2C circuit disclosed in the utility model, wherein the components included in the second I2C circuit and the connection method between the components can be as follows Fig.13 As shown;

[0109] Further, such as Fig.14 As shown, Fig.14 : is a schematic diagram of the structure of a second QSPI circuit disclosed in the utility model, wherein the components included in the second QSPI circuit and the connection method between the components can be as follows: Fig.14 As shown;

[0110] Further, such as Fig.15 As shown, Fig.15 : is a schematic diagram of the structure of a second P_MODE circuit disclosed in the utility model, wherein the components included in the second P_MODE circuit and the connection method between the components can be as follows: Fig.15 As shown;

[0111] Further, such as Fig.16 As shown, Fig.16 The utility model discloses a schematic diagram of the structure of an AUDIO circuit, wherein the components included in the AUDIO circuit and the connection method between the components can be as follows Fig.16 shown.

[0112] In this optional embodiment, optionally, the second processing chip can map one input HDMI signal into four output HDMI signals, that is, realize one input and four outputs. The second processing chip includes a GSV6505 chip, wherein the GSV6505 is a one-input and four-output HDMI2.1 distributor. This chip integrates an enhanced microcontroller based on RISC-V and is suitable for various application scenarios that require high-quality HDMI signal processing and transmission.

[0113] In this optional embodiment, optionally, the AUDIO circuit is mainly used to process audio signals to ensure that the audio signals can be transmitted and played clearly and accurately. The main function of the AUDIO circuit is to amplify and process the sound signals, wherein the process of AUDIO amplifying and processing the sound signals may include one or more of filtering processing, equalization processing, and reverberation processing.

[0114] In this optional embodiment, optionally, the second JTAG circuit includes a JTAG circuit; the second I2C circuit includes an I2C circuit; the second QSPI circuit includes a QSPI circuit; and the second P_MODE circuit includes a P_MODE circuit.

[0115] It can be seen that the implementation of this optional embodiment can process the HDMI signal received by the second switching processing module through the second processing chip, and output the obtained four-way HDMI signal to the signal output module, and through the coordinated operation of the second JTAG circuit, the second I2C circuit, the second QSPI circuit, the second P_MODE circuit and the AUDIO circuit, it can convert one input HDMI signal into four output HDMI signals through the second processing chip, and at the same time support up to 8K HDMI video signal output, can improve the processing capability of HDMI signals, improve the ability to output multiple high-quality HDMI signals, can synchronously display the same high-quality HDMI signal content on different devices, and improve user experience.

[0116] In yet another optional embodiment, the control module 106 includes a control chip and an EDID dialing circuit, wherein:

[0117] The first end of the control chip is electrically connected to the third end of the first switching processing module 101, the second end of the control chip is electrically connected to the third end of the second switching processing module 102, and the third end of the control chip is electrically connected to the first end of the EDID dialing circuit;

[0118] The EDID dial circuit is used to control the signal format of the second target signal output by the signal output module 103 .

[0119] In this optional embodiment, optionally, as Fig.17 As shown, Fig.17 is a schematic diagram of the structure of a control chip disclosed in the utility model, wherein the components included in the control chip and the connection method between the components can be as follows Fig.17 As shown;

[0120] Further, such as Fig.18 As shown, Fig.18 The utility model discloses a structural diagram of an EDID dial code circuit, wherein the components included in the EDID dial code circuit and the connection method between the components can be as follows Fig.18 shown.

[0121] In this optional embodiment, optionally, the control chip may include a GD32F330CBT6 chip with an ARM-M4 CPU core and a storage capacity of 64KB.

[0122] In this optional embodiment, the control chip may be used to simultaneously manage the working modes of the first switching processing module 101 , the second switching processing module 102 , and the signal processing module 105 .

[0123] In this optional embodiment, optionally, the EDID dial circuit can be used to control the signal format of the second target signal output by the signal output module 103. Specifically, when the GPIO0 pin of the EDID dial circuit is 1 and the GPIO1 pin is 1, the signal distribution circuit of the adaptive gain adjustment is in EDID COPY mode, at which time the EDID of the first external target device is copied, and the remaining seven outputs output signals according to the EDID of the first channel. When the GPIO0 pin of the EDID dial circuit is 0 and the GPIO1 pin is 0, the signal distribution circuit of the adaptive gain adjustment is in EDID Compose mode, at which time the EDID is compared, and the signal of corresponding clarity is adaptively output according to the EDID of the target device. When the GPIO0 pin of the EDID dial circuit is 0 and the GPIO1 pin is 1, the signal distribution circuit of the adaptive gain adjustment is fixed to output 4K or 2K signals. When the GPIO0 pin of the EDID dial circuit is 1 and the GPIO1 pin is 0, the signal distribution circuit of the adaptive gain adjustment is fixed to output 8K signals.

[0124] It can be seen that the implementation of this optional embodiment can quickly respond and accurately control the working status of each module or circuit through the control chip, thereby improving the response speed and control accuracy of the system, and also enhancing the flexibility and scalability of the system, and improving the reliability of the system, making the entire system more efficient, stable, reliable and flexible, and able to meet various complex application requirements. At the same time, the format of the HDMI video signal output by the signal output module can be changed through the EDID dial circuit. When facing different display resolutions of different target devices, the format of the output HDMI video signal can be adjusted according to the EDID of the target device, or the EDID of the target device connected to a certain port can be copied as a unified output HDMI video signal format, or it can be output in a fixed HDMI video signal format, and can adapt to devices of various resolution types, improve the flexibility and stability of HDMI video signal output, and can change the format of the output HDMI video signal according to user needs, thereby improving user experience.

[0125] In yet another optional embodiment, the circuit further includes a signal input module 104, the signal input module 104 includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein:

[0126] The first end of the target input chip is electrically connected to the first end of the signal processing module 105, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

[0127] In this optional embodiment, optionally, as Fig.19 As shown, Fig.19 is a schematic diagram of the structure of a target input chip disclosed in the utility model, wherein the components included in the target input chip and the connection method between the components can be as follows Fig.19 As shown;

[0128] Further, such as Fig. 20 As shown, Fig. 20 The utility model discloses a schematic diagram of the structure of an input ESD processing circuit, wherein the components included in the input ESD processing circuit and the connection method between the components can be as follows: Fig. 20 As shown;

[0129] Further, such as Fig.21 As shown, Fig.21 The utility model discloses a structural diagram of an input DDC processing circuit, wherein the components included in the input DDC processing circuit and the connection method between the components can be as follows Fig.21 As shown;

[0130] Further, such as Fig. 22 As shown, Fig. 22 The utility model discloses a schematic diagram of the structure of an input HPD processing circuit, wherein the components included in the input HPD processing circuit and the connection method between the components can be as follows: Fig. 22 shown.

[0131] In this optional embodiment, optionally, the target input chip may be a HDMI_A_SMD chip; further, the target input chip may be a HDMI_RX_23P_SMT_0228 chip.

[0132] In this optional embodiment, the input ESD processing circuit optionally includes an ESD protection circuit, wherein the ESD protection circuit is a circuit design for protecting electronic components from external electrostatic discharge damage. Electrostatic discharge refers to a short-term high-voltage discharge phenomenon caused by an imbalance of charge, which can cause irreversible damage to sensitive electronic devices. The design goal of the ESD protection circuit is to guide the energy of external electrostatic discharge to a safe place to prevent it from causing damage to electronic equipment.

[0133] In this optional embodiment, optionally, the input DDC processing circuit includes a DDC processing circuit, wherein the DDC processing circuit is the abbreviation of a digital downconverter processing circuit, which is used in a communication system to mix with a sinusoidal signal (local oscillator) generated by a local oscillator, thereby changing the frequency band in which the signal is located. Specifically, increasing the frequency is up-conversion, and reducing the frequency is down-conversion. Wherein, the DDC processing circuit includes at least one pull-up resistor, wherein the pull-up resistor is a resistor device, and its main function is to pull a certain signal pin to a high level so that the signal remains in a high level state. The pull-up resistor is usually used together with the pull-down resistor to control the signal transmission and logic function of the circuit. Further, the input signal of the video input chip is maintained at a high level of the signal by the pull-up resistor, which can avoid the signal from having a bad level, can be conducive to improving the accuracy and reliability of the input signal, and can improve the driving ability of the video input chip.

[0134] In this optional embodiment, the input HPD processing circuit optionally includes an HPD input level conversion circuit, wherein the HPD input level conversion circuit is a circuit specifically used to process HPD (high voltage discharge) signals, and its main function is to convert the level of the input HPD signal into a range suitable for subsequent circuit processing. For example, if the voltage corresponding to the device connected to the video input chip is 5V, and the operating voltage corresponding to the video input chip is 3.3V, then the voltage corresponding to the device connected to the video input chip does not match the voltage corresponding to the video input chip, then the HPD conversion submodule performs a level conversion operation, converting the voltage corresponding to the device connected to the video input chip of 5V to the voltage corresponding to the video input chip of 3.3V, so as to ensure the normal operation of the chip and prevent the chip from being damaged by high voltage.

[0135] In this optional embodiment, optionally, for example, an HDMI input signal is collected through a target input chip, and an electrostatic protection operation is performed on the target input chip through an input ESD processing circuit to prevent external static electricity from entering the target input chip and causing damage to the target input chip, and the driving capability of the target input chip is improved through an input DDC processing circuit, and a level conversion operation is performed through an input HPD processing circuit, which can effectively protect the target input chip from being damaged by external high voltage.

[0136] It can be seen that the implementation of this optional embodiment can collect HDMI input signals through the target input chip in the signal input module, and improve the driving capability of the target input chip through the input DDC processing circuit, and eliminate the influence of the outside world on the target input chip through the input ESD processing circuit, and perform level conversion operation through the input HPD processing circuit, and can effectively improve the driving capability of the target input chip through the input DDC processing submodule, which is beneficial to improve the stability and high quality of the HDMI input signal during data transmission, and can reduce signal attenuation and distortion when transmitting over long distances or in complex environments, thereby improving the performance of the overall system, and through the input ESD processing circuit The circuit can effectively absorb and disperse the energy of electrostatic discharge, protect the target input chip from damage, and improve the stability and reliability of the equipment. The input HPD processing circuit can help ensure that the signals between different modules can be correctly matched and transmitted, avoiding signal distortion or errors caused by level mismatch. Among them, level conversion is a key step in circuit design. It can make the entire system more flexible and compatible, which is conducive to improving the flexibility and compatibility of the target input chip, thereby achieving the improvement and protection of the target input chip performance, and also improving the stability and reliability of the entire system, which is conducive to improving the accuracy, reliability and intelligence of the adaptive gain adjustment.

[0137] In yet another optional embodiment, the signal output module 103 includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit, and a current limiting protection circuit, wherein:

[0138] The first end of the target output chip is electrically connected to the second end of the second switching processing module 102, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output chip is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output chip is electrically connected to the first end of the current limiting protection circuit.

[0139] In this optional embodiment, optionally, as Fig.23 As shown, Fig.23 is a schematic diagram of the structure of a target output chip disclosed in the utility model, wherein the components included in the target output chip and the connection method between the components can be as follows Fig.23 As shown;

[0140] Further, such as Fig.24 As shown, Fig.24 The utility model discloses a schematic diagram of the structure of an output ESD processing circuit, wherein the components included in the output ESD processing circuit and the connection method between the components can be as follows Fig.24 As shown;

[0141] Further, such as Fig.25 As shown, Fig.25 The utility model discloses a structural diagram of an output DDC processing circuit, wherein the components included in the output DDC processing circuit and the connection method between the components can be as follows Fig.25 As shown;

[0142] Further, such as Fig.26 As shown, Fig.26 The utility model discloses a schematic diagram of the structure of an output HPD processing circuit, wherein the components included in the output HPD processing circuit and the connection method between the components can be as follows: Fig.26 As shown;

[0143] Further, such as Fig. 27 As shown, Fig. 27 The utility model discloses a structural diagram of a current limiting protection circuit, wherein the components included in the current limiting protection circuit and the connection method between the components can be as follows Fig. 27 shown.

[0144] In this optional embodiment, optionally, the current limiting protection circuit includes a current limiting short circuit protection circuit, wherein the current limiting short circuit protection circuit is an electronic protection circuit, wherein it is intended to limit current and provide protection in the event of a short circuit. Further, the basic principle of the current limiting short circuit protection circuit is to monitor the magnitude of the current and trigger protection measures when the current exceeds a certain threshold. Furthermore, specific protection measures may include one or more of cutting off power supply, reducing output voltage, and limiting current to prevent excessive current caused by a short circuit from damaging the circuit.

[0145] In this optional embodiment, optionally, the target output chip may be a HDMI_A_SMD chip; further, the target output chip may be a HDMI_RX_23P_SMT_0228 chip.

[0146] In this optional embodiment, optionally, the second target signal is transmitted to a preset target device through the target output chip, and the driving capability of the target output chip is improved through the output DDC processing circuit, and a level conversion operation is performed on the level signal corresponding to the output DDC processing circuit and the level signal corresponding to the output ESD processing circuit according to the output HPD processing circuit, so that the levels between the electronic components are balanced with each other, which can effectively protect the target output chip from being damaged by external high voltage, and can also prevent short circuits and burning of the target output chip through current limiting protection circuits.

[0147] It can be seen that the implementation of this optional embodiment can transmit the second target signal to the preset target device through the target output chip, and improve the driving ability of the target output chip through the output DDC processing circuit, and perform level conversion operations on the level signal corresponding to the output DDC processing circuit and the level signal corresponding to the output HPD processing circuit through the output HPD processing current, and eliminate the influence of static electricity on the target output chip through the output ESD processing circuit, and prevent the target output chip from short-circuiting and burning the chip through the current limiting protection circuit. The driving ability of the target output chip can be significantly improved through the output DDC processing circuit, which is conducive to making the video signal more stable and more efficiently transmitted to the target device, and the output HPD processing circuit not only realizes the conversion of the output level signal of the output DDC processing circuit, but also processes the level signal of the output ESD processing circuit, so that the signal is ensured through double level conversion. The accuracy and completeness of the system enable the entire system to adapt to a variety of different devices or interfaces, greatly improving compatibility. The output ESD processing circuit provides effective electrostatic protection for the target output chip to prevent external static electricity from having a negative impact on the video output chip. Once a short circuit is detected through the current limiting protection circuit, the circuit can quickly cut off or limit the current to avoid irreversible damage to the chip and other related components. This not only optimizes the transmission and processing of HDMI signals, but also strengthens the system's protection mechanism, so that it can operate stably and safely in the face of various challenges, and then can also achieve the performance improvement and protection of the target output chip, while also improving the stability and reliability of the entire system, which is conducive to improving the accuracy, reliability and intelligence of achieving adaptive gain adjustment.

[0148] In yet another optional embodiment, the signal processing module 105 includes a signal processing chip, wherein:

[0149] A first end of the signal processing chip is electrically connected to a first end of the signal input module 104 , and a second end of the signal processing chip is electrically connected to a first end of the first switching processing module 101 .

[0150] In this optional embodiment, optionally, as Fig.28 As shown, Fig.28 The utility model discloses a schematic diagram of the structure of a signal processing chip, wherein the components included in the signal processing chip and the connection method between the components can be as follows Fig.28 shown.

[0151] In this optional embodiment, optionally, the signal processing chip can be an HDMI2.1 video processing chip PS8419 with a Redriver.

[0152] It can be seen that the implementation of this optional embodiment can perform gain control on the compensation insertion loss of the target input signal transmitted by the received signal input module through the signal processing chip, thereby improving the quality and stability of the HDMI signal.

[0153] Embodiment 2

[0154] See also Fig.29 , Fig.29 This is a schematic diagram of the structure of a dispenser disclosed in an embodiment of the utility model. Fig.29 The distributor shown includes a signal distribution circuit for adaptively adjusting gain as in any one of the embodiments of the first embodiment. And the signal distribution function of adaptively adjusting gain that can be implemented by the distributor includes but is not limited to adaptively adjusting gain to improve the quality of the output signal, converting one HDMI video signal input into multiple HDMI video signal outputs, realizing multiple 8K video signal outputs, improving the distribution output capacity and output clarity of the HDMI signal, and thus helping to improve the user experience. It should be noted that for the message description of the distributor, please refer to the specific description of the relevant content in the first embodiment, which will not be repeated in this embodiment.

[0155] It can be seen that the implementation Fig.29 The described distributor can adapt to adjust the gain to improve the quality of the output signal, convert one HDMI video signal input into multiple HDMI video signal outputs, realize multiple 8K video signal outputs, improve the distribution output capacity and output clarity of the HDMI signal, and thus help improve the user experience.

[0156] The above is a detailed introduction to a signal distribution circuit and distributor for adaptively adjusting gain disclosed in an embodiment of the utility model. Specific embodiments are used in this article to illustrate the principles and implementation methods of the utility model, but the above preferred embodiments are not used to limit the utility model. The description of the above embodiments is only used to help understand the method of the utility model and its core idea; at the same time, for general technical personnel in this field, based on the idea of ​​the utility model, without departing from the spirit and scope of the utility model, there will be changes in the specific implementation method and application scope. Therefore, the scope of protection of the utility model shall be based on the scope defined by the claims.

Claims

1. A signal distribution circuit for adaptively adjusting gain, characterized in that: The circuit comprises a first switching processing module, a second switching processing module and a signal output module, wherein: The first end of the first switching processing module is used to electrically connect to the signal input module, the second end of the first switching processing module is electrically connected to the first end of the second switching processing module, and the second end of the second switching processing module is electrically connected to the first end of the signal output module; The first switching processing module is used to receive the target input signal transmitted by the signal input module, perform a first target processing operation on the target input signal, obtain a first target signal, and transmit the first target signal to the second switching processing module; The second switching processing module is used to perform a second target processing operation on the first target signal to obtain a second target signal and transmit the second target signal to the signal output module; The signal output module is used to transmit the received second target signal to a preset target device.

2. The signal distribution circuit for adaptively adjusting gain according to claim 1, characterized in that: The circuit also includes a signal processing module, wherein: The first end of the signal processing module is used to be electrically connected to the signal input module, and the second end of the signal processing module is electrically connected to the first end of the first switching processing module; The signal processing module is used to receive the target input signal transmitted by the signal input module, perform signal processing operations on the target input signal, obtain the target input signal after signal processing, and transmit the target input signal after signal processing to the first switching processing module.

3. The signal distribution circuit for adaptively adjusting gain according to claim 2, characterized in that: The circuit also includes a control module, wherein: The first end of the control module is electrically connected to the third end of the first switching processing module, and the second end of the control module is electrically connected to the third end of the second switching processing module; The control module is used to manage the working modes of the first switching processing module, the second switching processing module and the signal processing module.

4. The signal distribution circuit for adaptively adjusting gain according to claim 3, characterized in that: The first switching processing module includes a first processing chip, a first JTAG circuit, a first I2C circuit, a first QSPI circuit and a first P_MODE circuit, wherein: A first end of the first processing chip is electrically connected to a second end of the signal processing module, a second end of the first processing chip is electrically connected to a first end of the second switching processing module, a third end of the first processing chip is electrically connected to a first end of the control module, a fourth end of the first processing chip is electrically connected to a first end of the first JTAG circuit, a fifth end of the first processing chip is electrically connected to a first end of the first I2C circuit, a sixth end of the first processing chip is electrically connected to a first end of the first QSPI circuit, and a seventh end of the first processing chip is electrically connected to a first end of the first P_MODE circuit.

5. The signal distribution circuit for adaptively adjusting gain according to claim 3 or 4, characterized in that: The second switching processing module includes a second processing chip, a second JTAG circuit, a second I2C circuit, a second QSPI circuit, a second P_MODE circuit and an AUDIO circuit, wherein: A first end of the second processing chip is electrically connected to a second end of the first switching processing module, a second end of the second processing chip is electrically connected to a first end of the signal output module, a third end of the second processing chip is electrically connected to a second end of the control module, a fourth end of the second processing chip is electrically connected to a first end of the second JTAG circuit, a fifth end of the second processing chip is electrically connected to a first end of the second I2C circuit, a sixth end of the second processing chip is electrically connected to a first end of the second QSPI circuit, a seventh end of the second processing chip is electrically connected to a first end of the second P_MODE circuit, and an eighth end of the second processing chip is electrically connected to a first end of the AUDIO circuit.

6. The signal distribution circuit for adaptively adjusting gain according to claim 3 or 4, characterized in that: The control module includes a control chip and an EDID dialing circuit, wherein: The first end of the control chip is electrically connected to the third end of the first switching processing module, the second end of the control chip is electrically connected to the third end of the second switching processing module, and the third end of the control chip is electrically connected to the first end of the EDID dialing circuit; The EDID dial circuit is used to control the signal format of the second target signal output by the signal output module.

7. The signal distribution circuit for adaptively adjusting gain according to any one of claims 2 to 4, characterized in that: The circuit further includes the signal input module, which includes a target input chip, an input ESD processing circuit, an input DDC processing circuit, and an input HPD processing circuit, wherein: The first end of the target input chip is electrically connected to the first end of the signal processing module, the second end of the target input chip is electrically connected to the first end of the input ESD processing circuit, the third end of the target input chip is electrically connected to the first end of the input DDC processing circuit, and the fourth end of the target input chip is electrically connected to the first end of the input HPD processing circuit.

8. The signal distribution circuit for adaptively adjusting gain according to any one of claims 1 to 4, characterized in that: The signal output module includes a target output chip, an output ESD processing circuit, an output DDC processing circuit, an output HPD processing circuit and a current limiting protection circuit, wherein: The first end of the target output chip is electrically connected to the second end of the second switching processing module, the second end of the target output chip is electrically connected to the first end of the output ESD processing circuit, the third end of the target output chip is electrically connected to the first end of the output DDC processing circuit, the fourth end of the target output chip is electrically connected to the first end of the output HPD processing circuit, and the fifth end of the target output chip is electrically connected to the first end of the current limiting protection circuit.

9. The signal distribution circuit for adaptively adjusting gain according to claim 7, characterized in that: The signal processing module includes a signal processing chip, wherein: The first end of the signal processing chip is electrically connected to the first end of the signal input module, and the second end of the signal processing chip is electrically connected to the first end of the first switching processing module.

10. A distributor, comprising an input port for receiving an HDMI signal, a signal distribution circuit for adaptively adjusting gain as claimed in any one of claims 1 to 9, and an output port for outputting a second target signal.

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