Off-chip capacitor-free low dropout linear regulator with wide bandwidth and high PSR

Abstract

The utility model discloses an off-chip capacitor-free low dropout regulator (LDO) with wide bandwidth and high power supply rejection (PSR) capability. An LDO circuit comprises a power supply rejection enhancement circuit and a frequency compensation circuit. The power supply suppression enhancement circuit not only can expand the overall loop bandwidth and improve the load current response speed, but also can improve the power supply suppression capability of high frequency bands in the LDO; according to the frequency compensation circuit based on the feedforward capacitance compensation technology and the Miller compensation technology with the zero setting resistor, two left half plane zero points can be provided for ensuring that the whole loop of the LDO has enough phase margin and gain margin within the full-load current change range so as to ensure stable operation of the LDO. The system has the advantages of high load response speed, wide bandwidth, high PSR and the like.

Description

Technical Field

[0001] The utility model relates to the field of semiconductor integrated circuits, in particular to a low-voltage difference linear regulator with wide bandwidth and high PSR and no external capacitor. Background Art

[0002] The power management unit in the system-on-chip (SOCs) application usually includes a switching power converter DC-DC module and an LDO module. The DC-DC module is often used to drive noise-insensitive modules, such as processor circuits, due to the large output voltage fluctuation. The LDO module is usually cascaded after a high-efficiency switching regulator to filter switching noise and provide a relatively clean driving voltage for noise-sensitive circuits such as sensors and power amplifiers. Although the LDO with an external uF-level capacitor has good power supply rejection characteristics, it is not conducive to integration. Moreover, with the development of SOCs, the random noise from the power supply has become more and more obvious in deteriorating the function of noise-sensitive circuits. Therefore, the LDO without external capacitors that still has high PSR characteristics in a wider frequency range needs to be studied and developed. Utility Model Content

[0003] The utility model provides a low voltage drop linear regulator with wide bandwidth and high power supply suppression capability without external capacitors.

[0004] The low-dropout linear regulator (LDO) without off-chip capacitors includes a power supply rejection enhancement circuit and a frequency compensation circuit. The power supply rejection enhancement circuit can not only expand the overall loop bandwidth and improve the load current response speed, but also improve the power supply rejection capability of the LDO in the medium and high frequency bands; the frequency compensation circuit based on the feedforward capacitor compensation technology and the Miller compensation technology with zero adjustment resistor can provide two left half plane zero points to ensure that the LDO overall loop has sufficient phase margin and gain margin within the full load current variation range, so as to ensure the stable operation of the LDO.

[0005] The power supply suppression enhancement circuit includes an ideal current source IREF, a resistor R1, two capacitors C1 and C2, six NMOS tubes, and eight PMOS tubes. The first terminal of the current source is connected to the input pin LDO_IN of the LDO; the second terminal of the current source, the drain and gate of MN1, the gate of MN2, and the gate of MN6 are connected to each other, and the network is marked as VBN. The source of MN1, the source of MN2, the source of MN3, the source of MN4, the second terminal of capacitor C2, the source of MN5, and the source of MN6 are all connected to the power ground AVSS; the drain of MN2, the drain and gate of MP1, the gate of MP2, and the first terminal of R1 are connected to each other, and the network is marked as VBP. The source of MP1, the source of MP2, the source of MP3, the source of MP4, the source of MP6, and the source of MP7 are all connected to the input pin LDO_IN of the LDO. The drain of MP2, the drain of MP3, the drain and gate of MN3, and the gate of MN4 are connected to each other; the second terminal of resistor R1, the first terminal of capacitor C1, and the gate of MP4 are connected to each other; the second terminal of capacitor C1 is connected to the power ground AVSS. The gate of MP3, the drain of MP4, the source of MP5, the gate and drain of MP6, the gate of MP7, and the drain of MN5 are connected to each other, and the network identification name is VG. The drain of MP5, the first terminal of C2, the drain of MN4, and the gate of MN5 are connected to each other; the gate of MP5, the drain of MP8, and the drain of MN6 are connected to each other, and the network identification name is VSSF; the drain of MP7 and the source of MP8 are connected to the output pin LDO_OUT of LDO.

[0006] The frequency compensation circuit includes two capacitors Cc and CF, three resistors Rz, RF1, and RF2, and an error amplifier EA. The first terminal of the resistor Rz is connected to the network identifier VSSF; the second terminal of Rz is connected to the second terminal of the capacitor Cc; the first terminal of Cc and the output terminal of the error amplifier are both connected to the gate of MP8. The non-inverting input terminal of EA is connected to the reference voltage input pin VREF of LDO; the inverting input terminal of EA, the second terminal of the resistor RF1, the second terminal of the capacitor CF, and the first terminal of the resistor RF2 are connected to each other; the first terminal of RF1 and the first terminal of CF are connected to each other to the output pin LDO_OUT of LDO; the second terminal of the resistor RF2 is connected to the power ground AVSS.

[0007] Preferably, the error amplifier EA in the frequency compensation circuit adopts a folded cascode amplifier with a PMOS as an input pair, and the power supply voltage of the error amplifier EA comes from the output end of the LDO.

[0008] Technical features and effects of this utility model:

[0009] The utility model adopts a topological structure that integrates a super source follower and a flip voltage follower, which can realize the expansion of the loop bandwidth and improve the load transient characteristics of the LDO; the feedforward ripple cancellation technology is adopted to optimize the PSR characteristics of the LDO in the middle and high frequency bands; Miller compensation and feedforward capacitor compensation technology are adopted to ensure the stability of the LDO loop. Under the conditions of input voltage 1.2V, output 1V, and load capacitance CL fluctuation range of 10pF to 200pF, when the load current of the LDO suddenly changes from 0mA to 50mA within 0.5us, it can recover to the ideal value within 1us and the error is less than 0.1%, and has a good load response effect. Under the load change of 0 to 50mA, the low-frequency PSR value reaches 90dB, the frequency bandwidth of PSR exceeds 10MHz, and the mid-frequency band PSR can achieve a maximum improvement of 12dB. The utility model has the advantages of faster load response speed, wide bandwidth, high PSR, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is the overall circuit diagram of the utility model;

[0011] FIG2 (a, b) depicts the loop stability simulation results of the present invention under different load currents;

[0012] FIG3 (a, b, c) describes the load transient simulation results of the present invention;

[0013] Figure 4 The simulation results of the power supply rejection capability of the utility model under different load currents are described. DETAILED DESCRIPTION

[0014] The technical solution of the present utility model is described in detail below with reference to the accompanying drawings and embodiments for better understanding.

[0015] In power management chips, low-dropout linear regulators are usually cascaded after high-efficiency switching regulators to provide power supply voltage for other modules in the circuit. The output voltage ripple of the switching regulator is large, so the LDO needs to have good PSR characteristics to filter out random noise from the output of the switching regulator to ensure stable operation of subsequent circuit modules.

[0016] The utility model has no external capacitor low voltage difference linear regulator. Figure 1As shown, it includes a power supply rejection enhancement circuit and a frequency compensation circuit. The LDO input voltage LDO_IN is 1.2V, and its output voltage is 1V. The ideal current source IREF in the power supply rejection ratio circuit provides a bias current of 2uA. The error amplifier EA in the frequency compensation circuit adopts a folded common source and common gate amplifier with PMOS as the input pair to ensure the low-frequency PSR characteristics of the LDO. The ratio of its feedback resistors RF1 and RF2 is 1:1. Due to the virtual short characteristic of the error amplifier EA, the reference voltage VREF connected to its in-phase terminal is a DC voltage of 0.5V, which is used to determine the static operating point of EA.

[0017] In the power supply rejection ratio enhancement circuit of the utility model, the ideal current source IREF, MN1 tube, MN2 tube, and MP1 tube form a bias circuit, wherein the current provided by the current source generates a bias voltage VBN with the diode-connected MN1 tube, providing a bias voltage for the MN6 tube; the MN2 tube and the MN1 tube form a 1:1 current mirror, after copying the current in the ideal current source, generate a bias voltage VBP with the diode-connected MP1, which can provide a bias voltage for the MP2 tube and the MP4 tube. The MP2 tube and the MP1 tube form a 1:3 current mirror, which can amplify the current of the branch where the MP1 tube is located by 3 times and serve as the reference input current of the MN3; the MN3 tube and the MN4 tube form a 1:1 current mirror, copy the current of the branch where the MN3 tube is located to the MN4 tube and use it to determine the bias current flowing into the MP5 tube; the MN6 tube and the MN1 tube form a current mirror, which mirrors the current of the branch where the MN1 tube is located and is used to determine the current flowing into the MP8 tube. The gates of the MP3 tube, the MP6 tube, and the power transistor MP7 are interconnected and the sources are at the same potential, so the VSG voltage difference of the three PMOS tubes will remain consistent. Therefore, the MP3 tube and the MP6 tube can be used to detect the current generated by the MP7 tube, thereby indirectly detecting the load current fluctuation. When the gate voltage of the MP7 tube drops due to a sudden increase in the load current, the MP3 tube will generate more current to be injected into the drain of the MN3 tube, and then the current flowing into the MP5 tube will increase after being mirrored by the MN4 tube, thereby enhancing the driving ability of the MP5 tube; the MP6 tube will also generate more current to flow into the MN5 tube, making the negative feedback effect of the MN5 tube stronger, reducing the equivalent resistance at the source of the MP5 tube, and the diode-connected MP6 tube has a lower output impedance, which further reduces the output impedance of the source follower, thereby improving the driving ability of the buffer stage. The output impedance of the adaptively biased source follower can be approximately expressed as:

[0018] Since the structure has an extremely low output impedance, the pole corresponding to the gate of the power transistor MP7 can be pushed to a higher frequency, thus not affecting the stability of the loop. In addition, the MP8, MP5, and MP7 tubes form a fast local negative feedback loop. When the load has a rapid mutation, the MP8 tube, as a common-gate amplifier, can detect the undershoot at LDO_OUT and feed it back to the gate of the power tube through the MP5 tube with a very small delay, thereby realizing a fast local negative feedback loop to improve the transient response characteristics of the load. In addition, due to the existence of the negative feedback loop, the equivalent impedance at the source of the MP8 tube drops to an open-loop state. Among them A V,Loopgain is the loop gain, the equivalent impedance of the open loop Therefore, the lower output impedance can push up the pole frequency corresponding to the output end, thereby expanding the loop bandwidth. The MN5 tube and the MP5 tube also have a local negative feedback loop. In order to avoid the jitter problem of the LDO main loop in the transient step response caused by the instability of the internal loop, a compensation capacitor C2 of a certain size is added to the gate of the MN5 tube.

[0019] In the power supply suppression enhancement circuit of the utility model, the MP1 tube and the MP4 tube form a current mirror, part of the current generated by the MP4 tube flows into the MP5 tube, and part flows into the MN5 tube; the resistor R1 and the capacitor C1 can be used to generate a low-frequency pole, and the corresponding pole frequency is approximately expressed as: The low-pass filter network formed by R1 and C1 can treat the gate of MP4 as an AC ground. Therefore, the MP4 tube, resistor R1, and capacitor C1 form an operating frequency that must exceed P LPF If a common-gate amplifier is used, the high-frequency power ripple from the LDO_IN end will be amplified and reused to the gate of the power transistor MP7. The introduced ripple size can be expressed as: Where Vin represents the high-frequency power ripple from the LDO_IN terminal. The high-frequency ripple current introduced by the power transistor MP7 at the output terminal LDO_OUT is i out,MP7 =(g mp7 +g dsp7 )V in ; In order to completely offset the high-frequency ripple current introduced by the MP7 tube at the output end LDO_OUT, the feedforward ripple voltage introduced at the gate end of the MP7 tube needs to be additionally: Therefore, by setting the width-to-length ratio of MP4, MP5, MP6, and MN5 tubes, V g,FFRC The size of V g,optimal This ensures that the power ripples at the LDO_OUT end cancel each other out and improves the PSR characteristics of the LDO.

[0020] The error amplifier EA in the frequency compensation circuit of the utility model adopts a folded common source and common gate amplifier with a PMOS as the input pair tube. The amplifier has a relatively high DC gain to ensure the PSR characteristics of the LDO low frequency band. At the same time, the power supply voltage of the error amplifier EA comes from the output end of the LDO, which can further optimize the power supply suppression capability of the LDO low frequency band. Due to the influence of the Miller effect, the added compensation capacitor Cc and the equivalent resistance R at the output end of the error amplifier out,EA This produces a pole whose expression is Among them C tot,EA Represents the total capacitance at the VEA node, that is, C tot,EA ≈[1+g mp8 *(r dsn6 ||g mp8 r dsp8 r dsp7 )], and this pole is also the main pole of the entire LDO loop. In addition, the resistor Rz and the capacitor Cc will also produce a zero point, and the corresponding zero point expression is: Therefore, the position of the zero point can be adjusted by setting the size of the resistor Rz, thereby improving the phase margin of the loop. The resistors RF1, RF2, and capacitor CF form a feedforward capacitor compensation network, which will introduce a pole and a left half plane zero point. The corresponding expression is: By setting the size of capacitor CF and the ratio of feedback resistors RF1 and RF2, the relative position of the left half plane zero and pole can be controlled, thereby ensuring that the LDO has good phase margin and gain margin in the full load current conversion range.

[0021] The simulation results of the main loop stability of the utility model under different load current sizes are shown in Figure 2 (a, b). Under no-load conditions, the phase margin of the LDO is the smallest, which is 41°; the minimum unit gain bandwidth product (UGBW) is 3.4MHz, and the gain margin (GM) is 26dB; when the load current is 50mA, the phase margin of the LDO loop is 114°; the gain bandwidth product is 8.5MHz, and the gain margin is 15dB. It can be seen from the simulation results that when the input voltage is 1.2V, the output is 1V, and the load capacitance is 100pF, whether under light load or heavy load, the low-frequency loop gain of the LDO is around 75dB, the phase margin is the worst 41°, and the gain margin is the worst 15dB. The utility model achieves the stability of the LDO loop within the full load current variation range by adopting Miller compensation technology and feedforward capacitor compensation technology, thereby ensuring the stability requirements of the system.

[0022] FIG3 (a, b, c) shows the load transient simulation results of the LDO of the utility model. Under the same transient test conditions, the transient simulation results of only using a super source follower to drive the power transistor and using the buffer stage circuit proposed in the utility model to drive the power tube are compared as shown in FIG3 (a). In comparison, the dive of the LDO of the utility model is reduced by 100mV, and the response recovery time is shortened to less than 1us. When the load current changes from 0 to 50mV, the transient response curve of the LDO under different load capacitances is shown in FIG3 (b). It can be seen from the simulation results that the undershoot amount and undershoot recovery time of the LDO are basically unchanged, but with the increase of the load capacitance, the required overshoot recovery time will increase, and the maximum overshoot recovery time is 2us. The load capacitance connected to the LDO of the utility model is 100pF, and the transient response curve when the load current undergoes different degrees of mutation is shown in FIG3 (c). When the load current suddenly changes from 0mA to 10mA, the corresponding undershoot voltage is 75mV and the overshoot voltage is 95mV, and when the load current suddenly changes from 1mA to 50mA, the corresponding undershoot voltage is 50mV and the overshoot voltage is 115mV, both of which can achieve stability within a time range of 1us. In summary, the LDO without external capacitors provided by the utility model can achieve good transient response results within the range of 0-50mA and parasitic load capacitance of 10pF-200pF.

[0023] Under the conditions of input voltage 1.2V and load capacitance 100pF, the simulation results of the characteristic curve of the utility model under different load currents are as follows: Figure 4 As shown. Compared with the case where the power supply rejection enhancement circuit provided by the utility model is not used, the PSR of the LDO of the utility model at the low frequency end is improved by 10dB, but for different load current sizes, the PSR improvement effect in the medium and high frequency bands is inconsistent. Under no-load conditions, the maximum optimized PSR level is about 12dB. As the load current increases, it decreases to 4dB under the maximum load current. After adopting the power supply rejection enhancement circuit provided by the utility model, the low-frequency PSR value of the LDO reaches 90dB under the load change of 0-50mA, and the frequency bandwidth of the PSR exceeds 10MHz.

[0024] The utility model adopts Miller compensation with zero adjustment resistor and feedforward capacitor compensation technology to ensure that the LDO has sufficient phase margin and gain margin within the full load current variation range; adopts a topological structure combining a super source follower and a flip voltage follower to drive the power transistor, expands the loop bandwidth and thus improves the load transient response characteristics of the LDO, and also embeds a passive first-order low-pass filter network into the buffer stage, thereby improving the LDO power supply suppression capability.

Claims

1. A low voltage dropout linear regulator with wide bandwidth and high PSR and no external capacitor, comprising a power supply rejection enhancement circuit and a frequency compensation circuit, characterized in that: The power supply rejection enhancement circuit comprises: a current source IREF, a resistor R1, capacitors C1 and C2, NMOS tubes MN1, MN2, MN3, MN4, MN5 and MN6, and PMOS tubes MP1, MP2, MP3, MP4, MP5, MP6, MP7 and MP8; the first terminal of the current source IREF is connected to the input pin LDO_IN of the LDO; the second terminal of the current source IREF, the drain and gate of MN1, the gate of MN2, and the gate of MN6 are connected to each other, and the connection point network is marked as VBN; the sources of MN1, MN2, MN3, MN4, MN5, MN6 and the second terminal of the capacitor C2 are all connected to the power ground AVSS; the drain of MN2, the drain and gate of MP1, the gate of MP2 and the first terminal of R1 are connected to each other, and the connection point network is marked as VBP; MP1, MP2 The sources of MP3, MP4, MP6 and MP7 are all connected to the input pin LDO_IN of this LDO; the drain of MP2, the drain of MP3, the drain and gate of MN3, and the gate of MN4 are connected to each other; the second terminal of resistor R1, the first terminal of capacitor C1, and the gate of MP4 are connected to each other; the second terminal of capacitor C1 is connected to the power ground AVSS; the gate of MP3, the drain of MP4, the source of MP5, the gate and drain of MP6, the gate of MP7, and the drain of MN5 are connected to each other, and the connection point network is marked as VG; the drain of MP5, the first terminal of C2, the drain of MN4, and the gate of MN5 are connected to each other; the gate of MP5, the drain of MP8, and the drain of MN6 are connected to each other, and the connection point network is marked as VSSF; the drain of MP7 and the source of MP8 are all connected to the output pin LDO_OUT of this LDO; The frequency compensation circuit includes: capacitors Cc and CF, resistors Rz, RF1 and RF2, and an error amplifier EA; the first terminal of Rz is connected to the network identifier VSSF, and the second terminal of Rz is connected to the second terminal of Cc; the first terminal of Cc and the output terminal of the error amplifier are both connected to the gate of MP8; the non-inverting input terminal of EA is connected to the reference voltage input pin VREF of LDO; the inverting input terminal of EA, the second terminal of RF1, the second terminal of CF, and the first terminal of RF2 are connected to each other; the first terminal of RF1 and the first terminal of CF are both connected to the output pin LDO_OUT of this LDO; the second terminal of RF2 is connected to the power ground AVSS.

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