Voltage suppression circuit
By designing a voltage suppression circuit including the first MOS tube Q1, the BOOST boost circuit and the voltage double circuit, the gate circuit of the first MOS tube Q1 is slowly established, and the existing surge voltage suppression circuit cannot effectively suppress surges. The current problem achieves effective inrush current suppression.
Patent Information
- Application Number
- CN202420716877.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-09
- Publication Date
- 2025-02-18
- Estimated Expiration
- 2034-04-09
AI Technical Summary
The existing surge voltage suppression circuit is quickly established after turning on the input terminal, resulting in a large current spike on the subsequent capacitors, which cannot meet the usage requirements.
A voltage suppression circuit is designed, including a first MOS tube Q1, a BOOST boost circuit and a voltage double circuit. By slowly establishing the gate circuit of the first MOS tube Q1, the inrush current suppression function is realized.
By slowly establishing the gate circuit of the first MOS tube Q1, the voltage suppression circuit can effectively suppress the inrush current, avoid current spikes on the subsequent capacitors, and meet the usage requirements.
Smart Images
Figure CN222509107U_ABST
Abstract
Description
Background Art
[0002] The existing surge voltage suppression circuit has a rapid output after the input is turned on, and generates a large current spike on the subsequent capacitor, which does not meet the use requirements. Summary of the invention
[0003] The present application provides a voltage suppression circuit for realizing the function of surge current suppression.
[0004] The present application provides a voltage suppression circuit, including a first MOS tube Q1, a BOOST boost circuit and a voltage doubling circuit, wherein:
[0005] The D terminal of the first MOS transistor Q1 is electrically connected to the voltage input terminal, and the S terminal of the first MOS transistor Q1 is electrically connected to the voltage output terminal;
[0006] The first end of the voltage doubler circuit is electrically connected to the voltage input end, and the second end of the voltage doubler circuit is electrically connected to the G end of the first MOS transistor Q1;
[0007] The first end of the BOOST boost circuit is electrically connected to the S end of the first MOS transistor Q1 , and the second end of the BOOST boost circuit is electrically connected to the voltage input end.
[0008] In the above technical solution, by setting the first MOS tube Q1, the BOOST boost circuit and the voltage doubler circuit, wherein the D end of the first MOS tube Q1 is electrically connected to the voltage input end, and the S end of the first MOS tube Q1 is electrically connected to the voltage output end; the first end of the voltage doubler circuit is electrically connected to the voltage input end, and the second end of the voltage doubler circuit is electrically connected to the G end of the first MOS tube Q1; the first end of the BOOST boost circuit is electrically connected to the S end of the first MOS tube Q1, and the second end of the BOOST boost circuit is electrically connected to the voltage input end. After power-on, the voltage suppression circuit realizes the surge current suppression function by slowly establishing the gate circuit of the first MOS tube Q1.
[0009] In a specific implementation scheme, the voltage doubling circuit includes a seventh MOS transistor Q7, wherein:
[0010] The D terminal of the seventh MOS transistor Q7 is electrically connected to the G terminal of the first MOS transistor Q1 through a seventh resistor R7;
[0011] The G terminal of the seventh MOS transistor Q7 is electrically connected to the first capacitor plate of the ninth capacitor C9, and the second capacitor plate of the ninth capacitor C9 is electrically connected to the voltage input terminal;
[0012] The S terminal of the seventh MOS transistor Q7 is grounded.
[0013] In a specific implementation scheme, the voltage doubling circuit includes a rectifying unit and a filtering unit, wherein:
[0014] The first capacitor plate of the ninth capacitor C9 is electrically connected to the G terminal of the seventh MOS transistor Q7 through the rectifying unit and the filtering unit in sequence.
[0015] In a specific implementation scheme, the rectifying unit includes a field effect transistor Q8, wherein:
[0016] The first end of the field effect transistor Q8 is electrically connected to the first capacitor plate of the ninth capacitor C9;
[0017] The second end of the field effect transistor Q8 is electrically connected to the G end of the seventh MOS transistor Q7;
[0018] The third terminal of the field effect transistor Q8 is grounded.
[0019] In a specific implementation scheme, the filtering unit includes an eighth capacitor C8 and a sixteenth resistor R16 connected in parallel, wherein:
[0020] The first capacitor plate of the eighth capacitor C8 is electrically connected to the G terminal of the seventh MOS transistor Q7, and the second capacitor plate of the eighth capacitor C8 is grounded;
[0021] A first end of the sixteenth resistor R16 is electrically connected to the G end of the seventh MOS transistor Q7 , and a second end of the sixteenth resistor R16 is grounded.
[0022] In a specific implementation scheme, the voltage doubling circuit includes a fifteenth resistor R15, wherein:
[0023] The first end of the fifteenth resistor R15 is electrically connected to the S end of the seventh MOS transistor Q7.
[0024] A second end of the fifteenth resistor R15 is grounded.
[0025] In a specific implementation manner, the seventh MOS transistor Q7 is a depletion-type NMOS transistor.
[0026] In a specific implementation scheme, it further includes a voltage stabilizing circuit, which is electrically connected to a common connection terminal between the seventh resistor R7 and the G terminal of the first MOS transistor Q1.
[0027] In a specific implementation scheme, it also includes a linear power supply circuit and a square wave generating circuit, wherein,
[0028] The first end of the linear power supply circuit is electrically connected to the voltage input end, and the second end of the linear power supply circuit is electrically connected to the first end of the square wave generating circuit;
[0029] The second end of the square wave generating circuit is electrically connected to the second capacitor plate of the ninth capacitor C9.
[0030] In a specific embodiment, a first diode D1 is further included, wherein:
[0031] The conducting end of the first diode D1 is electrically connected to the S end of the first MOS transistor Q1.
[0032] The cut-off end of the first diode D1 is electrically connected to the first end of the BOOST boost circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 A circuit diagram of a voltage suppression circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0034] The present application is further described in detail below through the accompanying drawings and embodiments. Through these descriptions, the characteristics and advantages of the present application will become clearer and more specific.
[0035] The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings are not necessarily drawn to scale unless otherwise noted.
[0036] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0037] To facilitate understanding of the voltage suppression circuit provided in the embodiment of the present application, its application scenario is first described. The voltage suppression circuit provided in the embodiment of the present application is used to realize the function of surge current suppression. The existing surge voltage suppression circuit has an output that is quickly established after the input end is turned on, and generates a large current spike on the subsequent capacitor, which does not meet the use requirements. For this reason, the embodiment of the present application provides a voltage suppression circuit to realize the function of surge current suppression. The following is a detailed description of the embodiment in conjunction with specific drawings.
[0038] refer to Figure 1 , Figure 1 This is a circuit diagram of a voltage suppression circuit provided in an embodiment of the present application. Figure 1 In the embodiment of the present application, a voltage suppression circuit is provided, including a first MOS tube Q1, a BOOST boost circuit and a voltage doubling circuit, wherein:
[0039] The D terminal of the first MOS transistor Q1 is electrically connected to the voltage input terminal, and the S terminal of the first MOS transistor Q1 is electrically connected to the voltage output terminal;
[0040] The first end of the voltage doubler circuit is electrically connected to the voltage input end, and the second end of the voltage doubler circuit is electrically connected to the G end of the first MOS transistor Q1;
[0041] The first end of the BOOST boost circuit is electrically connected to the S end of the first MOS transistor Q1 , and the second end of the BOOST boost circuit is electrically connected to the voltage input end.
[0042] In the above technical solution, by setting the first MOS tube Q1, the BOOST boost circuit and the voltage doubler circuit, wherein the D end of the first MOS tube Q1 is electrically connected to the voltage input end, and the S end of the first MOS tube Q1 is electrically connected to the voltage output end; the first end of the voltage doubler circuit is electrically connected to the voltage input end, and the second end of the voltage doubler circuit is electrically connected to the G end of the first MOS tube Q1; the first end of the BOOST boost circuit is electrically connected to the S end of the first MOS tube Q1, and the second end of the BOOST boost circuit is electrically connected to the voltage input end. After power-on, the voltage suppression circuit realizes the surge current suppression function by slowly establishing the gate circuit of the first MOS tube Q1.
[0043] In a specific implementation scheme, the voltage doubling circuit includes a seventh MOS transistor Q7, wherein:
[0044] The D terminal of the seventh MOS transistor Q7 is electrically connected to the G terminal of the first MOS transistor Q1 through a seventh resistor R7;
[0045] The G terminal of the seventh MOS transistor Q7 is electrically connected to the first capacitor plate of the ninth capacitor C9, and the second capacitor plate of the ninth capacitor C9 is electrically connected to the voltage input terminal;
[0046] The S terminal of the seventh MOS transistor Q7 is grounded.
[0047] In a specific implementation scheme, the voltage doubling circuit includes a rectifying unit and a filtering unit, wherein:
[0048] The first capacitor plate of the ninth capacitor C9 is electrically connected to the G terminal of the seventh MOS tube Q7 through the rectifying unit and the filtering unit in sequence.
[0049] refer to Figure 1 In a specific implementation scheme, the rectifying unit includes a field effect transistor Q8, wherein:
[0050] The first end of the field effect transistor Q8 is electrically connected to the first capacitor plate of the ninth capacitor C9;
[0051] The second end of the field effect transistor Q8 is electrically connected to the G end of the seventh MOS transistor Q7;
[0052] The third terminal of the field effect transistor Q8 is grounded.
[0053] exist Figure 1 In the embodiment, the field effect transistor Q8 includes a first diode and a second diode, the first end is a common connection end of a cut-off end of the first diode and a conduction end of the second diode; the second end is a conduction end of the first diode, and the third end is a cut-off end of the second diode.
[0054] In a specific implementation scheme, the filtering unit includes an eighth capacitor C8 and a sixteenth resistor R16 connected in parallel, wherein:
[0055] The first capacitor plate of the eighth capacitor C8 is electrically connected to the G terminal of the seventh MOS transistor Q7, and the second capacitor plate of the eighth capacitor C8 is grounded;
[0056] A first end of the sixteenth resistor R16 is electrically connected to the G end of the seventh MOS transistor Q7 , and a second end of the sixteenth resistor R16 is grounded.
[0057] In a specific implementation scheme, the voltage doubling circuit includes a fifteenth resistor R15, wherein:
[0058] The first end of the fifteenth resistor R15 is electrically connected to the S end of the seventh MOS transistor Q7.
[0059] A second end of the fifteenth resistor R15 is grounded.
[0060] In a specific implementation manner, the seventh MOS transistor Q7 is a depletion-type NMOS transistor.
[0061] In a specific implementation scheme, it further includes a voltage stabilizing circuit, which is electrically connected to a common connection terminal between the seventh resistor R7 and the G terminal of the first MOS transistor Q1.
[0062] In a specific implementation scheme, it also includes a linear power supply circuit and a square wave generating circuit, wherein:
[0063] The first end of the linear power supply circuit is electrically connected to the voltage input end, and the second end of the linear power supply circuit is electrically connected to the first end of the square wave generating circuit;
[0064] The second end of the square wave generating circuit is electrically connected to the second capacitor plate of the ninth capacitor C9.
[0065] In a specific embodiment, a first diode D1 is further included, wherein:
[0066] The conducting end of the first diode D1 is electrically connected to the S end of the first MOS transistor Q1.
[0067] The cut-off end of the first diode D1 is electrically connected to the first end of the BOOST boost circuit.
[0068] It should be noted that the specific structures of the linear power supply circuit, BOOST boost circuit, voltage stabilizing circuit and square wave generating circuit are not shown in the figure. Existing devices are used and the technology is formula. For details, please refer to relevant technical documents and will not be repeated here.
[0069] The voltage suppression circuit provided in the embodiment of the present application is designed to address the shortcomings of existing surge suppression circuits, and mainly includes a power supply circuit, a BOOST boost circuit, a voltage stabilization circuit, a square wave generation circuit, and a voltage doubling circuit. After the voltage suppression circuit is powered on, the surge current suppression function is achieved by slowly establishing the gate circuit of the first MOS tube Q1. The surge current suppression process is as follows:
[0070] The seventh MOS transistor Q7 is a depletion-type NMOS, and its gate-source voltage VGS(OFF) is -3.3V to -1.5V;
[0071] When the circuit is powered on normally, the seventh MOS transistor Q7 is in the on state, at which time the gate of the first MOS transistor Q1 of the main power transistor is pulled low, the first MOS transistor Q1 is not turned on, and the BOOST boost circuit performs boosting;
[0072] When the square wave generating circuit sends a square wave to the ninth capacitor C9 for charging and discharging, the electricity on the capacitor is rectified by the field effect tube Q8 and filtered by the eighth capacitor C8, generating a negative voltage on the sixteenth resistor R16, and the generated voltage is passed through the field effect tube Q8 to the ninth capacitor C9, and the square wave signal on the ninth capacitor C9 is superimposed on the rectification of the field effect tube Q8 and the filtering of the eighth capacitor C8, so as to slowly increase the negative voltage on the sixteenth resistor R16 (not exceeding the power supply voltage of the linear power supply circuit) to below -3.3V to -1.5V, and the seventh MOS tube Q7 is turned off, and the gate voltage on the first MOS tube Q1 of the main power tube is slowly established, and the first MOS tube Q1 is slowly turned on, so that the output is slowly established, and the output voltage is suppressed from generating a surge current in the subsequent capacitor;
[0073] When the circuit jumps to the surge state, the voltage stabilizing circuit clamps the gate voltage of the first MOS tube Q1, and the output voltage Vo=VG-VG(TH), thereby realizing the voltage limiting of the circuit.
[0074] It should be noted that VGS is the voltage between the gate and source of the field effect tube. In the field effect tube, VGS is an important parameter used to describe the voltage difference between the gate (G) and the source (S). The field effect tube is a semiconductor device that uses the electric field effect of the control input loop to control the output loop current. In addition to VGS, its main parameters include IDSS (saturated drain-source current), pinch-off voltage VP (sometimes also called threshold voltage Vt), maximum gate-source voltage VGS (max), maximum drain-source voltage VDS (max), etc.
[0075] During the operation of the field effect tube, the size of VGS will directly affect the conductive performance of the field effect tube. When VGS exceeds a certain threshold voltage, the field effect tube begins to conduct and the drain current begins to increase. Therefore, understanding and controlling VGS is crucial for the correct use and design of field effect tube circuits.
[0076] In addition, the field effect transistor has three main terminals, namely the gate G (gate), the drain D (drain) and the source S (source).
[0077] Among them, the gate G is the control terminal of the field effect tube, and the output current of the field effect tube can be controlled by changing the voltage of the gate. In an n-channel metal oxide semiconductor field effect transistor (n-mosfet), the gate is a piece of metal that forms an inversion shape on the pn junction.
[0078] The drain D is the output terminal of the field effect tube, which controls the field effect tube to enter the conduction state and is the output terminal of the electrons in the field effect tube. In n-mosfet, the drain is a conductor connected to the negative electrode.
[0079] The source S is the input terminal of the field effect transistor and is responsible for the current flowing through the output load. In n-mosfet, the source is a conductor connected to the n-type semiconductor region.
[0080] One thing to note here is that all FETs except the JFET have a fourth terminal, called the body, base, bulk, or substrate. This fourth terminal can modulate the transistor into operation. In circuit design, the body terminal rarely plays a big role, but its existence is important when physically designing an integrated circuit.
[0081] Those skilled in the art will appreciate that the present application may be implemented as a system, method or computer program product.
[0082] Therefore, the present disclosure may be specifically implemented in the following forms, namely: it may be completely hardware, it may be completely software (including firmware, resident software, microcode, etc.), or it may be a combination of hardware and software, generally referred to herein as a "circuit", "module" or "system". In addition, in some embodiments, the present application may also be implemented in the form of a computer program product in one or more computer-readable media, and the computer-readable medium may contain computer-readable program code.
[0083] Any combination of one or more computer-readable media can be used. Computer-readable media can be computer-readable signal media or computer-readable storage media. Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any combination of the above. More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connections with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above. In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.
[0084] Although the embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present application. On this basis, a variety of replacements and improvements can be made to the present application, all of which fall within the scope of protection of the present application.
Claims
1. A voltage suppression circuit, characterized in that: It includes a first MOS tube Q1, a BOOST boost circuit and a voltage doubling circuit, wherein: The D terminal of the first MOS transistor Q1 is electrically connected to the voltage input terminal, and the S terminal of the first MOS transistor Q1 is electrically connected to the voltage output terminal; The first end of the voltage doubler circuit is electrically connected to the voltage input end, and the second end of the voltage doubler circuit is electrically connected to the G end of the first MOS transistor Q1; The first end of the BOOST boost circuit is electrically connected to the S end of the first MOS transistor Q1 , and the second end of the BOOST boost circuit is electrically connected to the voltage input end.
2. The voltage suppression circuit according to claim 1, characterized in that: The voltage doubler circuit includes a seventh MOS tube Q7, wherein: The D terminal of the seventh MOS transistor Q7 is electrically connected to the G terminal of the first MOS transistor Q1 through a seventh resistor R7; The G terminal of the seventh MOS transistor Q7 is electrically connected to the first capacitor plate of the ninth capacitor C9, and the second capacitor plate of the ninth capacitor C9 is electrically connected to the voltage input terminal; The S terminal of the seventh MOS transistor Q7 is grounded.
3. The voltage suppression circuit according to claim 2, characterized in that: The voltage doubler circuit includes a rectifying unit and a filtering unit, wherein: The first capacitor plate of the ninth capacitor C9 is electrically connected to the G terminal of the seventh MOS tube Q7 through the rectifying unit and the filtering unit in sequence.
4. The voltage suppression circuit according to claim 3, characterized in that: The rectifying unit includes a field effect transistor Q8, wherein: The first end of the field effect transistor Q8 is electrically connected to the first capacitor plate of the ninth capacitor C9; The second end of the field effect transistor Q8 is electrically connected to the G end of the seventh MOS transistor Q7; The third terminal of the field effect transistor Q8 is grounded.
5. The voltage suppression circuit according to claim 4, characterized in that: The filtering unit includes an eighth capacitor C8 and a sixteenth resistor R16 connected in parallel, wherein: The first capacitor plate of the eighth capacitor C8 is electrically connected to the G terminal of the seventh MOS transistor Q7, and the second capacitor plate of the eighth capacitor C8 is grounded; A first end of the sixteenth resistor R16 is electrically connected to the G end of the seventh MOS transistor Q7 , and a second end of the sixteenth resistor R16 is grounded.
6. The voltage suppression circuit according to claim 5, characterized in that: The voltage doubling circuit includes a fifteenth resistor R15, wherein: The first end of the fifteenth resistor R15 is electrically connected to the S end of the seventh MOS transistor Q7. A second end of the fifteenth resistor R15 is grounded.
7. The voltage suppression circuit according to claim 6, characterized in that: The seventh MOS transistor Q7 is a depletion-type NMOS transistor.
8. The voltage suppression circuit according to any one of claims 2 to 7, characterized in that: It also includes a voltage stabilizing circuit, which is electrically connected to a common connection terminal between the seventh resistor R7 and the G terminal of the first MOS transistor Q1.
9. The voltage suppression circuit according to any one of claims 2 to 7, characterized in that: It also includes a linear power supply circuit and a square wave generating circuit, wherein: The first end of the linear power supply circuit is electrically connected to the voltage input end, and the second end of the linear power supply circuit is electrically connected to the first end of the square wave generating circuit; The second end of the square wave generating circuit is electrically connected to the second capacitor plate of the ninth capacitor C9.
10. The voltage suppression circuit according to any one of claims 1 to 7, characterized in that: Also includes a first diode D1, wherein, The conducting end of the first diode D1 is electrically connected to the S end of the first MOS transistor Q1. The cut-off end of the first diode D1 is electrically connected to the first end of the BOOST boost circuit.