Control circuit and switching power supply

Abstract

The utility model discloses a control circuit and a switching power supply. The control circuit comprises a driving circuit and an interlocking circuit. The input end of the interlock circuit is connected with the power supply end of the drive circuit, the first control end is connected with the first input end of the drive circuit, the second control end is connected with the second input end of the drive circuit, the first output end is connected with the first enable signal input end of the drive circuit, and the second output end is connected with the second enable signal input end of the drive circuit; when the control circuit works and the first driving signal is at a high level, the first driving signal controls the interlocking circuit to pull down the level of the second enable signal input end of the driving circuit to a low level, so that the second output end of the driving circuit can only output the low level; and when the second driving signal is at a high level, the second driving signal controls the interlock circuit to pull down the level of the first enable signal input end of the driving circuit to a low level, so that the first output end of the driving circuit can only output the low level. According to the utility model, the power level circuit can be effectively prevented from being short-circuited to fail.

Description

Technical Field

[0001] The utility model relates to the field of switch converters, in particular to a control circuit and a switch power supply. Background Art

[0002] Half-bridge circuits or full-bridge circuits formed by MOS tubes are often used in circuit designs such as switching power supplies. For the control of the MOS tubes in the half-bridge circuits or full-bridge circuits, it is necessary to avoid the situation where the upper and lower bridges are turned on at the same time.

[0003] As the application environment of switching power supplies becomes increasingly harsh, especially in some places with high grid noise, when the grid voltage jumps or surge voltage is injected, these interferences may cause the reset or control signal of DSP (Digital Signal Processing) to be distorted. When the DSP is reset or the control signal is distorted, the drive signal may be abnormal. The abnormal drive signal may cause the power stage circuit to short-circuit and fail. Therefore, when designing the control circuit, we need to ensure that when the DSP drive signal is abnormal, the abnormal drive signal cannot be sent to the gate of the power MOS to avoid causing the power stage circuit to short-circuit and fail. Utility Model Content

[0004] In view of this, the technical problem to be solved by the present invention is to provide a control circuit and a switching power supply, which can effectively prevent the power stage circuit from short-circuiting and failing.

[0005] As a first aspect of the present invention, the technical solution of the control circuit provided is as follows:

[0006] A control circuit, comprising: a drive circuit and an interlock circuit;

[0007] The first input end of the drive circuit is used to input a first drive signal, the second input end is used to input a second drive signal, the power supply end is used to input a power supply voltage, the ground end is used for grounding, the first output end is used to output a signal amplified by the first drive signal, and the second output end is used to output a signal amplified by the second drive signal; the input end of the interlock circuit is connected to the power supply end of the drive circuit, the first control end is connected to the first input end of the drive circuit, the second control end is connected to the second input end of the drive circuit, the first output end is connected to the first enable signal input end of the drive circuit, the second output end is connected to the second enable signal input end of the drive circuit, and the ground end is connected to the ground end of the drive circuit;

[0008] When the control circuit is working, when the first drive signal is at a high level, the first drive signal controls the interlock circuit to pull down the level of the second enable signal input terminal of the drive circuit to a low level, so that the second output terminal of the drive circuit can only output a low level; when the second drive signal is at a high level, the second drive signal controls the interlock circuit to pull down the level of the first enable signal input terminal of the drive circuit to a low level, so that the first output terminal of the drive circuit can only output a low level.

[0009] Preferably, the driving circuit includes a voltage driving chip SGM48524 of Shengbangwei, a voltage driving chip UCC27524 of Texas Instruments, or a voltage driving chip UCC27525 of Texas Instruments.

[0010] Preferably, the interlocking circuit includes a resistor R1, a resistor R2, a transistor Q1 and a transistor Q2; one end of the resistor R1 and one end of the resistor R2 are simultaneously connected to the input end of the interlocking circuit, the other end of the resistor R2 and the collector of the transistor Q1 are simultaneously connected to the first output end of the interlocking circuit, the other end of the resistor R1 and the collector of the transistor Q2 are simultaneously connected to the second output end of the interlocking circuit, the gate of the transistor Q1 is connected to the first control end of the interlocking circuit, the gate of the transistor Q2 is connected to the second control end of the interlocking circuit, and the emitter of the transistor Q1 and the emitter of the transistor Q2 are simultaneously connected to the ground end of the interlocking circuit.

[0011] Furthermore, the control circuit also includes a resistor R3, a resistor R4 and a capacitor C1, one end of the resistor R4 is used to input a first drive signal, the other end of the resistor R4 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the first input end of the drive circuit, and the other end of the resistor R3 and the other end of the capacitor C1 are simultaneously connected to the ground end of the drive circuit.

[0012] Furthermore, the control circuit also includes a resistor R5, a resistor R6 and a capacitor C3, one end of the resistor R5 is used to input a second drive signal, the other end of the resistor R5 is simultaneously connected to one end of the resistor R6, one end of the capacitor C3 and the second input end of the drive circuit, and the other end of the resistor R6 and the other end of the capacitor C3 are simultaneously connected to the ground end of the drive circuit.

[0013] Furthermore, the control circuit further includes a capacitor C2, and the capacitor C2 is connected between a power supply terminal of the drive circuit and a ground terminal of the drive circuit.

[0014] Furthermore, the control circuit also includes a resistor R3, a resistor R4 and a capacitor C1, one end of the resistor R4 is used to input a first drive signal, the other end of the resistor R4 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the first input end of the drive circuit, and the other end of the resistor R3 and the other end of the capacitor C1 are simultaneously connected to the ground end of the drive circuit; the control circuit also includes a resistor R5, a resistor R6 and a capacitor C3, one end of the resistor R5 is used to input a second drive signal, the other end of the resistor R5 is simultaneously connected to one end of the resistor R6, one end of the capacitor C3 and the second input end of the drive circuit, and the other end of the resistor R6 and the other end of the capacitor C3 are simultaneously connected to the ground end of the drive circuit; the control circuit also includes a capacitor C2, and the capacitor C2 is connected between the power supply end of the drive circuit and the ground end of the drive circuit.

[0015] As a second aspect of the present invention, the technical solution of the embodiment of the switching power supply provided is as follows:

[0016] A switching power supply, comprising two switching tubes, wherein the two switching tubes are not turned on at the same time, wherein: the switching power supply comprises the control circuit described in any one of the first aspects above, and the control circuit is used to control the conduction and disconnection of the two switching tubes.

[0017] Compared with the direct drive solution of the prior art, the utility model has the following beneficial effects:

[0018] The control circuit of the embodiment of the utility model adds an interlock circuit on the basis of the driving circuit. When the first driving signal is at a high level, the first driving signal controls the interlock circuit to pull down the level of the second enable signal input terminal of the driving circuit to a low level, so that the second output terminal of the driving circuit can only output a low level; when the second driving signal is at a high level, the second driving signal controls the interlock circuit to pull down the level of the first enable signal input terminal of the driving circuit to a low level, so that the first output terminal of the driving circuit can only output a low level, thereby effectively preventing the power stage circuit of the switching power supply from short circuiting and failing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a schematic diagram of a specific control circuit of the first embodiment of the utility model. DETAILED DESCRIPTION

[0020] In order to make the above-mentioned purposes, features and advantages of the utility model more obvious and easy to understand, the specific implementation methods of the utility model are described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the utility model, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0021] It should be noted that the terms "including" and "having" and any variations thereof described in the specification and claims of the present application are intended to cover non-exclusive inclusions. For example, the inclusion of a series of components, unit circuits or control timings is not necessarily limited to those components, unit circuits or control timings clearly listed, but may include components, unit circuits or control timings that are not clearly listed or inherent to these circuits.

[0022] In addition, the embodiments and features of the embodiments in this application may be combined with each other if there is no conflict.

[0023] It should be understood that, in the specification and the claims, when an element is described as being “connected” to another element, the element may be “directly connected” to the other element, or be “connected” to the other element through a third element; when a step is described as being continued to another step, the step may be directly continued to the other step, or be continued to the other step through a third step.

[0024] First embodiment

[0025] This embodiment provides a control circuit, which includes: a drive circuit and an interlocking circuit;

[0026] The first input terminal of the driving circuit is used to input the first driving signal Drv_A, the second input terminal is used to input the second driving signal Drv_B, the power supply terminal is used to input the power supply voltage VCC, the ground terminal is used to connect to the ground GND, the first output terminal is used to output the signal Out_A after amplifying the first driving signal, and the second output terminal is used to output the signal Out_B after amplifying the second driving signal; the input terminal of the interlocking circuit is connected to the power supply terminal VCC of the driving circuit, the first control terminal is connected to the first input terminal INA of the driving circuit, the second control terminal is connected to the second input terminal INB of the driving circuit, the first output terminal is connected to the first enable signal input terminal ENA of the driving circuit, the second output terminal is connected to the second enable signal input terminal ENB of the driving circuit, and the ground terminal is connected to the ground terminal GND of the driving circuit;

[0027] When the control circuit is working, when the first drive signal is at a high level, the first drive signal controls the interlock circuit to pull down the level of the second enable signal input terminal of the drive circuit to a low level, so that the second output terminal of the drive circuit can only output a low level; when the second drive signal is at a high level, the second drive signal controls the interlock circuit to pull down the level of the first enable signal input terminal of the drive circuit to a low level, so that the first output terminal of the drive circuit can only output a low level.

[0028] The control circuit of the embodiment of the utility model adds an interlock circuit on the basis of the drive circuit. When the first drive signal is at a high level, the first drive signal controls the interlock circuit to pull down the level of the second enable signal input terminal of the drive circuit to a low level, so that the second output terminal of the drive circuit can only output a low level; when the second drive signal is at a high level, the second drive signal controls the interlock circuit to pull down the level of the first enable signal input terminal of the drive circuit to a low level, so that the first output terminal of the drive circuit can only output a low level, thereby effectively preventing the power stage circuit from short-circuiting and failing.

[0029] Preferably, the driving circuit includes a voltage driving chip SGM48524 of Shengbangwei, a voltage driving chip UCC27524 of Texas Instruments, or a voltage driving chip UCC27525 of Texas Instruments. These chips are dual-channel low-side gate driving chips, which are used to convert low voltage signals into high voltage signals. The pins of these chips are compatible and are defined as follows:

[0030] Pin 1: Enable signal input pin ENA of channel 1;

[0031] Pin 2: Primary low voltage signal input pin INA of channel 1;

[0032] Pin 7: secondary side high voltage signal output pin OUTA of channel 1;

[0033] Pin 3: Chip ground pin GND;

[0034] Pin 6: Chip power supply pin VCC;

[0035] Pin 8: Enable signal input pin ENB of channel 2;

[0036] Pin 4: primary low voltage signal input pin INB of channel 2;

[0037] Pin 5: Secondary side high voltage signal output pin OUTB of channel 2.

[0038] Figure 1 This is a schematic diagram of a specific control circuit of the first embodiment of the utility model, see Figure 1, wherein the interlocking circuit includes a resistor R1, a resistor R2, a transistor Q1 and a transistor Q2; one end of the resistor R1 and one end of the resistor R2 are simultaneously connected to the input end of the interlocking circuit, the other end of the resistor R2 and the collector of the transistor Q1 are simultaneously connected to the first output end of the interlocking circuit, the other end of the resistor R1 and the collector of the transistor Q2 are simultaneously connected to the second output end of the interlocking circuit, the gate of the transistor Q1 is connected to the first control end of the interlocking circuit, the gate of the transistor Q2 is connected to the second control end of the interlocking circuit, and the emitter of the transistor Q1 and the emitter of the transistor Q2 are simultaneously connected to the ground end of the interlocking circuit.

[0039] Please continue to see Figure 1 , wherein the control circuit further includes a resistor R3, a resistor R4 and a capacitor C1, one end of the resistor R4 is used to input the first drive signal, the other end of the resistor R4 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the first input end of the drive circuit, and the other end of the resistor R3 and the other end of the capacitor C1 are simultaneously connected to the ground end of the drive circuit. The purpose of adding the resistor R3, the resistor R4 and the capacitor C1 to the control circuit is to filter out high-frequency noise and keep the DC bias basically unchanged.

[0040] Please continue to see Figure 1 , wherein the control circuit further includes a resistor R5, a resistor R6 and a capacitor C3, one end of the resistor R5 is used to input the second drive signal, the other end of the resistor R5 is simultaneously connected to one end of the resistor R6, one end of the capacitor C3 and the second input end of the drive circuit, and the other end of the resistor R6 and the other end of the capacitor C3 are simultaneously connected to the ground end of the drive circuit. The purpose of adding the resistor R5, the resistor R6 and the capacitor C3 to the control circuit is to filter out high-frequency noise and keep the DC bias basically unchanged.

[0041] Please continue to see Figure 1 The control circuit further includes a capacitor C2, which is connected between the power supply terminal of the drive circuit and the ground terminal of the drive circuit. The control circuit adds capacitor C2 for the purpose of energy storage and filtering, so that the chip U1 works in a stable and reliable state.

[0042] Figure 1 The working principle of the circuit is analyzed as follows:

[0043] When Drv_A is at a high level, transistor Q2 is turned on, and the enable signal ENB at pin 8 of the voltage driver chip U1 is at a low level. When the enable signal ENB is at a low level, no matter whether Drv_B is at a high level or a low level, the output signal Out_B corresponding to Drv_B remains at a low level. Therefore, as long as Drv_A is at a high level, the output signal Out_B corresponding to Drv_B is at a low level, then there will not be a situation where Out_A and Out_B are at high levels at the same time, so there will be no direct pass of the interlocked power tube; when Drv_B is at a high level, transistor Q1 is turned on, and the enable signal ENA at pin 1 of the voltage driver chip U1 is at a low level. When the enable signal ENA is at a low level No matter Drv_A is at a high level or a low level, the output signal Out_A corresponding to Drv_A remains at a low level. Therefore, as long as Drv_B is at a high level, the output signal Out_A corresponding to Drv_A is at a low level. Then, there will not be a situation where Out_A and Out_B are at high levels at the same time, and therefore, the interlocking power tube will not be directly connected. Therefore, after using this hardware interlocking circuit, even if Drv_A and Drv_B are abnormal in the DSP driving situation, the output signals Out_A and Out_B will not be at high levels at the same time, and therefore, the interlocking power tube will not fail due to directly connected, which can greatly improve the reliability of the power control circuit.

[0044] Second embodiment

[0045] This embodiment provides a switching power supply, which includes two switching tubes, and the two switching tubes are not turned on at the same time, wherein: the switching power supply includes any control circuit in the first embodiment, and the control circuit is used to control the conduction and shutdown of the two switching tubes.

[0046] The switching power supply of this embodiment includes any one of the control circuits in the first embodiment to control the on and off of the two switching tubes, thereby effectively preventing the power stage circuit from failing due to a short circuit.

[0047] The above are only implementation methods of the utility model, and those skilled in the art to which the utility model belongs may also make changes and modifications to the above specific implementation methods. Therefore, the utility model is not limited to the specific control methods disclosed and described above, and some modifications and changes to the utility model should also fall within the scope of protection of the claims of the utility model. In addition, although some specific terms are used in this specification, these terms are only for the convenience of explanation and do not constitute any limitation to the utility model.

Claims

1. A control circuit, characterized in that: include: Drive circuit and interlock circuit; The first input end of the drive circuit is used to input a first drive signal, the second input end is used to input a second drive signal, the power supply end is used to input a power supply voltage, the ground end is used for grounding, the first output end is used to output a signal amplified by the first drive signal, and the second output end is used to output a signal amplified by the second drive signal; the input end of the interlock circuit is connected to the power supply end of the drive circuit, the first control end is connected to the first input end of the drive circuit, the second control end is connected to the second input end of the drive circuit, the first output end is connected to the first enable signal input end of the drive circuit, the second output end is connected to the second enable signal input end of the drive circuit, and the ground end is connected to the ground end of the drive circuit; When the control circuit is working, when the first drive signal is at a high level, the first drive signal controls the interlock circuit to pull down the level of the second enable signal input terminal of the drive circuit to a low level, so that the second output terminal of the drive circuit can only output a low level; when the second drive signal is at a high level, the second drive signal controls the interlock circuit to pull down the level of the first enable signal input terminal of the drive circuit to a low level, so that the first output terminal of the drive circuit can only output a low level.

2. The control circuit according to claim 1, characterized in that: The driving circuit includes a voltage driving chip SGM48524 of Shengbangwei, a voltage driving chip UCC27524 of Texas Instruments, or a voltage driving chip UCC27525 of Texas Instruments.

3. The control circuit according to claim 1, characterized in that: The interlocking circuit includes a resistor R1, a resistor R2, a transistor Q1 and a transistor Q2; one end of the resistor R1 and one end of the resistor R2 are simultaneously connected to the input end of the interlocking circuit, the other end of the resistor R2 and the collector of the transistor Q1 are simultaneously connected to the first output end of the interlocking circuit, the other end of the resistor R1 and the collector of the transistor Q2 are simultaneously connected to the second output end of the interlocking circuit, the gate of the transistor Q1 is connected to the first control end of the interlocking circuit, the gate of the transistor Q2 is connected to the second control end of the interlocking circuit, and the emitter of the transistor Q1 and the emitter of the transistor Q2 are simultaneously connected to the ground end of the interlocking circuit.

4. The control circuit according to any one of claims 1 to 3, characterized in that: The control circuit also includes a resistor R3, a resistor R4 and a capacitor C1, one end of the resistor R4 is used to input a first drive signal, the other end of the resistor R4 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the first input end of the drive circuit, and the other end of the resistor R3 and the other end of the capacitor C1 are simultaneously connected to the ground end of the drive circuit.

5. The control circuit according to any one of claims 1 to 3, characterized in that: The control circuit also includes a resistor R5, a resistor R6 and a capacitor C3, one end of the resistor R5 is used to input a second drive signal, the other end of the resistor R5 is simultaneously connected to one end of the resistor R6, one end of the capacitor C3 and the second input end of the drive circuit, and the other end of the resistor R6 and the other end of the capacitor C3 are simultaneously connected to the ground end of the drive circuit.

6. The control circuit according to any one of claims 1 to 3, characterized in that: The control circuit further includes a capacitor C2, and the capacitor C2 is connected between a power supply terminal of the drive circuit and a ground terminal of the drive circuit.

7. The control circuit according to any one of claims 1 to 3, characterized in that: The control circuit further includes a resistor R3, a resistor R4 and a capacitor C1, one end of the resistor R4 is used to input a first drive signal, the other end of the resistor R4 is simultaneously connected to one end of the resistor R3, one end of the capacitor C1 and the first input end of the drive circuit, and the other end of the resistor R3 and the other end of the capacitor C1 are simultaneously connected to the ground end of the drive circuit; The control circuit further includes a resistor R5, a resistor R6 and a capacitor C3, one end of the resistor R5 is used to input the second drive signal, the other end of the resistor R5 is simultaneously connected to one end of the resistor R6, one end of the capacitor C3 and the second input end of the drive circuit, and the other end of the resistor R6 and the other end of the capacitor C3 are simultaneously connected to the ground end of the drive circuit; The control circuit further includes a capacitor C2, and the capacitor C2 is connected between a power supply terminal of the drive circuit and a ground terminal of the drive circuit.

8. A switching power supply, comprising two switching tubes, wherein the two switching tubes are not turned on at the same time, characterized in that: The switching power supply comprises the control circuit according to any one of claims 1 to 7, and the control circuit is used to control the on and off of the two switching tubes.

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