Parallel MOS tube driving circuit

Abstract

The utility model relates to a parallel MOS (Metal Oxide Semiconductor) tube driving circuit, which comprises a digital isolation unit, a negative voltage bias driving unit and a plurality of MOS tube driving units, and is characterized in that the negative voltage bias driving unit comprises a silicon carbide MOS tube driving chip U2 with the model of IVCR1401; the input end of the digital isolation unit is used for accessing a driving signal, the output end of the digital isolation unit is electrically connected with the logic input end of the silicon carbide MOS tube driving chip U2, and the driving output end of the silicon carbide MOS tube driving chip U2 is electrically connected with the input ends of the MOS tube driving units. The negative voltage output end of the silicon carbide MOS tube driving chip U2 is electrically connected with the input ends of the MOS tube driving units through the series capacitor C6, and the output ends of the MOS tube driving units are used for being connected with grid electrodes of MOS tubes. According to the utility model, the IVCR1401 silicon carbide MOS tube driving chip is utilized to provide driving signals for each MOS tube driving unit, so that the whole driving circuit has the functions of negative voltage turn-off, short circuit protection, fault output and the like.

Description

Technical Field

[0001] The utility model relates to the technical field of drive circuits, in particular to a parallel MOS tube drive circuit. Background Art

[0002] In the application of parallel driving of multiple MOS tubes, the solution of the prior art is to use multiple driving circuits to drive multiple MOS tubes respectively, that is, to transmit the driving signal to each driving circuit respectively, and drive the corresponding MOS tube through each driving circuit. The traditional MOS tube driving circuit only has the functions of negative voltage shutdown and constant current driving, without short circuit protection, fault output and dynamic current sharing of multiple tubes in parallel. Utility Model Content

[0003] In order to solve the technical problems in the prior art that the MOS tube driving circuit does not have short circuit protection, fault output and multi-tube parallel dynamic current sharing function, the utility model provides a parallel MOS tube driving circuit.

[0004] The technical solution of the utility model to solve the above technical problems is as follows:

[0005] A parallel MOS tube driving circuit comprises a digital isolation unit, a negative voltage bias driving unit and a plurality of MOS tube driving units, wherein the negative voltage bias driving unit comprises a silicon carbide MOS tube driving chip U2 of model IVCR1401; an input end of the digital isolation unit is used to access a driving signal, an output end of the digital isolation unit is electrically connected to a logic input end of the silicon carbide MOS tube driving chip U2, a driving output end of the silicon carbide MOS tube driving chip U2 is electrically connected to input ends of a plurality of the MOS tube driving units, a negative voltage output end of the silicon carbide MOS tube driving chip U2 is electrically connected to input ends of a plurality of the MOS tube driving units through a series capacitor C6, and an output end of the MOS tube driving unit is used to connect a gate of the MOS tube.

[0006] The beneficial effect of the utility model is as follows: by adopting the silicon carbide MOS tube driver chip U2 of model IVCR1401 to output driving signals to multiple MOS tube driver units respectively, and using each MOS tube driver unit to drive the MOS tube, since the IVCR1401 silicon carbide MOS tube driver chip has the functions of negative pressure shutdown, short circuit protection, fault output, etc., therefore, by using the IVCR1401 silicon carbide MOS tube driver chip to provide driving signals for each MOS tube driver unit, the entire driving circuit can have the functions of negative pressure shutdown, short circuit protection, fault output, etc.

[0007] On the basis of the above technical solution, the present invention can also be improved as follows.

[0008] Furthermore, the negative voltage bias driving unit also includes a voltage divider circuit, which includes a resistor R5, one end of the resistor R5 is electrically connected to the driving output end of the silicon carbide MOS tube driving chip U2, one end of the capacitor C6 is electrically connected to the negative voltage output end of the silicon carbide MOS tube driving chip U2, the other end of the resistor R5 is electrically connected to the other end of the capacitor C6, and the other end of the capacitor C6 is electrically connected to the input ends of the multiple MOS tube driving units respectively.

[0009] The beneficial effect of adopting the above further scheme is that by adding a voltage-dividing resistor R5 between the silicon carbide MOS tube driver chip U2OUT pin and the negative voltage capacitor C6, during the charging process, since the resistor R5 shares a certain voltage, a signal is taken at the connection point of the resistor R5 and the capacitor C6. At this time, the maximum voltage is less than 1.6V, which is lower than the input high-level threshold voltage of the MOS tube driver unit 1.9V. Therefore, the output section of the MOS tube driver unit can still maintain a low level.

[0010] Furthermore, the negative voltage bias driving unit also includes a relay protection circuit, which includes an ultra-fast recovery diode D2 and a Schottky diode D3, the other end of the capacitor C6 is electrically connected to the positive electrode of the ultra-fast recovery diode D2 and the negative electrode of the Schottky diode D3, respectively, the negative electrode of the ultra-fast recovery diode D2 is electrically connected to the positive electrode of the Schottky diode D3, and the negative electrode of the ultra-fast recovery diode D2 or the positive electrode of the Schottky diode D3 is electrically connected to the input end of the plurality of MOS tube driving units.

[0011] The beneficial effect of adopting the above further solution is that, by providing a relay protection circuit composed of an ultrafast recovery diode D2 and a Schottky diode D3, the input level of the MOS tube driving unit can be further reduced.

[0012] Furthermore, the MOS tube driving unit includes a MOS tube driving chip with model IVCR1412BD, the input end of the MOS tube driving chip is electrically connected to the cathode of the ultrafast recovery diode D2 or the anode of the Schottky diode D3, the pull-up output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube through a front negative voltage capacitor connected in series, the negative voltage output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube, the power supply end of the MOS tube driving chip is connected to the power supply, and the ground end of the MOS tube driving chip is grounded.

[0013] The beneficial effect of adopting the above further scheme is that, due to the parallel connection of multiple power tubes, the load capacity of the MOS tube driver chip with model IVCR1412BD is limited, and the spatial distribution of the MOS tubes on the surface layout causes each MOS tube to be at a different distance from the MOS tube driver chip. Therefore, the silicon carbide MOS tube driver chip U2 with model IVCR1401 does not directly drive the MOS tube, but outputs the signal to multiple MOS tube driver chips through the OUT pin, and the multiple MOS tube driver chips respectively drive the corresponding MOS tubes. In this way, multiple MOS tube driver chips on the layout can be placed close to the corresponding MOS tubes to reduce interference.

[0014] Furthermore, the negative voltage bias driving unit also includes a protection withdrawal and detection peripheral circuit, which includes a diode D1, a resistor R4, a diode D4 and a resistor R3, the cathode of the diode D1 is used to connect the drain of the MOS tube, the anode of the diode D1 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is electrically connected to the desaturation detection input end of the silicon carbide MOS tube driver chip U2, the desaturation detection input end of the silicon carbide MOS tube driver chip U2 is electrically connected to the cathode of the diode D4, the anode of the diode D4 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is grounded.

[0015] The beneficial effect of adopting the above further solution is that by setting the protection withdrawal and detection peripheral circuit, when a short circuit or overcurrent occurs, the drain or collector current of the MOS tube may increase to a very high value, thereby causing the silicon carbide MOS tube driver chip U2 to exit the saturation state.

[0016] Further, the digital isolation unit includes a dual-channel digital isolator U1, the dual-channel digital isolator U1 includes a first channel input end, a first channel output end, a second channel input end, and a second channel output end, the first channel output end of the dual-channel digital isolator U1 is used to output a fault signal, the first channel input end of the dual-channel digital isolator U1 is electrically connected to the fault output end of the silicon carbide MOS tube driver chip U2, the second channel input end of the dual-channel digital isolator U1 is connected to the drive signal through a series resistor R1, the second channel output end of the dual-channel digital isolator U1 is electrically connected to the logic input end of the silicon carbide MOS tube driver chip U2, the primary power supply end of the dual-channel digital isolator U1 is connected to the power supply, the secondary power supply end of the dual-channel digital isolator U1 is electrically connected to the power supply output end of the silicon carbide MOS tube driver chip U2, and the primary grounding end and the secondary grounding end of the dual-channel digital isolator U1 are both grounded.

[0017] The beneficial effect of adopting the above further solution is that, by setting up a dual-channel digital isolator U1, one channel can be used to transmit the drive signal and the other channel can be used to feed back the fault signal, thereby realizing isolated transmission of the drive signal and the fault signal.

[0018] Furthermore, the digital isolation unit also includes an isolator filter circuit, which includes a capacitor C1, a capacitor C2 and a capacitor C3, one end of the capacitor C1 is electrically connected to the second channel input terminal of the dual-channel digital isolator U1, and the other end of the capacitor C1 is grounded; one end of the capacitor C2 is electrically connected to the primary power supply terminal of the dual-channel digital isolator U1, and the other end of the capacitor C2 is grounded; one end of the capacitor C3 is electrically connected to the secondary power supply terminal of the dual-channel digital isolator U1, and the other end of the capacitor C3 is grounded.

[0019] The beneficial effect of adopting the above further solution is that the power supply stability is improved by providing an isolator filter circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a circuit principle block diagram of the utility model;

[0021] Figure 2 This is a circuit diagram of the utility model. DETAILED DESCRIPTION

[0022] The principles and features of the present invention are described below in conjunction with the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0023] like Figure 1 As shown, this embodiment provides a parallel MOS tube driving circuit, including a digital isolation unit, a negative voltage bias driving unit and a plurality of MOS tube driving units, wherein the negative voltage bias driving unit includes a silicon carbide MOS tube driving chip U2 of model IVCR1401; the input end of the digital isolation unit is used to access the driving signal, the output end of the digital isolation unit is electrically connected to the logic input end of the silicon carbide MOS tube driving chip U2, the driving output end of the silicon carbide MOS tube driving chip U2 is electrically connected to the input ends of the plurality of MOS tube driving units respectively, the negative voltage output end of the silicon carbide MOS tube driving chip U2 is electrically connected to the input ends of the plurality of MOS tube driving units respectively through a series capacitor C6, and the output end of the MOS tube driving unit is used to connect the gate of the MOS tube.

[0024] like Figure 2As shown, the negative voltage bias driving unit also includes a voltage divider circuit, which includes a resistor R5, one end of which is electrically connected to the driving output end of the silicon carbide MOS tube driving chip U2, one end of which is electrically connected to the negative voltage output end of the silicon carbide MOS tube driving chip U2, the other end of which is electrically connected to the other end of the capacitor C6, and the other end of which is electrically connected to the input ends of the plurality of MOS tube driving units. By adding a voltage divider resistor R5 between the OUT pin of the silicon carbide MOS tube driving chip U2 and the negative voltage capacitor C6, during the charging process, since the resistor R5 shares a certain voltage, a signal is taken at the connection point between the resistor R5 and the capacitor C6, and at this time, the maximum voltage is less than 1.6V, which is lower than the input high level threshold voltage of the MOS tube driving unit 1.9V, so the output section of the MOS tube driving unit can still maintain a low level.

[0025] Specifically, the negative voltage bias driving unit further includes a relay protection circuit, the relay protection circuit includes an ultra-fast recovery diode D2 and a Schottky diode D3, the other end of the capacitor C6 is electrically connected to the positive electrode of the ultra-fast recovery diode D2 and the negative electrode of the Schottky diode D3, the negative electrode of the ultra-fast recovery diode D2 is electrically connected to the positive electrode of the Schottky diode D3, and the negative electrode of the ultra-fast recovery diode D2 or the positive electrode of the Schottky diode D3 is electrically connected to the input end of the plurality of MOS tube driving units. By providing a relay protection circuit composed of the ultra-fast recovery diode D2 and the Schottky diode D3, the input level of the MOS tube driving unit can be further reduced.

[0026] In order to further reduce the input level of the MOS tube driver core of model IVCR1412 and ensure reliability, two diodes connected in parallel opposite to each other are added in front of the signal input end of the MOS tube driver core of model IVCR1412, that is, pin 6. Diode D2 uses an ultra-fast recovery diode. The signal level input to the MOS tube driver core of model IVCR1412 will produce a voltage drop of about 0.6V on this diode, so the false trigger signal level transmitted to the MOS tube driver core of model IVCR1412 has been reduced to about 1V, which is less than the low level threshold voltage of 1.2V of the MOS tube driver core of model IVCR1412. It can ensure that the MOS tube driver core of model IVCR1412 is not triggered at this time, outputs a low level, and keeps the power tube off. In normal operation, the high level amplitude of the signal output by the OUT pin is about 2.1V. After the above voltage divider circuit, the signal level sent to the MOS tube driver core of model IVCR1412 is also about 20V, so the above circuit does not affect the transmission of normal high level. When the OUT pin, i.e. the 6th pin of the silicon carbide MOS tube driver chip U2, outputs a low level, the output signal of the MOS tube driver core model IVCR1412 is pulled down through the diode D3, so the diode D3 should be a Schottky diode with a low conduction voltage drop. At this time, the voltage drop on the diode D3 is about 0.3V, which is much smaller than the low-level threshold voltage of 1.2V of the MOS tube driver core model IVCR1412, so it does not affect the transmission of the low-level signal.

[0027] The MOS tube driving unit includes a MOS tube driving chip with model IVCR1412BD, the input end of the MOS tube driving chip is electrically connected to the cathode of the ultrafast recovery diode D2 or the anode of the Schottky diode D3, the pull-up output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube through a front negative voltage capacitor connected in series, the negative voltage output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube, the power supply end of the MOS tube driving chip is connected to the power supply, and the ground end of the MOS tube driving chip is grounded. The multiple MOS tube driving units are respectively a first MOS tube driving unit, a second MOS tube driving unit and a third MOS tube driving unit; the first MOS tube driving unit includes a first MOS tube driving chip U3 with a model number of IVCR1412BD, the second MOS tube driving unit includes a second MOS tube driving chip U4 with a model number of IVCR1412BD, and the third MOS tube driving unit includes a third MOS tube driving chip U5 with a model number of IVCR1412BD; the input terminals IN of the first MOS tube driving chip U3, the second MOS tube driving chip U4 and the third MOS tube driving chip U5 are connected to the cathode of the ultrafast recovery diode D2 or the Schottky diode The positive electrode of D3; the output end OUT of the first MOS tube driver chip U3 is connected to the gate of the first MOS tube Q1 through the series capacitor C8, and the negative output end of the first MOS tube driver chip U3 is connected to the gate of the first MOS tube Q1; the output end OUT of the second MOS tube driver chip U4 is connected to the gate of the second MOS tube Q2 through the series capacitor C10, and the negative output end of the second MOS tube driver chip U4 is connected to the gate of the second MOS tube Q2; the output end OUT of the third MOS tube driver chip U5 is connected to the gate of the third MOS tube Q3 through the series capacitor C12, and the negative output end of the third MOS tube driver chip U5 is connected to the gate of the third MOS tube Q3. The sources of the first MOS tube Q1, the second MOS tube Q2 and the third MOS tube Q3 are all grounded.

[0028] Since multiple power tubes are connected in parallel, the load capacity of the MOS tube driver chip model IVCR1412BD is limited. The spatial distribution of the MOS tubes on the layout causes each MOS tube to be at a different distance from the MOS tube driver chip. Therefore, the silicon carbide MOS tube driver chip U2 model IVCR1401 does not directly drive the MOS tube, but outputs the signal to multiple MOS tube driver chips through the OUT pin. The multiple MOS tube driver chips drive the corresponding MOS tubes respectively. In this way, multiple MOS tube driver chips on the layout can be placed close to the corresponding MOS tubes to reduce interference.

[0029] The negative voltage bias driving unit also includes a circuit for withdrawing insurance and detecting peripherals, which includes a diode D1, a resistor R4, a diode D4 and a resistor R3, wherein the cathode of the diode D1 is used to connect the drain of the MOS tube, the anode of the diode D1 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is electrically connected to the desaturation detection input of the silicon carbide MOS tube driver chip U2, the desaturation detection input of the silicon carbide MOS tube driver chip U2 is electrically connected to the cathode of the diode D4, the anode of the diode D4 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is grounded. By setting the circuit for withdrawing insurance and detecting peripherals, when a short circuit or overcurrent occurs, the drain or collector current of the MOS tube may increase to a very high value, thereby causing the silicon carbide MOS tube driver chip U2 to exit the saturation state.

[0030] The digital isolation unit includes a dual-channel digital isolator U1, the dual-channel digital isolator U1 includes a first channel input, a first channel output, a second channel input, and a second channel output. The first channel output of the dual-channel digital isolator U1 is used to output a fault signal. The first channel input of the dual-channel digital isolator U1 is electrically connected to the fault output of the silicon carbide MOS tube driver chip U2. The second channel input of the dual-channel digital isolator U1 is connected to the drive signal through a series resistor R1. The second channel output of the dual-channel digital isolator U1 is electrically connected to the logic input of the silicon carbide MOS tube driver chip U2. The primary power supply end of the dual-channel digital isolator U1 is connected to the power supply. The secondary power supply end of the dual-channel digital isolator U1 is electrically connected to the power supply output of the silicon carbide MOS tube driver chip U2. The primary grounding end and the secondary grounding end of the dual-channel digital isolator U1 are both grounded. By setting the dual-channel digital isolator U1, one channel can be used to transmit the drive signal, and the other channel can be used to feedback the fault signal, so as to realize the isolated transmission of the drive signal and the fault signal.

[0031] The digital isolation unit also includes an isolator filter circuit, which includes a capacitor C1, a capacitor C2, and a capacitor C3. One end of the capacitor C1 is electrically connected to the second channel input end of the dual-channel digital isolator U1, and the other end of the capacitor C1 is grounded; one end of the capacitor C2 is electrically connected to the primary power supply end of the dual-channel digital isolator U1, and the other end of the capacitor C2 is grounded; one end of the capacitor C3 is electrically connected to the secondary power supply end of the dual-channel digital isolator U1, and the other end of the capacitor C3 is grounded. By setting the isolator filter circuit, the power supply stability is improved.

[0032] Zhanxin Electronics' two silicon carbide driver chips, IVCR1401 and IVCR1412, have different functions. IVCR1401 is a single-tube driver chip with negative voltage shutdown, short circuit protection, and fault output functions; while the function of IVCR1412 is much simpler, with only negative voltage shutdown and constant current drive functions, and is mainly used for dynamic current sharing when multiple tubes are driven in parallel. When it is necessary to have bridge arm short circuit protection, fault output function, and dynamic current sharing function, the use of IVCR1401 and IVCR1412 alone cannot meet the requirements. Therefore, IVCR1401 and IVCR1412 are cascaded to achieve short circuit protection, fault output, and dynamic current sharing functions of multiple tubes in parallel. At this time, if IVCR1401 still outputs signals from the NEG pin to multiple IVCR1412s, the charge on the negative voltage capacitor will be discharged due to the large load, causing IVCR1401 to work abnormally, so the signal can only be output from the OUT pin of the IVCR1401 chip to IVCR1412. However, when the chip is powered on, the OUT pin of IVCR1401 will output a pulse voltage to charge the negative voltage capacitor. The amplitude of the pulse is 3.5V, which exceeds the input high level threshold of IVCR1412. Therefore, IVCR1412 will output a high level signal to turn on the power tube, resulting in false triggering, which may cause a short circuit in the bridge arm of the power circuit. The traditional solution is to power on the signal circuit first, and then power on the power module, thus avoiding the false trigger signal at the moment of powering on the signal circuit. However, this method only avoids the problem. For some systems that power on first or keep the power on, the above driving scheme cannot be applied. The embodiment of the utility model adopts a silicon carbide MOS tube driver chip U2 of model IVCR1401 to output driving signals to multiple MOS tube driver units respectively, and uses each MOS tube driver unit to drive the MOS tube. Since the IVCR1401 silicon carbide MOS tube driver chip has functions such as negative voltage shutdown, short circuit protection, and fault output, the entire driving circuit can have functions such as negative voltage shutdown, short circuit protection, and fault output by using the IVCR1401 silicon carbide MOS tube driver chip to provide driving signals for each MOS tube driver unit.

[0033] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the concept and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A parallel MOS tube driving circuit, characterized in that: It includes a digital isolation unit, a negative voltage bias driving unit and multiple MOS tube driving units, wherein the negative voltage bias driving unit includes a silicon carbide MOS tube driving chip U2 of model IVCR1401; the input end of the digital isolation unit is used to access the driving signal, the output end of the digital isolation unit is electrically connected to the logic input end of the silicon carbide MOS tube driving chip U2, the driving output end of the silicon carbide MOS tube driving chip U2 is electrically connected to the input ends of multiple MOS tube driving units respectively, the negative voltage output end of the silicon carbide MOS tube driving chip U2 is electrically connected to the input ends of multiple MOS tube driving units respectively through a series capacitor C6, and the output end of the MOS tube driving unit is used to connect the gate of the MOS tube.

2. The parallel MOS tube driving circuit according to claim 1, characterized in that: The negative voltage bias driving unit also includes a voltage divider circuit, which includes a resistor R5, one end of the resistor R5 is electrically connected to the driving output end of the silicon carbide MOS tube driving chip U2, one end of the capacitor C6 is electrically connected to the negative voltage output end of the silicon carbide MOS tube driving chip U2, the other end of the resistor R5 is electrically connected to the other end of the capacitor C6, and the other end of the capacitor C6 is electrically connected to the input ends of the multiple MOS tube driving units respectively.

3. The parallel MOS tube driving circuit according to claim 2, characterized in that: The negative voltage bias driving unit also includes a relay protection circuit, which includes an ultra-fast recovery diode D2 and a Schottky diode D3. The other end of the capacitor C6 is electrically connected to the positive electrode of the ultra-fast recovery diode D2 and the negative electrode of the Schottky diode D3, respectively. The negative electrode of the ultra-fast recovery diode D2 is electrically connected to the positive electrode of the Schottky diode D3. The negative electrode of the ultra-fast recovery diode D2 or the positive electrode of the Schottky diode D3 is electrically connected to the input end of the plurality of MOS tube driving units.

4. The parallel MOS tube driving circuit according to claim 3, characterized in that: The MOS tube driving unit includes a MOS tube driving chip with model IVCR1412BD, the input end of the MOS tube driving chip is electrically connected to the cathode of the ultrafast recovery diode D2 or the anode of the Schottky diode D3, the pull-up output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube through a front negative voltage capacitor connected in series, the negative voltage output end of the MOS tube driving chip is electrically connected to the gate of the MOS tube, the power supply end of the MOS tube driving chip is connected to the power supply, and the ground end of the MOS tube driving chip is grounded.

5. The parallel MOS tube driving circuit according to any one of claims 1 to 4, characterized in that: The negative voltage bias driving unit also includes a protection withdrawal and detection peripheral circuit, which includes a diode D1, a resistor R4, a diode D4 and a resistor R3, the cathode of the diode D1 is used to connect the drain of the MOS tube, the anode of the diode D1 is electrically connected to one end of the resistor R4, the other end of the resistor R4 is electrically connected to the desaturation detection input end of the silicon carbide MOS tube driver chip U2, the desaturation detection input end of the silicon carbide MOS tube driver chip U2 is electrically connected to the cathode of the diode D4, the anode of the diode D4 is electrically connected to one end of the resistor R3, and the other end of the resistor R3 is grounded.

6. The parallel MOS tube driving circuit according to claim 1, characterized in that: The digital isolation unit includes a dual-channel digital isolator U1, which includes a first channel input end, a first channel output end, a second channel input end, and a second channel output end. The first channel output end of the dual-channel digital isolator U1 is used to output a fault signal. The first channel input end of the dual-channel digital isolator U1 is electrically connected to the fault output end of the silicon carbide MOS tube driver chip U2. The second channel input end of the dual-channel digital isolator U1 is connected to the drive signal through a series resistor R1. The second channel output end of the dual-channel digital isolator U1 is electrically connected to the logic input end of the silicon carbide MOS tube driver chip U2. The primary power supply end of the dual-channel digital isolator U1 is connected to the power supply, the secondary power supply end of the dual-channel digital isolator U1 is electrically connected to the power supply output end of the silicon carbide MOS tube driver chip U2, and the primary grounding end and the secondary grounding end of the dual-channel digital isolator U1 are both grounded.

7. The parallel MOS tube driving circuit according to claim 6, characterized in that: The digital isolation unit further includes an isolator filter circuit, which includes a capacitor C1, a capacitor C2, and a capacitor C3, one end of the capacitor C1 is electrically connected to the second channel input end of the dual-channel digital isolator U1, and the other end of the capacitor C1 is grounded; one end of the capacitor C2 is electrically connected to the primary power supply end of the dual-channel digital isolator U1, and the other end of the capacitor C2 is grounded; One end of the capacitor C3 is electrically connected to the secondary power supply terminal of the dual-channel digital isolator U1, and the other end of the capacitor C3 is grounded.

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