Array substrate and display panel

Abstract

The utility model discloses an array substrate and a display panel, the array substrate comprises a substrate, a first conductive layer, a first insulating layer, a first semiconductor layer and a second insulating layer, the first conductive layer, the first insulating layer, the first semiconductor layer and the second insulating layer are stacked in the direction away from the substrate, and the first conductive layer comprises a first signal line; the first semiconductor layer comprises a first semiconductor region; a first via hole and a second via hole are further included, the first via hole penetrates through the first insulating layer and the second insulating layer and comprises a first end extending to the surface of the side, away from the substrate, of the first signal line, and a first connecting part is formed in the first via hole; the second via hole penetrates through the second insulating layer and comprises a second end extending to the surface of the side, away from the substrate, of the first semiconductor region, a second connecting part is formed in the second via hole, and the second connecting part is electrically connected with the first connecting part. According to the array substrate provided by the invention, the contact reliability of the second connecting part and the first semiconductor region is higher, and the contact resistance of the second connecting part and the first semiconductor region is reduced, so that the yield of signal transmission is improved, and the phenomenon of signal delay is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in particular, relates to an array substrate and a display panel. Background Art

[0002] The display panel includes an array substrate having a variety of film layers and vias penetrating at least part of the film layers. In order to reduce the number of masking times in the via preparation process, the related art uses the same masking process to etch the vias extending to the data lines and the vias extending to the semiconductor layer of the transistor. However, due to the different etching depths of different vias, over-etching of the semiconductor layer of the transistor may be easily caused, thereby affecting the preparation yield and the performance of the array substrate. Utility Model Content

[0003] The purpose of the present application is to at least solve the problem of over-etching of the semiconductor layer of the transistor in the array substrate. This purpose is achieved through the following technical solutions:

[0004] The first aspect of the present application provides an array substrate, comprising:

[0005] substrate;

[0006] A first conductive layer, formed on one side of the substrate, includes a first signal line;

[0007] A first insulating layer, formed on a side of the first conductive layer facing away from the substrate;

[0008] A first semiconductor layer, formed on a side of the first insulating layer away from the first conductive layer, comprising a first semiconductor region;

[0009] a second insulating layer formed on a side of the first semiconductor layer away from the first insulating layer;

[0010] a first via hole, penetrating the first insulating layer and the second insulating layer, the first via hole comprising a first end, the first end being located on a surface of the first signal line facing away from the substrate, and a first connecting portion being formed in the first via hole;

[0011] A second via hole penetrates the second insulating layer, the second via hole comprises a second end, the second end is located on a surface of the first semiconductor region facing away from the substrate, a second connecting portion is formed in the second via hole, and the second connecting portion is electrically connected to the first connecting portion.

[0012] The array substrate provided in the present application includes a substrate and a first conductive layer, a first insulating layer, a first semiconductor layer and a second insulating layer stacked in a direction away from the substrate. A transistor and a plurality of signal lines are formed in the array substrate. Specifically, the plurality of signal lines include a first signal line, and the first signal line is formed in the first conductive layer. The transistor includes a semiconductor layer, and a first semiconductor region is formed in the first semiconductor layer. The semiconductor layer in one of the transistors in the array substrate is located in the first semiconductor region. A first insulating layer is formed on the side of the first conductive layer facing away from the substrate, so as to insulate the first conductive layer from other film layers located on the side of the first conductive layer facing away from the substrate. A second insulating layer is formed on the side of the first semiconductor layer facing away from the substrate, so as to insulate the first semiconductor layer from other film layers located on the side of the first semiconductor layer facing away from the substrate. The first via penetrates the first insulating layer and the second insulating layer, and a first connection portion is formed in the first via. Since the first end of the first via extends to the surface of the first signal line away from the substrate, the first connection portion can be in contact with the surface of the first signal line away from the substrate; the second via penetrates the second insulating layer, and a second connection portion is formed in the second via. Since the second end of the second via extends to the surface of the first semiconductor region away from the substrate, the second connection portion can be in contact with the surface of the first semiconductor region away from the substrate, and since the first connection portion is connected to the second connection portion, the connection between the first signal line and the transistor can be realized. Among them, since the second end of the second via extends to the surface of the first semiconductor region away from the substrate, the contact reliability of the second connection portion and the first semiconductor region is stronger, and the contact resistance between the two is reduced, thereby improving the yield of signal transmission and improving the phenomenon of signal delay.

[0013] The second aspect of the present application provides a display panel, including the array substrate provided by the first aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present application. Moreover, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0015] Figure 1 is a structural schematic diagram of an array substrate provided in an embodiment of the present application;

[0016] Figure 2 for Figure 1 A schematic diagram of a portion of the film layer in a cross-sectional view along A-A';

[0017] Figure 3 for Figure 1 A schematic diagram of a portion of the film layer in another cross-sectional view along A-A';

[0018] Figure 4 for Figure 1 A schematic diagram of a portion of the film layer in another cross-sectional view along A-A';

[0019] Figure 5 for Figure 1 A schematic diagram of a portion of the film layer in another cross-sectional view along A-A';

[0020] Figure 6 for Figure 1 A schematic diagram of a portion of the film layer in another cross-sectional view along A-A';

[0021] Figure 7 for Figure 1 A cross-sectional view along the middle line A-A';

[0022] Figure 8 is a circuit diagram in an array substrate provided in an embodiment of the present application;

[0023] Fig. 9 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0024] Fig.10 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present application;

[0025] Figures 11 to 13 It is a schematic diagram of film layer changes in a method for preparing an array substrate provided in an embodiment of the present application;

[0026] Figures 14 to 17 is a schematic diagram of film layer changes in another method for preparing an array substrate provided in an embodiment of the present application;

[0027] Figures 18 to 21 It is a schematic diagram of film layer changes in another method for preparing an array substrate provided in an embodiment of the present application.

[0028] The reference numerals are as follows:

[0029] 1. array substrate; 11. substrate; 12. first conductive layer; 121. first signal line; 13. first insulating layer; 14. first semiconductor layer; 141. first semiconductor region; 142. second semiconductor region; 15. second insulating layer; 16. first via hole; 161. first sub-hole; 162. second sub-hole; 17. second via hole; 18. first conductive part; 181. first connecting part; 182. first pattern part; 19. second conductive part; 191. second connecting part; 192. second pattern part; 20. second conductive layer; 201. first routing line; 21. third insulating layer; 22. third conductive layer; 23. fourth insulating layer; 24. fourth conductive layer; 25. third via hole; 26. third conductive part Electrical part; 261, third connecting part; 262, third pattern part; 27, fifth insulating layer; 28, fifth conductive layer; 29, fourth via; 30, fourth conductive part; 301, fourth connecting part; 302, fourth pattern part; 31, capacitor; 301, first electrode; 302, second electrode; 303, third electrode; 32, sixth conductive layer; 33, seventh conductive layer; 34, eighth conductive layer; 35, first electrode; 36, buffer layer; T1, first transistor; T2, second transistor; T3, third transistor; ELVDD, first power supply signal; ELVSS, second power supply signal; Data, data signal; Sens, compensation signal; N1, first node; N2, second node. DETAILED DESCRIPTION

[0030] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0031] It should be understood that the terms used herein are only for the purpose of describing specific example embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive, and therefore specify the existence of stated features, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The method steps, processes, and operations described herein are not interpreted as necessarily requiring them to be performed in the specific order described or illustrated, unless the execution order is clearly indicated. It should also be understood that additional or alternative steps may be used.

[0032] Although the terms first, second, third, etc. can be used in the text to describe multiple elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms can only be used to distinguish an element, component, region, layer or section from another region, layer or section. Unless the context clearly indicates, terms such as "first", "second" and other numerical terms do not imply order or sequence when used in the text. Therefore, the first element, component, region, layer or section discussed below can be referred to as the second element, component, region, layer or section without departing from the teaching of the example embodiments.

[0033] For ease of description, spatial relative terms may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figure, such as "inside", "outside", "inner side", "outer side", "below", "below", "above", "above", etc. Such spatial relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is turned over, then the elements described as "below other elements or features" or "below other elements or features" will subsequently be oriented as "above other elements or features" or "above other elements or features". Therefore, the example term "below..." can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or in other directions) and the spatial relative descriptors used in the text are interpreted accordingly.

[0034] like Figure 1 and Figure 2 As shown, according to an embodiment of the present application, an array substrate 1 is proposed, which includes a substrate 11, a first conductive layer 12, a first insulating layer 13, a first semiconductor layer 14, and a second insulating layer 15. The first conductive layer 12 is formed on one side of the substrate 11, and includes a first signal line 121. The first insulating layer 13 is formed on the side of the first conductive layer 12 away from the substrate 11. The first semiconductor layer 14 is formed on the side of the first insulating layer 13 away from the first conductive layer 12, and includes a first semiconductor region 141. The second insulating layer 15 is formed on the side of the first semiconductor layer 14 away from the first insulating layer 13. The first via 16 penetrates the first insulating layer 13 and the second insulating layer 15, and the first via 16 includes a first end, and the first end is located on the surface of the first signal line 121 on the side away from the substrate 11, and a first connecting portion 181 is formed in the first via 16. The second via hole 17 penetrates the second insulating layer 15 and includes a second end located on a surface of the first semiconductor region 141 facing away from the substrate 11 . A second connecting portion 191 is formed in the second via hole 17 and is electrically connected to the first connecting portion 181 .

[0035] The array substrate 1 provided in the present application includes a substrate 11 and a first conductive layer 12, a first insulating layer 13, a first semiconductor layer 14 and a second insulating layer 15 stacked in a direction away from the substrate 11. A transistor and a plurality of signal lines are formed in the array substrate 1. Specifically, the plurality of signal lines include a first signal line 121, and the first signal line 121 is formed in the first conductive layer 12. The transistor includes a semiconductor layer, and a first semiconductor region 141 is formed in the first semiconductor layer 14. The semiconductor layer in one of the transistors in the array substrate 1 is located in the first semiconductor region 141. A first insulating layer 13 is formed on the side of the first conductive layer 12 facing away from the substrate 11, so as to insulate the first conductive layer 12 from other film layers located on the side of the first conductive layer 12 facing away from the substrate 11. A second insulating layer 15 is formed on the side of the first semiconductor layer 14 facing away from the substrate 11, so as to insulate the first semiconductor layer 14 from other film layers located on the side of the first semiconductor layer 14 facing away from the substrate 11. The first via 16 passes through the first insulating layer 13 and the second insulating layer 15, and a first connecting portion 181 is formed in the first via 16. Since the first end of the first via 16 extends to the side surface of the first signal line 121 away from the substrate 11, the first connecting portion 181 can be in contact with the side surface of the first signal line 121 away from the substrate 11; the second via 17 passes through the second insulating layer 15, and a second connecting portion 191 is formed in the second via 17. Since the second end of the second via 17 extends to the side surface of the first semiconductor region 141 away from the substrate 11, the second connecting portion 191 can be in contact with the side surface of the first semiconductor region 141 away from the substrate 11, and since the first connecting portion 181 is connected to the second connecting portion 191, the connection between the first signal line 121 and the transistor can be realized. Among them, since the second end of the second via 17 extends to the side surface of the first semiconductor region 141 away from the substrate 11, the contact reliability between the second connecting portion 191 and the first semiconductor region 141 is stronger and the contact resistance between the two is reduced, thereby improving the yield of signal transmission and improving the signal delay phenomenon.

[0036] Specifically, the contact resistance when the second connection portion 191 contacts the surface of the side of the first semiconductor region 141 away from the substrate 11 is less than the contact resistance when the second connection portion 191 contacts the first semiconductor region 141 laterally, wherein the second connection portion 191 can contact the side of the first semiconductor region 141 after the second via 17 penetrates the first semiconductor region 141. In the array substrate 1 provided by the present application, the second via 17 only extends to the surface of the side of the first semiconductor region 141 away from the substrate 11, and the first semiconductor region 141 is not over-etched, so that the second connection portion 191 can contact the surface of the first semiconductor region 141 instead of the side, thereby improving the connection yield of the second connection portion 191 and the first semiconductor region 141, and reducing the contact resistance. When the contact resistance is too large, it will cause the problem of signal transmission delay. The array substrate 1 provided by the present application can improve the yield of signal transmission and improve the phenomenon of signal delay.

[0037] Specifically, the “electrical connection” between the second connection portion 191 and the first connection portion 181 includes an electrical connection in which the second connection portion 191 and the first connection portion 181 are in direct contact with each other and an electrical connection in an indirect form.

[0038] Specifically, the first signal line 121 may be a data line. The material of the first conductive layer 12 may include metal, and the material of the first semiconductor layer 14 may include polysilicon.

[0039] In a possible implementation, Figure 2 As shown, the array substrate 1 further includes a second conductive layer 20, a third insulating layer 21, a third conductive layer 22, a fourth insulating layer 23 and a fourth conductive layer 24. The second conductive layer 20 is formed on a surface of the first insulating layer 13 on a side away from the first conductive layer 12, and a first trace 201 is formed in the second conductive layer 20. The third insulating layer 21 is formed between the second conductive layer 20 and the first semiconductor layer 14. The third conductive layer 22 is formed on a side of the second insulating layer 15 away from the first semiconductor layer 14. The fourth insulating layer 23 is formed on a side of the third conductive layer 22 away from the third insulating layer 21. The fourth conductive layer 24 is partially formed on a side of the fourth insulating layer 23 away from the third conductive layer 22. The array substrate 1 also includes a third via 25 and a third conductive portion 26. The third via 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21 and extends to the side surface of the first wiring 201 away from the substrate 11; the third conductive portion 26 is formed in the fourth conductive layer 24, and the third conductive portion 26 includes a third pattern portion 262 and a third connecting portion 261 that are interconnected. The third pattern portion 262 is located on the side surface of the fourth insulating layer 23 away from the third conductive layer 22, and the third connecting portion 261 is located in the third via 25 and in contact with the first wiring 201.

[0040] Specifically, the orthographic projection of the first wiring 201 on the substrate 11 does not overlap with the orthographic projection of the first signal line 121 on the substrate 11. In the above embodiment, the array substrate 1 further includes a second conductive layer 20, a third insulating layer 21, a third conductive layer 22, a fourth insulating layer 23 and a fourth conductive layer 24 which are sequentially stacked in a direction away from the second insulating layer 15. The second conductive layer 20 is used to form the first wiring 201. The third insulating layer 21 is used to achieve insulation between the second conductive layer 20 and the first semiconductor layer 14. The third conductive layer 22 is used to form the gate of the transistor and the plate of the capacitor 31 in the array substrate 1, wherein the orthographic projection of the gate on the substrate 11 is located within the orthographic projection of the first semiconductor region 141 on the substrate 11. The fourth conductive layer 24 is used to form a third conductive portion 26, and the third conductive portion 26 can be used to connect the signal line to achieve signal transmission. Specifically, a third via hole 25 may be formed in the array substrate 1, the third via hole 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21 and extends to the surface of the first wiring 201 facing away from the substrate 11, the third conductive portion 26 may be connected to the first wiring 201 through the third via hole 25, the third conductive portion 26 includes a third pattern portion 262 and a third connecting portion 261 connected to each other, the third pattern portion 262 is located on the surface of the fourth insulating layer 23 facing away from the third conductive layer 22, the third connecting portion 261 is located in the third via hole 25 and contacts the first wiring 201. The fourth insulating layer 23 is located between the third conductive layer 22 and the fourth conductive layer 24, and is used to achieve insulation between the third conductive layer 22 and the fourth conductive layer 24.

[0041] The first wiring 201 may be used to connect external devices such as a driver chip.

[0042] In a possible implementation, Figure 2 As shown, the array substrate 1 further includes a first conductive portion 18 and a second conductive portion 19. The first conductive portion 18 is formed on the fourth conductive layer 24. The first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181. The first pattern portion 182 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22. The first via 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. The second conductive portion 19 is formed on the fourth conductive layer 24. The second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191. The second pattern portion 192 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22. The second via 17 sequentially penetrates the fourth insulating layer 23 and the second insulating layer 15. Among them, the first pattern portion 182 is connected to the second pattern portion 192, and / or, as Figure 3 As shown, the first connection portion 181 is connected to the second connection portion 191 .

[0043] In the above embodiment, the first via hole 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13, and the third via hole 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21 and extends to the surface of the first wiring 201 facing away from the substrate 11. Since the depths of the first via hole 16 and the third via hole 25 are similar, the first via hole 16 and the third via hole 25 can be prepared by the same preparation process to save the number of masking times. The second via hole 17 sequentially penetrates the fourth insulating layer 23 and the second insulating layer 15. The depths of the second via hole 17 and the first via hole 16 are quite different. Therefore, the second via hole 17 and the first via hole 16 are prepared by different preparation processes to prevent the second via hole 17 from being prepared at the same time as the first via hole 16, which causes the second via hole 17 to have a deeper depth, causing the first semiconductor layer 14 to be over-etched, thereby affecting the yield of the first semiconductor region 141 and the connection yield of the second connection portion 191 and the first semiconductor region 141.

[0044] In the above embodiment, the first conductive portion 18 includes a first connection portion 181 and a first pattern portion 182 interconnected with the first connection portion 181, and the second conductive portion 19 includes a second connection portion 191 and a second pattern portion 192 interconnected with the second connection portion 191. The first pattern portion 182 and the second pattern portion 192 are both located on the surface of the fourth insulating layer 23 facing away from the third conductive layer 22, that is, the first pattern portion 182 and the second pattern portion 192 are prepared in the same layer, so that the first signal line 121 can be connected to the transistor corresponding to the first semiconductor region 141 through the connection of the first pattern portion 182 and the second pattern portion 192. Alternatively, the first via 16 and the second via 17 can be close to each other so that the side walls are connected, so that the first signal line 121 can be connected to the transistor corresponding to the first semiconductor region 141 through the connection of the first connection portion 181 and the second connection portion 191. The first connection portion 181 can also be connected to the second connection portion 191 while the first pattern portion 182 and the second pattern portion 192 are connected, and this is not particularly limited in the present application.

[0045] In the above embodiment, the second conductive portion 19 is connected to a surface of the first semiconductor region 141 that is away from the substrate 11. Specifically, the first semiconductor region 141 includes a source region, a drain region and a channel region located between the source region and the drain region. The source region, the channel region and the drain region are arranged in a direction parallel to the substrate 11. The second conductive portion 19 can be connected to a surface of the source region that is away from the substrate 11.

[0046] In a possible implementation, Figure 3 and Figure 4As shown, the array substrate 1 further includes a fifth insulating layer 27, a fifth conductive layer 28, a fourth via hole 29 and a fourth conductive portion 30. The fifth insulating layer 27 is formed on the side of the fourth conductive layer 24 away from the fourth insulating layer 23; the fifth conductive layer 28 is partially formed on the side of the fifth insulating layer 27 away from the third conductive layer 22; the fourth via hole 29 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to the surface of the first semiconductor region 141 away from the substrate 11; the fourth conductive portion 30 is formed in the fifth conductive layer 28, and the fourth conductive portion 30 includes a fourth pattern portion 302 and a fourth connecting portion 301, the fourth pattern portion 302 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24, and the fourth connecting portion 301 is located in the fourth via hole 29 and in contact with the first semiconductor region 141.

[0047] In the above embodiment, the first semiconductor region 141 includes a source region, a drain region and a channel region located between the source region and the drain region, the source region, the channel region and the drain region are arranged in a direction parallel to the substrate 11, and the fourth conductive portion 30 can be connected to the surface of the drain region facing away from the substrate 11.

[0048] In the above embodiment, the fifth insulating layer 27 and the fifth conductive layer 28 are arranged in sequence in a direction away from the fourth conductive layer 24. The fifth insulating layer 27 is used to achieve insulation between the fourth conductive layer 24 and the fifth conductive layer 28. The fifth conductive layer 28 can be used to form a fourth conductive portion 30 to achieve connection with the drain region in the first semiconductor region 141. Specifically, the fourth via 29 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to the side surface of the first semiconductor region 141 away from the substrate 11, and specifically can extend to the side surface of the drain region away from the substrate 11. The fourth conductive portion 30 is formed in the fifth conductive layer 28, and the fourth conductive portion 30 includes a fourth pattern portion 302 and a fourth connecting portion 301. The fourth pattern portion 302 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24, and the fourth connecting portion 301 is located in the fourth via 29 and contacts the first semiconductor region 141, thereby achieving connection between the fourth conductive portion 30 and the first semiconductor region 141.

[0049] In a possible implementation, Figure 4As shown, the array substrate 1 further includes a first conductive portion 18 and a second conductive portion 19. The first conductive portion 18 may be formed in the fourth conductive layer 24. The first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181. The first pattern portion 182 is located on a surface of the fourth insulating layer 23 that is away from the third conductive layer 22. The first via 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. The second conductive portion 19 may be formed in the fifth conductive layer 28. The second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191. The second pattern portion 192 is located on a side of the fifth insulating layer 27 that is away from the fourth conductive layer 24. The second via 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15. Among them, the first pattern portion 182 is connected to the second connecting portion 191.

[0050] Specifically, the first via hole 16 may sequentially penetrate the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. Since the third via hole 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21, the depths of the first via hole 16 and the third via hole 25 are not much different. Therefore, in order to save the number of masks and simplify the preparation process, the first via hole 16 and the third via hole 25 can be prepared by the same mask process. The second via hole 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15. Since the fourth via hole 29 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15, the depths of the second via hole 17 and the fourth via hole 29 are the same. Therefore, in order to save the number of masks and simplify the preparation process, the second via hole 17 and the fourth via hole 29 can be prepared by the same mask process. In this embodiment, the first via hole 16 and the third via hole 25 are prepared by the same mask process, and the second via hole 17 and the fourth via hole 29 are prepared by the same mask process, so that the preparation process of the first via hole 16 and the second via hole 17 does not increase the number of masking times of the array substrate 1, so that the preparation process can be simple and the cost is low. In addition, since the depths of the first via hole 16 and the second via hole 17 are quite different, the preparation using different processes can ensure the preparation yield of the first via hole 16 and the second via hole 17, prevent over-engraving from causing poor connection between the second connecting portion 191 and the first semiconductor region 141, and help improve the connection yield between the second connecting portion 191 and the first semiconductor region 141.

[0051] In the above embodiment, since the second pattern portion 192 in the second conductive portion 19 is located on the side of the first pattern portion 182 of the first conductive portion 18 away from the substrate 11, the first signal line 121 can be electrically connected to the transistor corresponding to the first semiconductor region 141 by connecting the first pattern portion 182 to the second connecting portion 191.

[0052] Specifically, the dimension of the contact surface between the first pattern portion 182 and the second connecting portion 191 along the thickness direction of the substrate 11 is greater than or equal to 1.2um, that is, the dimension of the first pattern portion 182 along the thickness direction of the substrate 11 in the projection on the second connecting portion 191 along the direction parallel to the substrate 11 is greater than or equal to 1.2um, so as to improve the connection yield between the first conductive portion 18 and the second conductive portion 19 and ensure the stability and reliability of signal transmission.

[0053] In another possible implementation, if Figure 5 and Figure 6 As shown, the array substrate 1 further includes a first conductive portion 18 and a second conductive portion 19. The first conductive portion 18 is formed on the fifth conductive layer 28. The first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181. The first pattern portion 182 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24. The first via 16 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. The second conductive portion 19 is formed on the fifth conductive layer 28. The second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191. The second pattern portion 192 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24. The second via 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15. Among them, the first pattern portion 182 is connected to the second pattern portion 192, and / or the first connecting portion 181 is connected to the second connecting portion 191.

[0054] In the above embodiment, the first via 16 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. Since the second via 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15, and the third via 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21, the film layer passed by the first via 16 is similar in overall thickness to the film layer passed by the third via 25 and the second via 17 in total. Therefore, a part of the first via 16 can be prepared while preparing the third via 25, and another part of the first via 16 can be prepared while preparing the second via 17, and the two parts are connected to form the first via 16, and the preparation of the first via 16 does not require an additional mask process. Since the second via hole 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23, and the second insulating layer 15, and the fourth via hole 29 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23, and the second insulating layer 15, the depths of the second via hole 17 and the fourth via hole 29 are the same, so in order to save the number of masks and simplify the preparation process, the second via hole 17 and the fourth via hole 29 can be prepared by the same mask process. In this embodiment, part of the first via hole 16 is prepared by the same mask process as the third via hole 25, and part of the first via hole 16 is prepared by the same mask process as the second via hole 17, and the second via hole 17 is prepared by the same mask process as the fourth via hole 29, so that the preparation process of the first via hole 16 and the second via hole 17 does not increase the number of masks of the array substrate 1, so that the preparation process can be simple and low in cost. And because the depths of the first via 16 and the second via 17 differ greatly, the above-mentioned preparation process can ensure the preparation yield of the first via 16 and the second via 17, prevent over-engraving from causing poor connection between the second connecting portion 191 and the first semiconductor region 141, and help improve the connection yield between the second connecting portion 191 and the first semiconductor region 141.

[0055] In the above embodiment, the first conductive part 18 includes a first connecting part 181 and a first pattern part 182 interconnected with the first connecting part 181, and the second conductive part 19 includes a second connecting part 191 and a second pattern part 192 interconnected with the second connecting part 191. Since the second pattern part 192 in the second conductive part 19 and the first pattern part 182 of the first conductive part 18 are both made of the fifth conductive layer 28 and are both located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24, that is, the first pattern part 182 and the second pattern part 192 are made in the same layer, the first signal line 121 can be electrically connected to the transistor corresponding to the first semiconductor region 141 by connecting the first pattern part 182 to the second pattern part 192. Alternatively, the first via 16 and the second via 17 can be close to each other so that the side walls are connected, so that the first signal line 121 can be connected to the transistor corresponding to the first semiconductor region 141 by connecting the first connecting part 181 to the second connecting part 191. The first connection portion 181 and the second connection portion 191 may also be connected while the first pattern portion 182 and the second pattern portion 192 are connected, and this is not particularly limited in the present application.

[0056] Specifically, Figure 7 As shown, the array substrate 1 provided in the present application may include a 3T1C structure, that is, it includes three transistors and a capacitor 31. The three transistors may include a first transistor T1, a second transistor T2, and a third transistor T3. The active region of the first transistor T1 may be the first semiconductor region 141, the gate of the first transistor T1 may be located in the third conductive layer 22, and the source and drain of the first transistor T1 may be the second conductive portion 19 and the fourth conductive portion 30, respectively. The active layer of the second transistor T2 may be prepared in the same layer as the active layer of the first transistor T1, and is located in the first semiconductor layer 14. Specifically, the first semiconductor layer 14 may further include a second semiconductor region 142 as the active region of the second transistor T2. The gate of the second transistor T2 may be prepared in the same layer as the gate of the first transistor T1, that is, located in the third conductive layer 22. One of the source and drain of the second transistor T2 may be arranged in the same manner as the fourth conductive portion 30, and the other may adopt other conductive layers.

[0057] Specifically, the array substrate 1 may further include a sixth conductive layer 32, a seventh conductive layer 33, and an eighth conductive layer 34 stacked in a direction away from the fifth conductive layer 28, the sixth conductive layer 32 may be used to form a signal line, the seventh conductive layer 33 may be used to form a conductive portion connected to the signal line, and the eighth conductive layer 34 may be used to form a signal line and / or a conductive portion, etc., which is not particularly limited in the present application. Among them, the other of the source and the drain of the second transistor T2 may be formed in the seventh conductive layer 33.

[0058] The array substrate 1 further includes a capacitor 31, such as Figure 7As shown, the capacitor 31 includes a first electrode 311, a second electrode 312 and a third electrode 313 arranged in a direction away from the substrate 11, the first electrode 311 is located in the third conductive layer 22, the second electrode 312 is located in the fourth conductive layer 24 and is connected to the third pattern portion 262, the third electrode 313 is located in the fifth conductive layer 28 and is connected to the fourth pattern portion 302, and the first electrode 311 is connected to the fourth connecting portion 301.

[0059] In the above embodiment, the first plate 311 and the second plate 312 of the capacitor 31 are connected to the same signal and are both connected to the fourth conductive portion 30 to achieve electrical connection with the first transistor T1. The fourth conductive portion 30 may be in lateral contact with the first plate 311. The second plate 312 is located between the first plate 311 and the third plate 313 along the thickness direction of the substrate 11.

[0060] Specifically, the dimension of the contact surface between the first electrode plate 311 and the fourth connecting part along the thickness direction of the substrate 11 is greater than or equal to 1.2um, that is, the dimension of the first electrode plate 311 along the thickness direction of the substrate 11 in the projection on the fourth connecting part along the direction parallel to the substrate 11 is greater than or equal to 1.2um, so as to improve the connection yield between the first electrode plate 311 and the fourth connecting part and ensure the stability and reliability of signal transmission.

[0061] In a feasible implementation, the semiconductor layer of the third transistor T3 may be partially located in the same layer as the fifth conductive layer 28, and may partially extend to the side of the fifth conductive layer 28 away from the substrate 11. The semiconductor layer of the third transistor T3 may be an oxide semiconductor layer.

[0062] Specifically, Figure 8 As shown, in the 3T1C circuit, the source of the first transistor T1 can be connected to the data signal Data, the drain can be connected to the first node N1, and the gate can be connected to the scan signal Scan; the gate of the second transistor T2 can be connected to the first node N1, the source can be connected to the first power signal ELVDD, and the drain can be connected to the second node N2; the source of the third transistor T3 can be connected to the compensation signal Sens, the gate can be connected to the scan signal Scan, and the drain can be connected to the second node N2.

[0063] In a possible implementation, Figure 7As shown, the array substrate 1 further includes a first electrode 35, which is formed on the side of the eighth conductive layer 34 away from the substrate 11 and is connected to the second transistor T2 and the third transistor T3. The first electrode 35 includes a first layer and a second layer stacked along the thickness direction of the substrate 11, the first layer is an indium tin oxide layer, and the second layer includes a titanium metal layer, an aluminum metal layer and a titanium metal layer stacked in a direction away from the substrate 11. The first electrode 35 can be prepared by a dry etching process, and the dry etching process can better control the precision, so that the first electrode 35 can be made smaller to adapt to a high-resolution display panel.

[0064] In a possible implementation, Figure 7 As shown, a buffer layer 36 may also be included. The buffer layer 36 is located between the fifth insulating layer 27 and the fifth conductive layer 28 along the thickness direction of the substrate 11 .

[0065] The present application also provides a display panel 2, such as Fig. 9 As shown, it includes any one of the array substrates 1 provided in the above embodiments of the present application.

[0066] The display panel 2 may further include a light emitting device connected to a driving circuit in the array substrate 1, which may be a 3T1C circuit. The anode of the light emitting device is connected to the second node N2 in the 3T1C circuit, and the cathode is connected to the second power signal ELVSS.

[0067] In the display panel 2, since the connection yield between the first transistor T1 in the array substrate 1 and the first signal line 121 is higher and the contact resistance is smaller, the yield and performance of the display panel 2 can be improved. Specifically, the first signal line 121 can be a data line, thereby improving the data writing capability and the charging rate.

[0068] The present application also provides a method for preparing the array substrate 1, such as Fig.10 As shown, including:

[0069] S200 , providing a substrate 11 .

[0070] S400 , forming a first conductive layer 12 on one side of the substrate 11 , and patterning the first conductive layer 12 to form a first signal line 121 .

[0071] Specifically, the first conductive layer 12 may be a metal layer, and the first conductive layer 12 may be in direct contact with the substrate 11 .

[0072] S600 , forming a first insulating layer 13 on a side of the first conductive layer 12 facing away from the substrate 11 .

[0073] Specifically, the first insulating layer 13 may also play a buffering role.

[0074] S800 , forming a first semiconductor layer 14 on a side of the first insulating layer 13 away from the first conductive layer 12 , and patterning the first semiconductor layer 14 to form a first semiconductor region 141 .

[0075] Specifically, the material of the first semiconductor layer 14 may include polysilicon.

[0076] S1000 , forming a second insulating layer 15 on a side of the first semiconductor layer 14 facing away from the first insulating layer 13 .

[0077] S1200 , forming a first via hole 16 , the first via hole 16 penetrates the first insulating layer 13 and the second insulating layer 15 , and includes a first end extending to a surface of the first signal line 121 facing away from the substrate 11 , and a first connecting portion 181 is formed in the first via hole 16 .

[0078] S1400, forming a second via hole 17, the second via hole 17 penetrates the second insulating layer 15 and includes a second end extending to the surface of the first semiconductor region 141 on the side away from the substrate 11, forming a second connecting portion 191 in the second via hole 17, and making the second connecting portion 191 electrically connected to the first connecting portion 181.

[0079] The first via hole 16 and the second via hole 17 prepared in the above embodiment extend to the surface of the first signal line 121 facing away from the substrate 11 and the surface of the first semiconductor layer 14 facing away from the substrate 11, respectively. Therefore, the first signal line 121 and the first semiconductor layer 14 are not over-etched, which can improve the connection yield between the first connection portion 181 and the first signal line 121 and the connection yield between the second connection portion 191 and the first semiconductor layer 14. Therefore, the connection yield between the signal in the first signal line 121 and the transistor corresponding to the first semiconductor layer 14 can be improved.

[0080] In a feasible implementation, it also includes:

[0081] S610 , forming a second conductive layer 20 on a surface of the first insulating layer 13 that is away from the first conductive layer 12 , and patterning the second conductive layer 20 to form a first trace 201 .

[0082] Specifically, the material of the second conductive layer 20 may be metal.

[0083] S620 , forming a third insulating layer 21 on a side of the second conductive layer 20 away from the first insulating layer 13 , so as to achieve insulation between the second conductive layer 20 and the first semiconductor layer 14 .

[0084] Specifically, the third insulating layer 21 may also play a buffering role.

[0085] as well as,

[0086] S1010 , forming a third conductive layer 22 on a side of the second insulating layer 15 away from the first semiconductor layer 14 .

[0087] Specifically, the third conductive layer 22 may be used to form a gate of a transistor and a connection wiring, etc. The third conductive layer 22 may be made of metal.

[0088] S1020 , forming a fourth insulating layer 23 on a side of the third conductive layer 22 away from the third insulating layer 21 .

[0089] S1030 , forming a third via hole 25 , the third via hole 25 sequentially penetrates the fourth insulating layer 23 , the second insulating layer 15 and the third insulating layer 21 and extends to a surface of the first trace 201 facing away from the substrate 11 .

[0090] S1040, forming a fourth conductive layer 24, wherein the fourth conductive layer 24 is partially formed on a side of the fourth insulating layer 23 away from the third conductive layer 22, and the fourth conductive layer 24 is patterned to form a third conductive portion 26, wherein the third conductive portion 26 includes a third pattern portion 262 and a third connecting portion 261 that are interconnected, wherein the third pattern portion 262 is located on a surface of the fourth insulating layer 23 that is away from the third conductive layer 22, and the third connecting portion 261 is located in the third via 25 and in contact with the first trace 201.

[0091] In the above embodiment, a mask process is performed on the side of the fourth insulating layer 23 facing away from the substrate 11 to form the third via hole 25. After the third via hole 25 is formed, the fourth conductive layer 24 is prepared, and the fourth conductive layer 24 includes a third conductive portion 26. The third conductive portion 26 includes a third pattern portion 262 located on the surface of the side of the fourth insulating layer 23 facing away from the third conductive layer 22 and a third connecting portion 261 located in the third via hole 25. The third connecting portion 261 is connected to the first trace 201.

[0092] In a possible implementation, Fig.11 As shown, a first etching process is used to form a first via hole 16 and a third via hole 25, and the first via hole 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the surface of the first signal line 121 facing away from the substrate 11;

[0093] like Fig.12 As shown, a second etching process is used to form a second via hole 17, and the second via hole 17 sequentially penetrates the fourth insulating layer 23 and the second insulating layer 15 and extends to a surface of the first semiconductor region 141 facing away from the substrate 11;

[0094] like Fig.13As shown, forming the fourth conductive layer 24 includes: forming a first conductive portion 18 and a second conductive portion 19, the first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181, the first pattern portion 182 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, and the first connecting portion 181 is located in the first via 16; the second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191, the second pattern portion 192 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, the second connecting portion 191 is located in the second via 17, the first pattern portion 182 is connected to the second pattern portion 192, and / or the first connecting portion 181 is connected to the second connecting portion 191.

[0095] Specifically, forming the fourth conductive layer 24 also includes forming the third conductive portion 26 , which will not be described in detail in this application.

[0096] In the above preparation method, step S1200 and step S1030 can be prepared and formed by a one-time preparation process. Specifically, after the fourth insulating layer 23 is prepared, a one-time mask process can be used to etch and form the first via 16 and the third via 25. The first via 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the side surface of the first signal line 121 away from the substrate 11; the third via 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21 and extends to the side surface of the first wiring 201 away from the substrate 11. The depths of the first via 16 and the third via 25 are similar, and the use of a one-time mask process can save the number of mask times. Since the depth of the second via hole 17 is significantly different from that of the first via hole 16, another mask process is used to etch and form the second via hole 17, thereby ensuring the yield of the second via hole 17 and preventing the first semiconductor region 141 from being over-etched during the etching process to form the second via hole 17 and affecting the connection yield.

[0097] In the above preparation method, after the first via 16, the second via 17 and the third via 25 are formed, the fourth conductive layer 24 is further prepared, so that the first pattern portion 182 of the first conductive portion 18, the second pattern portion 192 of the second conductive portion 19 and the third pattern portion 262 of the third conductive portion 26 are located in the same layer, so that the first conductive portion 18, the second conductive portion 19 and the third conductive portion 26 can be prepared by the same process, and at the same time, it is convenient to connect the first pattern portion 182 with the second pattern portion 192 to realize the connection between the first signal line 121 and the transistor corresponding to the first semiconductor region 141.

[0098] At the same time, the first via hole 16 and the second via hole 17 can be arranged adjacent to each other, and the sidewalls of the first via hole 16 and the second via hole 17 can be connected to facilitate the connection between the first connection portion 181 in the first via hole 16 and the second connection portion 191 in the second via hole 17, thereby realizing the connection between the first signal line 121 and the transistor corresponding to the first semiconductor region 141. This preparation method can further enhance the connection strength between the first signal line 121 and the transistor corresponding to the first semiconductor region 141.

[0099] In a feasible implementation, it also includes:

[0100] S1060 , forming a fifth insulating layer 27 on a side of the fourth conductive layer 24 away from the fourth insulating layer 23 .

[0101] S1080 , forming a fourth via hole 29 , wherein the fourth via hole 29 sequentially penetrates the fifth insulating layer 27 , the fourth insulating layer 23 , and the second insulating layer 15 and extends to a surface of the first semiconductor region 141 facing away from the substrate 11 .

[0102] S1100, forming a fifth conductive layer 28, a portion of the fifth conductive layer 28 is formed on a side of the fifth insulating layer 27 away from the third conductive layer 22, and the fifth conductive layer 28 is patterned to form a fourth conductive portion 30, the fourth conductive portion 30 includes a fourth pattern portion 302 and a fourth connecting portion 301, the fourth pattern portion 302 is located on a side of the fifth insulating layer 27 away from the fourth conductive layer 24, the fourth connecting portion 301 is located in the fourth via 29 and in contact with the first semiconductor region 141.

[0103] In the above embodiment, the fourth via hole 29 extends to the surface of the first semiconductor region 141 on the side facing away from the substrate 11, and the fourth via hole 29 and the first via hole 16 respectively expose the drain region and the source region of the first semiconductor region 141. The fifth conductive layer 28 is used to form a fourth conductive portion 30, and the fourth conductive portion 30 includes a fourth connecting portion 301 located in the fourth via hole 29 and connected to the first semiconductor region 141. During the formation of the fourth via hole 29, the fourth via hole 29 can be formed by performing a masking process and etching on the side of the fifth insulating layer 27 facing away from the substrate 11.

[0104] In a feasible implementation, it also includes:

[0105] like Fig.14 As shown, a first etching process is used to form a first via hole 16 and a third via hole 25, and the first via hole 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the surface of the first trace 201 facing away from the substrate 11;

[0106] like Fig.15As shown, forming the fourth conductive layer 24 includes: forming a first conductive portion 18 and a third conductive portion 26, the first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181, the first pattern portion 182 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, and the first connecting portion 181 is located in the first via 16; the third conductive portion 26 includes a third pattern portion 262 and a third connecting portion 261 connected to each other, the third pattern portion 262 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, and the third connecting portion 261 is located in the third via 25 and in contact with the first trace 201;

[0107] like Fig.16 As shown, a second etching process is used to form a second via hole 17 and a fourth via hole 29, and the second via hole 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to a surface of the first semiconductor region 141 facing away from the substrate 11;

[0108] like Fig.17 As shown, forming the fifth conductive layer 28 includes: forming a second conductive portion 19 and a fourth conductive portion 30, the second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191, the second pattern portion 192 is located on a side of the fifth insulating layer 27 away from the fourth conductive layer 24, and the second connecting portion 191 is located in the first via 16; the fourth conductive portion 30 includes a fourth pattern portion 302 and a fourth connecting portion 301 that are interconnected, the fourth pattern portion 302 is located on a side of the fifth insulating layer 27 away from the fourth conductive layer 24, the fourth connecting portion 301 is located in the fourth via 29 and in contact with the first semiconductor region 141, and the second connecting portion 191 is connected to the first pattern portion 182.

[0109] In the above preparation method, step S1200 and step S1030 can be prepared and formed by a one-time preparation process. Specifically, after the fourth insulating layer 23 is prepared, a one-time mask process can be used to etch and form the first via 16 and the third via 25. The first via 16 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the side surface of the first signal line 121 away from the substrate 11; the third via 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21 and extends to the side surface of the first wiring 201 away from the substrate 11. The depths of the first via 16 and the third via 25 are similar. The one-time mask process can save the number of mask times, thereby helping to simplify the preparation process and reduce the preparation cost.

[0110] Then, a fourth conductive layer 24 is prepared to form a first conductive portion 18 corresponding to the first via hole 16 and a third conductive portion 26 corresponding to the third via hole 25. Then, a fifth insulating layer 27 is prepared and after the fifth insulating layer 27 is prepared, another mask process is used to etch to form a second via hole 17 and a fourth via hole 29. The second via hole 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to the side surface of the first semiconductor region 141 away from the substrate 11; the fourth via hole 29 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to the side surface of the first semiconductor region 141 away from the substrate 11; the second via hole 17 and the fourth via hole 29 pass through the same film layer, so the second via hole 17 and the fourth via hole 29 can be etched by a single mask process. This preparation method does not require additional mask times for the preparation of the second via hole 17, which helps to simplify the preparation process and reduce the preparation cost. At the same time, the yield of the second via hole 17 can be guaranteed, and the connection yield can be prevented from being affected by over-etching the first semiconductor region 141 during the process of etching to form the second via hole 17 .

[0111] In the above preparation method, the first via 16 and the third via 25 are formed by etching using the same mask process, so that the preparation of the first via 16 does not require additional masking times; the second via 17 and the fourth via 29 are formed by etching using the same mask process, so that the preparation of the second via 17 does not require additional masking times, and because the second via 17 and the fourth via 29 have the same depth, the second via 17 and the fourth via 29 can be etched with the same mask process with higher precision, and will not cause over-etching to the first semiconductor region 141.

[0112] In a feasible implementation, it also includes:

[0113] like Fig.18 As shown, a first etching process is used to form a third via hole 25 and a first sub-hole 161, and the first sub-hole 161 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the surface of the first signal line 121 facing away from the substrate 11;

[0114] like Fig.19 As shown, forming the fourth conductive layer 24 includes: forming a third conductive portion 26, the third conductive portion 26 includes a third pattern portion 262 and a third connecting portion 261 connected to each other, the third pattern portion 262 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, and the third connecting portion 261 is located in the third via hole 25 and contacts the first trace 201;

[0115] like Fig. 20As shown, a second etching process is used to form a second sub-hole 162, a second via hole 17 and a fourth via hole 29, the second via hole 17 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23 and the second insulating layer 15 and extends to a surface of the first semiconductor region 141 on a side away from the substrate 11, and the second sub-hole 162 penetrates the fifth insulating layer 27 and communicates with the first sub-hole 161 to form a first via hole 16;

[0116] like Fig.21 As shown, forming the fifth conductive layer 28 includes: forming a first conductive portion 18, a second conductive portion 19 and a fourth conductive portion 30, the first conductive portion 18 includes a first connecting portion 181 and a first pattern portion 182 interconnected with the first connecting portion 181, the first pattern portion 182 is located on a side surface of the fourth insulating layer 23 away from the third conductive layer 22, the first connecting portion 181 is located in the first via 16; the second conductive portion 19 includes a second connecting portion 191 and a second pattern portion 192 interconnected with the second connecting portion 191, the second pattern portion 192 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24, the second connecting portion 191 is located in the first via 16, the second pattern portion 192 is connected to the first pattern portion 182, and / or the second connecting portion 191 is connected to the first connecting portion 181; the fourth conductive portion 30 includes a fourth pattern portion 302 and a fourth connecting portion 301 that are connected to each other, the fourth pattern portion 302 is located on the side of the fifth insulating layer 27 away from the fourth conductive layer 24, the fourth connecting portion 301 is located in the fourth via 29 and in contact with the first semiconductor region 141.

[0117] In the above-mentioned preparation method, the first via hole 16 is prepared by etching twice. Specifically, the first via hole 16 includes a first sub-hole 161 and a second sub-hole 162 which are connected to each other. The first sub-hole 161 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13 and extends to the surface of the first signal line 121 on the side away from the substrate 11; the second sub-hole 162 penetrates the fifth insulating layer 27 and then communicates with the first via hole 16, so that the first via hole 16 sequentially penetrates the fifth insulating layer 27, the fourth insulating layer 23, the second insulating layer 15, the third insulating layer 21 and the first insulating layer 13. Specifically, since the third via hole 25 sequentially penetrates the fourth insulating layer 23, the second insulating layer 15 and the third insulating layer 21, the first sub-hole 161 and the third via hole 25 can be formed by etching using the same mask process. Since the fourth sub-hole extends from the fifth insulating layer 27 toward the second insulating layer 15, the second sub-hole 162 can be formed by etching with the fourth via hole 29 using the same mask process, and since the second via hole 17 and the fourth via hole 29 penetrate the same film layer, the second via hole 17 and the fourth via hole 29 can be etched with the same mask process to achieve high precision, and will not cause over-etching of the first semiconductor region 141. That is, the second sub-hole 162, the second via hole 17 and the fourth via hole 29 are etched with the same mask process. This preparation method does not require additional masking times for the preparation of the second via hole 17 and the first via hole 16, which helps to simplify the preparation process and reduce the preparation cost. At the same time, the yield of the second via hole 17 can be guaranteed, and the first semiconductor region 141 is prevented from being over-etched during the process of etching the second via hole 17, thereby affecting the connection yield.

[0118] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, formed on one side of the substrate, includes a first signal line; A first insulating layer, formed on a side of the first conductive layer facing away from the substrate; A first semiconductor layer, formed on a side of the first insulating layer away from the first conductive layer, comprising a first semiconductor region; a second insulating layer formed on a side of the first semiconductor layer away from the first insulating layer; a first via hole, penetrating the first insulating layer and the second insulating layer, the first via hole comprising a first end, the first end being located on a surface of the first signal line facing away from the substrate, and a first connecting portion being formed in the first via hole; A second via hole penetrates the second insulating layer, the second via hole comprises a second end, the second end is located on a surface of the first semiconductor region facing away from the substrate, a second connecting portion is formed in the second via hole, and the second connecting portion is electrically connected to the first connecting portion.

2. The array substrate according to claim 1, characterized in that: Also includes: A second conductive layer is formed on a surface of the first insulating layer facing away from the first conductive layer, and a first trace is formed in the second conductive layer; a third insulating layer formed between the second conductive layer and the first semiconductor layer; a third conductive layer, formed on a side of the second insulating layer away from the first semiconductor layer; a fourth insulating layer, formed on a side of the third conductive layer away from the third insulating layer; a fourth conductive layer, partially formed on a side of the fourth insulating layer away from the third conductive layer; a third via hole, sequentially penetrating the fourth insulating layer, the second insulating layer and the third insulating layer and extending to a surface of a side of the first trace facing away from the substrate; A third conductive portion is formed in the fourth conductive layer, the third conductive portion includes a third pattern portion and a third connecting portion that are connected to each other, the third pattern portion is located on a surface of the fourth insulating layer that is away from the third conductive layer, and the third connecting portion is located in the third via hole and in contact with the first trace.

3. The array substrate according to claim 2, characterized in that: Also includes: a first conductive portion formed in the fourth conductive layer, the first conductive portion comprising the first connecting portion and a first pattern portion interconnected with the first connecting portion, the first pattern portion being located on a surface of the fourth insulating layer facing away from the third conductive layer, and the first via hole sequentially penetrating the fourth insulating layer, the second insulating layer, the third insulating layer and the first insulating layer; a second conductive portion formed in the fourth conductive layer, the second conductive portion comprising the second connecting portion and a second pattern portion interconnected with the second connecting portion, the second pattern portion being located on a surface of the fourth insulating layer facing away from the third conductive layer, and the second via hole sequentially penetrating the fourth insulating layer and the second insulating layer; Wherein, the first pattern portion is connected to the second pattern portion, and / or the first connection portion is connected to the second connection portion.

4. The array substrate according to claim 2, characterized in that: Also includes: a fifth insulating layer, formed on a side of the fourth conductive layer away from the fourth insulating layer; a fifth conductive layer, partially formed on a side of the fifth insulating layer away from the third conductive layer; a fourth via hole, sequentially penetrating the fifth insulating layer, the fourth insulating layer and the second insulating layer and extending to a surface of the first semiconductor region facing away from the substrate; A fourth conductive portion is formed in the fifth conductive layer, the fourth conductive portion includes a fourth pattern portion and a fourth connecting portion, the fourth pattern portion is located on a side of the fifth insulating layer away from the fourth conductive layer, and the fourth connecting portion is located in the fourth via hole and in contact with the first semiconductor region.

5. The array substrate according to claim 4, characterized in that: Also includes: a first conductive portion formed in the fourth conductive layer, the first conductive portion comprising the first connecting portion and a first pattern portion interconnected with the first connecting portion, the first pattern portion being located on a surface of the fourth insulating layer facing away from the third conductive layer, and the first via hole sequentially penetrating the fourth insulating layer, the second insulating layer, the third insulating layer and the first insulating layer; a second conductive portion formed in the fifth conductive layer, the second conductive portion comprising the second connecting portion and a second pattern portion interconnected with the second connecting portion, the second pattern portion being located at a side of the fifth insulating layer away from the fourth conductive layer, and the second via hole sequentially penetrating the fifth insulating layer, the fourth insulating layer and the second insulating layer; Wherein, the first pattern portion is connected to the second connection portion.

6. The array substrate according to claim 5, characterized in that: A size of a contact surface between the first pattern portion and the second connection portion along a thickness direction of the substrate is greater than or equal to 1.2 um.

7. The array substrate according to claim 4, characterized in that: Also includes: a first conductive portion formed in the fifth conductive layer, the first conductive portion comprising the first connecting portion and a first pattern portion interconnected with the first connecting portion, the first pattern portion being located at a side of the fifth insulating layer away from the fourth conductive layer, and the first via hole sequentially penetrating the fifth insulating layer, the fourth insulating layer, the second insulating layer, the third insulating layer and the first insulating layer; a second conductive portion formed in the fifth conductive layer, the second conductive portion comprising the second connecting portion and a second pattern portion interconnected with the second connecting portion, the second pattern portion being located at a side of the fifth insulating layer away from the fourth conductive layer, and the second via hole sequentially penetrating the fifth insulating layer, the fourth insulating layer and the second insulating layer; Wherein, the first pattern portion is connected to the second pattern portion, and / or the first connection portion is connected to the second connection portion.

8. The array substrate according to claim 4, characterized in that: The array substrate also includes a capacitor, which includes a first electrode plate, a second electrode plate and a third electrode plate arranged in a direction away from the substrate, the first electrode plate is located in the third conductive layer, the second electrode plate is located in the fourth conductive layer and connected to the third pattern portion, the third electrode plate is located in the fifth conductive layer and connected to the fourth pattern portion, and the first electrode plate is connected to the fourth connecting portion.

9. The array substrate according to claim 8, characterized in that: A dimension of a contact surface between the first electrode plate and the fourth connecting portion along a thickness direction of the substrate is greater than or equal to 1.2 um.

10. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 9.

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