Chip positive packaging fan-out structure

Abstract

The utility model discloses a chip front packaging fan-out structure, which comprises a glass carrier, a rewiring layer, a chip and solder, and is characterized in that the glass carrier comprises a first surface and a second surface which are deviated from each other, and the glass carrier is provided with a via hole penetrating from the first surface to the second surface and a blind hole positioned on the first surface; the rewiring layer is arranged on the first surface of the glass carrier and passes through the inner sides of the blind holes and the via holes; the chip is positioned in the blind hole and is connected with the rewiring layer; and the solder is positioned on the second surface of the glass carrier and is connected with the redistribution layer in the via hole. According to the chip positive packaging fan-out structure, the chip is arranged in the blind hole of the glass carrier, and is connected with the welding flux on the second surface of the glass carrier through the rewiring layer in the via hole, so that the size of the whole structure is relatively reduced, and the conduction performance is ensured at the same time.

Description

Technical Field

[0001] The utility model relates to the field of chip packaging, in particular to a chip positive packaging fan-out structure. Background Art

[0002] The main purpose of the chip packaging structure is to protect the chip from external environmental influences such as moisture, dust, static electricity, etc., and to enhance the electrical and thermal performance of the chip. The packaging structure also provides electrical connections between the chip and external circuits, allowing the chip to work in conjunction with other devices or systems.

[0003] The upright structure is the earliest and most widely used chip packaging structure. The existing chip upright structure has the problem of being large in size because most of the chip is exposed.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] 1. Technical issues to be solved

[0006] The utility model provides a chip positive packaging fan-out structure, which at least solves the technical problem of how to reduce the volume of the chip structure.

[0007] (II) Technical solution

[0008] In order to solve the above technical problems, the utility model provides the following technical solutions:

[0009] A chip packaging fan-out structure, comprising:

[0010] A glass carrier, comprising a first surface and a second surface which are opposite to each other, wherein the glass carrier is provided with a through hole penetrating from the first surface to the second surface, and a blind hole located on the first surface;

[0011] A redistribution layer is disposed on the first surface of the glass carrier and passes through the inner side of the blind hole and the through hole;

[0012] A chip is located in the blind hole and connected to the redistribution layer;

[0013] The solder is located on the second surface of the glass carrier and is connected to the redistribution layer in the via hole.

[0014] In some embodiments, a protective layer is further included, which is disposed on the surface of the redistribution layer and is configured to protect the redistribution layer or the redistribution layer and the chip.

[0015] In some embodiments, the protection layer fills the via hole.

[0016] In some embodiments, the diameter of the via gradually decreases from the first surface to the second surface.

[0017] In some embodiments, the protective layer is provided with a clearance opening in the extension direction of the blind hole.

[0018] In some embodiments, the diameter of the blind hole gradually decreases from the first surface to the second surface.

[0019] In some embodiments, the blind hole extends along the thickness direction of the glass carrier, and has a depth of 1 / 3 to 2 / 3 of the thickness of the glass carrier.

[0020] (III) Beneficial effects

[0021] Compared with the prior art, the chip positive package fan-out structure provided by the utility model has the following beneficial effects:

[0022] The chip positive package fan-out structure sets the chip in the blind hole of the glass carrier and connects the solder located on the second side of the glass carrier through the redistribution layer in the conductive hole. With this arrangement, the overall volume is relatively reduced while ensuring the conductive performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 Schematic diagram of the chip packaging fan-out structure in an embodiment.

[0024] Reference numerals: glass carrier 1 , redistribution layer 2 , chip 3 , solder 4 , first surface 11 , second surface 12 , via 13 , blind via 14 . DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0026] The existing upright structure is the earliest and most widely used chip packaging structure. Since most of the chip is exposed, the existing chip upright structure has a problem of being large in size.

[0027] To solve the above technical problems, this embodiment provides a chip positive package fan-out structure, please refer to Figure 1 As shown, Figure 1 Schematic diagram of the chip packaging fan-out structure in an embodiment.

[0028] The chip packaging fan-out structure of this embodiment includes: a glass carrier 1, a redistribution layer 2, a chip 3 and solder 4.

[0029] The glass carrier 1 comprises a first surface 11 and a second surface 12 which are opposite to each other. The glass carrier 1 is provided with a through hole 13 which passes through from the first surface 11 to the second surface 12 , and a blind hole 14 located on the first surface 11 .

[0030] The glass carrier 1 is used as a sealing material to ensure that the internal structure and circuit of the chip 3 are not damaged by the external environment, thereby improving the reliability and stability of the chip 3 .

[0031] The redistribution layer 2 is disposed on the first surface 11 of the glass carrier 1 and passes through the inner sides of the blind holes 14 and the through holes 13 .

[0032] The main function of the redistribution layer 2 is to provide a redistributed circuit layer so as to redistribute the circuit pins or pads inside the chip 3 and lead them out in a more flexible way to adapt to different packaging requirements and different connection methods. According to the position of the redistribution bumps, the redistribution layer 2 can be divided into two types: fan-in type and fan-out type. The fan-in type package concentrates the circuits inside the chip and is mainly used in low I / O node count and smaller die processes.

[0033] The chip 3 is located in the blind hole 14 and connected to the redistribution layer 2 .

[0034] The chip 3 is connected to the redistribution layer 2 to lead the circuit outward. Since the chip 3 is located in the blind hole 14, the volume exposed outside the glass carrier 1 can be reduced.

[0035] The solder 4 is located on the second surface 12 of the glass carrier 1 and is connected to the redistribution layer 2 in the via hole 13 .

[0036] The solder 4 is mainly used to connect the redistribution layer 2 with the substrate or the pins to achieve electrical connection and mechanical fixation.

[0037] The chip positive package fan-out structure of the above technical solution sets the chip 3 in the blind hole 14 of the glass carrier 1, and connects the solder 4 located on the second side 12 of the glass carrier 1 through the redistribution layer 2 in the conductive hole 13. This arrangement reduces the volume of the overall structure relatively while ensuring the conductive performance.

[0038] Among them, the glass carrier 1 uses semiconductor process to produce finer line width lines. The thickness is thinner than the traditional organic resin carrier, and the volume is relatively reduced, meeting the current light, thin, short and small requirements; the conductive path is not affected by the reduced adhesive effect between the organic resin layers, resulting in delamination from the insulating layer, affecting the conduction performance, and the service life is extended.

[0039] In this embodiment, the chip packaging fan-out structure also includes a protective layer 5, which is disposed on the surface of the redistribution layer 2 and is configured to protect the redistribution layer 2 or the redistribution layer 2 and the chip 3. The protective layer 5 can be a passivation layer to prevent the chip 3 structure from being damaged by moisture, oxygen, ions and other pollutants in the environment, thereby protecting the circuit inside the chip 3 from damage.

[0040] Furthermore, the protection layer 5 fills the via hole 13 to make the chip 3 structure more flat, and protects the redistribution layer 2 in the via hole 13 .

[0041] In some embodiments, the diameter of the via 13 gradually decreases from the first surface 11 to the second surface 12 .

[0042] In order to facilitate the disassembly and assembly of the chip 3 and the heat dissipation, the protection layer 5 is provided with a clearance opening in the extension direction of the blind hole 14 , which enables the disassembly and assembly of the chip 3 and improves the heat dissipation efficiency of the chip 3 .

[0043] In some embodiments, the diameter of the blind hole 14 gradually decreases from the first surface 11 to the second surface 12 .

[0044] In this embodiment, the blind hole 14 extends along the thickness direction of the glass carrier 1 , and has a depth of 1 / 3 to 2 / 3 of the thickness of the glass carrier 1 .

[0045] This embodiment provides a chip packaging method, including forming the above-mentioned chip packaging structure.

[0046] In some embodiments, the redistribution layer 2 may be connected to connection points on the glass carrier 1 through metal wires to ensure electrical connection between the chip 3 and an external circuit.

[0047] In some embodiments, the chip 3 is connected to the redistribution layer 2 via an interface with an external circuit.

[0048] In some embodiments, the protection layer 5 is made of insulating material, such as glass, silicate, silicon nitride, etc.

[0049] Although the embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A chip packaging fan-out structure, characterized in that: include: A glass carrier, comprising a first surface and a second surface which are opposite to each other, wherein the glass carrier is provided with a through hole penetrating from the first surface to the second surface, and a blind hole located on the first surface; A redistribution layer is disposed on the first surface of the glass carrier and passes through the inner side of the blind hole and the through hole; A chip is located in the blind hole and connected to the redistribution layer; The solder is located on the second surface of the glass carrier and is connected to the redistribution layer in the via hole.

2. The chip package fan-out structure according to claim 1, characterized in that: It also includes a protection layer, which is arranged on the surface of the redistribution layer and is configured to protect the redistribution layer or the redistribution layer and the chip.

3. The chip package fan-out structure according to claim 2, characterized in that: The protection layer fills the via hole.

4. The chip package fan-out structure according to claim 2, characterized in that: The diameter of the via hole gradually decreases from the first surface to the second surface.

5. The chip package fan-out structure according to claim 2, characterized in that: The protective layer is provided with a clearance opening in the extending direction of the blind hole.

6. The chip package fan-out structure according to claim 1, characterized in that: The diameter of the blind hole gradually decreases from the first surface to the second surface.

7. The chip package fan-out structure according to claim 1, characterized in that: The blind hole extends along the thickness direction of the glass carrier, and has a depth of 1 / 3 to 2 / 3 of the thickness of the glass carrier.

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