Solar cell

Abstract

A solar cell comprises a silicon substrate, a PN junction and a back electrode, wherein the PN junction and the back electrode are located on the back face of the silicon substrate. The front surface of the silicon substrate is provided with a grid line area and a non-grid line area, and the solar cell further comprises a front tunneling layer, a front doped polycrystalline silicon layer and a front electrode which are only positioned in the grid line area. According to the solar cell provided by the utility model, the front tunneling layer and the front doped polycrystalline silicon layer are arranged in the grid line area of the front to form a patterned front passivation contact structure, so that the direct contact between the front electrode and the silicon substrate is avoided, and the under-metal recombination of the front is reduced, thereby improving the cell efficiency and improving the product competitiveness.

Description

Technical Field

[0001] The utility model relates to the photovoltaic field, in particular to a solar cell. Background Art

[0002] TOPCon (Tunnel Oxide Passivated Contact) solar cells are mainly optimized on the back side of the cell. A tunnel layer and a doped polysilicon layer are used to form a passivated contact structure to achieve a field passivation effect, reduce contact resistance, and increase the open circuit voltage and short circuit current of the cell, thereby improving the cell conversion efficiency.

[0003] However, there is also the problem of metal-submerged recombination on the front side of the battery, which limits the efficiency of the battery.

[0004] In view of this, it is necessary to provide an improved solar cell to solve the above technical problems. Utility Model Content

[0005] The utility model provides a solar cell, which is helpful to improve the passivation effect of the grid line area on the front side of the cell, thereby improving the cell efficiency.

[0006] In order to achieve one of the above-mentioned purposes of the utility model, the utility model adopts the following technical solutions:

[0007] A solar cell comprises a silicon substrate, a PN junction and a back electrode located on the back of the silicon substrate; the front of the silicon substrate has a gate line area and a non-gate line area, and the solar cell also comprises a front tunneling layer, a front doped polysilicon layer and a front electrode located only in the gate line area.

[0008] Optionally, the silicon substrate is an N-type silicon wafer, and the front-side doped polysilicon layer is an N-type doped polysilicon layer.

[0009] Optionally, the front tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and / or the thickness of the front tunneling layer is 1 nm to 3 nm.

[0010] Optionally, the front-side doped polysilicon layer has a thickness of 1 nm to 120 nm.

[0011] Optionally, the solar cell also includes a front passivation layer and a front anti-reflection layer located on the front side of the front doped polysilicon layer, and the front electrode passes through the front anti-reflection layer and the front passivation layer and contacts the front doped polysilicon layer; wherein the thickness of the front passivation layer is 2nm~7nm, and the thickness of the front anti-reflection layer is 60nm~130nm.

[0012] Optionally, the front side of the silicon substrate has a pyramid velvet structure.

[0013] Optionally, the silicon substrate is an N-type silicon wafer, and the solar cell includes a back tunneling layer and a P-type doped polysilicon layer located on the back side of the silicon substrate.

[0014] Optionally, the back tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and / or the thickness of the back tunneling layer is 1 nm to 3 nm.

[0015] Optionally, the thickness of the P-type doped polysilicon layer is 50 nm to 150 nm.

[0016] Optionally, the solar cell also includes a back passivation layer and a back anti-reflection layer located on the back side of the P-type doped polycrystalline silicon layer, and the back electrode passes through the back anti-reflection layer and the back passivation layer to contact the back doped polycrystalline silicon layer; wherein the thickness of the back passivation layer is 2nm~7nm, and the thickness of the back anti-reflection layer is 60nm~130nm.

[0017] The beneficial effects of the utility model are as follows: the solar cell of the utility model, by arranging a front tunneling layer and a front doped polysilicon layer in the front gate line area to form a patterned front passivation contact structure, avoids direct contact between the front electrode and the silicon substrate, reduces front metal sub-recombination, thereby improving battery efficiency and enhancing product competitiveness. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic diagram of the structure of the solar cell of the utility model;

[0019] Figure 2 is a schematic diagram of depositing poly Si on the back side of a silicon substrate in one embodiment;

[0020] Figure 3 For Figure 2 Schematic diagram of the backside after boron expansion;

[0021] Figure 4 For Figure 3 Schematic diagram of the front side after BSG removal and velveting;

[0022] Figure 5 For Figure 4 Schematic diagram of poly Si deposited on the front and annealed;

[0023] Figure 6 For Figure 5 Based on the schematic diagram of the front gate line area after laser oxidation;

[0024] Figure 7 For Figure 6 Based on the schematic diagram, the poly Si layer in the non-gate line area is etched on the front side;

[0025] Figure 8For Figure 7 Based on this, a schematic diagram is shown after removing the front and back oxide layers;

[0026] Fig. 9 For Figure 8 Schematic diagram of the front and back sides after the passivation layer is deposited;

[0027] Fig.10 For Fig. 9 Schematic diagram of the front and back sides after depositing anti-reflection layers;

[0028] Fig.11 For Fig.10 Based on this, a schematic diagram is shown after the front and back electrodes are formed.

[0029] Among them, 100-solar cell, 1-silicon substrate, 2-passivation contact structure, 21-front tunneling layer, 22-front doped polysilicon layer, 3-front passivation layer, 4-front anti-reflection layer, 5-front electrode, 6-back tunneling layer, 7-back doped polysilicon layer, 8-back passivation layer, 9-back anti-reflection layer, 10-back electrode, M1-BSG, M2-oxide layer mask. DETAILED DESCRIPTION

[0030] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodological, or functional changes made by a person skilled in the art based on these embodiments are all within the scope of protection of the present invention.

[0031] In the various drawings of the present invention, for the convenience of illustration, some dimensions of structures or parts are exaggerated relative to other structures or parts, and therefore, are only used to illustrate the basic structure of the subject matter of the present invention.

[0032] Please refer to Figure 1 As shown, the solar cell 100 of the utility model includes: a silicon substrate 1, a front tunneling layer 21 located on the front side of the silicon substrate 1, a front doped polysilicon layer 22, a front electrode 5, and a PN junction and a back electrode 10 located on the back side of the silicon substrate 1.

[0033] The silicon substrate 1 is an N-type silicon wafer with a resistivity of 0.3 Ohm·cm to 1.0 Ohm·cm. Preferably, the front surface of the silicon substrate 1 has a pyramid velvet structure to reduce the front reflectivity; the size of the pyramid velvet structure is 0.5 μm to 3 μm.

[0034] The front side of the silicon substrate 1 has a gate line area and a non-gate line area. The front tunneling layer 21 and the front doped polysilicon layer 22 are only located in the gate line area, forming a patterned front passivation contact structure 2, which passivates the front side of the silicon substrate and avoids direct contact between the front electrode 5 and the silicon substrate 1, thereby reducing front metal sub-recombination, thereby improving battery efficiency and enhancing product competitiveness.

[0035] Preferably, the front tunneling layer 21 is a silicon oxide layer or a silicon oxynitride layer, with a thickness of 1 nm to 3 nm, preferably 1.5 nm to 2 nm, and 1 nm, 1.5 nm, 2 nm, 2.5 nm, and 3 nm can be selected.

[0036] The front doped polysilicon layer 22 is an N-type doped polysilicon layer, such as a phosphorus doped polysilicon layer or a carbon doped polysilicon layer, and the doping concentration is 1E20cm -3 ~9E20cm -3 ; The thickness is 1nm~120nm, preferably 80nm~100nm.

[0037] The solar cell 100 further includes a front passivation layer 3 located on the front side of the front doped polysilicon layer 22. The front passivation layer 3 is preferably an aluminum oxide layer. The thickness of the front passivation layer 3 is 2 nm to 7 nm, preferably 3 to 6 nm.

[0038] The solar cell 100 further includes a front anti-reflection layer 4 located on the front side of the front passivation layer 3 to reduce light reflectivity. The front anti-reflection layer 4 is a laminated film of one or more of a silicon nitride film, a silicon oxynitride film, and a silicon oxide film, and the thickness of the front anti-reflection layer 4 is 60nm to 130nm.

[0039] The front electrode 5 passes through the front anti-reflection layer 4 and the front passivation layer 3 and contacts the front doped polysilicon layer 22 , avoiding direct contact with the silicon substrate 1 .

[0040] Furthermore, the solar cell 100 further includes a back tunneling layer 6 , a back doped polysilicon layer 7 , a back passivation layer 8 , a back anti-reflection layer 9 and a back electrode 10 located on the back side of the silicon substrate 1 .

[0041] The back tunneling layer 6 may be formed by related technologies, such as a silicon oxide layer or a silicon oxynitride layer, with a thickness of 1 nm to 3 nm, preferably 1 nm to 2.5 nm, and more preferably 1.5 nm to 2 nm.

[0042] The back-doped polysilicon layer 7 is a P-type doped polysilicon layer, such as a boron-doped polysilicon layer. The doping concentration is 3E18 cm -3 ~3E19cm -3, square resistance is 250~300ohm / sq; thickness is 50nm~150nm, preferably 80nm~100nm.

[0043] The back tunneling layer 6 and the P-type doped polysilicon layer constitute a carrier transport layer, forming a PN junction with the silicon substrate 1; at the same time, the back tunneling layer 6 and the P-type doped polysilicon layer constitute a back passivation contact structure to achieve back field passivation and improve battery efficiency.

[0044] The back passivation layer 8 is used to passivate the P-type doped polysilicon layer and is an optional film layer. In the present invention, the back passivation layer 8 is an aluminum oxide layer with a thickness of 2nm to 7nm, preferably 3nm to 6nm.

[0045] The back anti-reflection layer 9 is used to reduce the light reflectivity of the back side and is also an optional film layer. In the present invention, the back anti-reflection layer 9 is selected from one or more laminated films of silicon nitride, silicon oxynitride, and silicon oxide, with a thickness of 60nm to 130nm.

[0046] The back electrode 10 is a metal electrode, which passes through the back anti-reflection layer 9 and the back passivation layer 8 to contact the P-type doped polysilicon layer, but cannot penetrate the P-type doped polysilicon layer to damage the back tunneling layer 6 to avoid contact with the silicon substrate 1.

[0047] Please refer to Figure 2~Figure 11 As shown, the utility model also provides a method for preparing a solar cell 100, comprising the following steps:

[0048] Double-sided polishing: An N-type silicon wafer with a resistivity of 0.3 ohm·cm to 1.0 ohm·cm is selected as the silicon substrate 1, and an alkali polishing is used to form a polished surface, and the tower base size is 8 to 15 μm.

[0049] Back Poly layer deposition: Figure 2 As shown, a back tunneling layer 6 and a polysilicon layer (poly Si) are deposited on the back side of a silicon substrate 1 using LPCVD equipment. The back tunneling layer 6 is a silicon oxide layer with a thickness of 1 nm to 3 nm, and the poly Si layer has a thickness of 50 nm to 150 nm.

[0050] Back Boron Diffusion: Figure 3 As shown, a P+ emitter is prepared on the back side using a high temperature deposition device, with a doping concentration of 3E18~3E19cm-3 and a square resistance of 250~300ohm / sq. During this process, a layer of borosilicate glass (BSG) M1 is formed on the front and back sides.

[0051] Front removal of BSG + velveting: Figure 4As shown, the BSG on the front side is first removed by a single-sided chain device; then a trough device is used to perform alkali texturing on the front side to form a pyramid texturing surface with a pyramid size of 0.5μm~3μm.

[0052] Front deposition of Poly Si: Figure 5 As shown, a 1nm~3nm tunneling silicon oxide layer is deposited on the front side by using the PECVD process, and then a layer of phosphorus-doped amorphous silicon or multiple layers of phosphorus-doped amorphous silicon layers with different doping concentrations are deposited, with a total thickness of 1nm~120nm, preferably 80~100nm.

[0053] Annealing: Annealing is performed in a high temperature annealing furnace at a temperature of 880°C to 980°C, preferably 900°C to 950°C. After annealing, doped amorphous silicon is converted into doped polysilicon, and doped amorphous silicide is converted into doped polysilicide. At the same time, phosphorus activation is completed to form a tunnel passivation contact structure on the front side.

[0054] Laser oxidation: Figure 6 As shown, laser oxidation equipment is used to perform laser processing on the front gate line area, and an oxide layer mask M2 is formed in the laser processing area using laser high temperature + oxygen in an oxygen-rich environment. The laser power is 10W~100w, the scanning speed is 30000 mm / s~60000mm / s, the frequency is 250 KHz~600KHz, and an oxide layer mask M2 with a thickness of 3nm~30nm is formed in the processing area.

[0055] Etching: Figure 7 , Figure 8 As shown, the SiO2+poly in the front non-laser area is removed using an alkaline solution + additive from a tank-type cleaning device, while the laser area is not affected because it is protected by an oxide layer; then hydrofluoric acid is used to remove the oxide layers on the front and back sides.

[0056] Double-sided passivation layer: Fig. 9 As shown, an aluminum oxide passivation layer is deposited on the front and back sides by ALD process, with a thickness of 2nm~7nm, preferably 3nm~6nm, to passivate the doped polysilicon layers on the front and back sides.

[0057] Double-sided anti-reflection layer: Fig.10 As shown, an anti-reflection layer is deposited on the front and back sides by PECVD. The anti-reflection layer can be one or more laminated films of silicon nitride, silicon oxynitride, and silicon oxide. The thickness of the anti-reflection layer is 60nm~130nm.

[0058] Screen printed electrodes: Fig.11 As shown, metal electrodes are printed on the front and back sides by screen printing, and then sintered and light-injected or electric-injected, and LIF-treated to form ohmic contacts.

[0059] Testing and sorting: Testing and sorting of battery cells and storage.

[0060] In summary, the solar cell 100 of the utility model can be regarded as a Topcon back-junction cell, which forms a patterned front passivation contact structure 2 by arranging a front tunneling layer 21 and a front doped polysilicon layer 22 in the front gate line area to avoid direct contact between the front electrode 5 and the silicon substrate 1, reduce the front metal under-recombination, thereby improving the cell efficiency by 0.1%~0.2%, and improving the product competitiveness.

[0061] It should be understood that although this specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each implementation mode may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

[0062] The series of detailed descriptions listed above are only specific descriptions of feasible implementation methods of the utility model. They are not intended to limit the protection scope of the utility model. Any equivalent implementation methods or changes that do not deviate from the technical spirit of the utility model should be included in the protection scope of the utility model.

Claims

1. A solar cell comprising a silicon substrate, a PN junction located on the back side of the silicon substrate and a back electrode; characterized in that: The front side of the silicon substrate has a gate line region and a non-gate line region. The solar cell further comprises a front tunneling layer, a front doped polysilicon layer and a front electrode which are only located in the gate line region.

2. The solar cell according to claim 1, characterized in that: The silicon substrate is an N-type silicon wafer, and the front-side doped polysilicon layer is an N-type doped polysilicon layer.

3. The solar cell according to claim 1, characterized in that: The front tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and / or the thickness of the front tunneling layer is 1 nm to 3 nm.

4. The solar cell according to claim 1, characterized in that: The thickness of the front doped polysilicon layer is 1 nm to 120 nm.

5. The solar cell according to claim 1, characterized in that: The solar cell further comprises a front passivation layer and a front anti-reflection layer located on the front side of the front doped polysilicon layer, and the front electrode passes through the front anti-reflection layer and the front passivation layer and contacts the front doped polysilicon layer; in The thickness of the front passivation layer is 2nm-7nm, and the thickness of the front anti-reflection layer is 60nm-130nm.

6. The solar cell according to claim 1, characterized in that: The front surface of the silicon substrate has a pyramid velvet structure.

7. The solar cell according to any one of claims 1 to 6, characterized in that: The silicon substrate is an N-type silicon wafer, and the solar cell comprises a back tunneling layer and a P-type doped polysilicon layer located on the back side of the silicon substrate.

8. The solar cell according to claim 7, characterized in that: The back tunneling layer is a silicon oxide layer or a silicon oxynitride layer, and / or the thickness of the back tunneling layer is 1 nm to 3 nm.

9. The solar cell according to claim 7, characterized in that: The thickness of the P-type doped polysilicon layer is 50nm-150nm.

10. The solar cell according to claim 7, characterized in that: The solar cell further comprises a back passivation layer and a back anti-reflection layer located on the back of the P-type doped polysilicon layer, and a back electrode passes through the back anti-reflection layer and the back passivation layer and contacts the back doped polysilicon layer; in The thickness of the back passivation layer is 2nm-7nm, and the thickness of the back anti-reflection layer is 60nm-130nm.

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