Display panel and electronic device

Abstract

The utility model discloses a display panel and an electronic device. The display panel according to one embodiment of the utility model comprises a substrate layer; a pixel defining film disposed on the base layer and defining a light emitting opening; a partition wall disposed on the pixel defining film and defining a partition wall opening portion corresponding to the light emitting opening portion; and a light-emitting element including an anode, an intermediate layer, and a cathode in contact with the partition wall, the light-emitting element being disposed at the partition wall opening, the partition wall including: a first partition wall layer disposed on the pixel defining film and formed of a transparent conductive oxide; and a second partition layer disposed on the first partition layer and formed of a metal or a silicon-based compound, the first partition layer including: a first portion disposed on the pixel defining film; a second portion spaced apart from the pixel defining film and having a step with the first portion; and a first side portion connecting the first portion and the second portion.

Description

Technical Field

[0001] The utility model relates to a display panel, an electronic device including the same and a method for manufacturing the display panel, and more particularly, to a display panel with improved transmittance, an electronic device including the same and a method for manufacturing the display panel. Background Art

[0002] Display devices such as televisions, monitors, smartphones, and tablets that provide images to users include display panels that display images. Various display panels are being developed as display panels, such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels.

[0003] An organic light emitting display panel may include an anode, a cathode and a light emitting pattern. The light emitting pattern may be separated according to each light emitting area, and the cathode provides a common voltage according to each light emitting area. Utility Model Content

[0004] The purpose of the utility model is to provide a display panel which improves the transmittance of light signals.

[0005] The purpose of the utility model is to provide an electronic device for improving the transmittance of light signals.

[0006] The purpose of the utility model is to provide a method for manufacturing a display panel with improved reliability.

[0007] According to one embodiment of the present invention, a display panel includes: a base layer; a pixel defining film, which is arranged on the base layer and defines a light-emitting opening; a partition wall, which is arranged on the pixel defining film and defines a partition wall opening corresponding to the light-emitting opening; and a light-emitting element, including an anode, an intermediate layer and a cathode in contact with the partition wall and arranged in the partition wall opening, wherein the partition wall includes: a first partition wall layer, which is arranged on the pixel defining film and is formed of a transparent conductive oxide; and a second partition wall layer, which is arranged on the first partition wall layer and is formed of a metal or a silicon compound, wherein the first partition wall layer includes: a first portion, which is arranged on the pixel defining film; a second portion, which is separated from the pixel defining film and has a step with the first portion; and a first side portion, which connects the first portion and the second portion.

[0008] It may be that the adjacent wall opening portion includes: a first region, in which the light-emitting element is configured; and a second region, having a width smaller than that of the first region, and the first side portion of the first adjacent wall layer includes: a first outer side portion, which defines the first region, and the second portion of the first adjacent wall layer includes: a second outer side portion, which defines the second region.

[0009] The cathode may be in contact with the first side surface portion of the first partition layer.

[0010] The partition wall may further include an organic film disposed between the first partition wall layer and the second partition wall layer.

[0011] The first portion of the first partition layer may be directly disposed on the pixel defining film.

[0012] The partition wall may have a partition space defined by the first portion, the first side portion, and a portion of the second partition wall layer, and the organic film may be arranged to fill the partition space.

[0013] The second partition layer may be arranged on the first portion and the organic film.

[0014] The outer side surface of the second portion and the outer side surface of the second partition layer may define an alignment surface.

[0015] The second partition wall layer may be directly disposed on the first partition wall layer.

[0016] The second partition layer may include: a third portion disposed on the first portion; a fourth portion spaced apart from the first portion and having a step with the third portion; and a second side portion connecting the third portion and the fourth portion.

[0017] The first barrier layer may be formed of at least one of indium tin oxide, indium zinc oxide, zinc oxide, indium zinc tin oxide, and indium oxide.

[0018] The second partition layer may be formed of at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0019] The thickness of each of the first portion and the second portion may be greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms, and the thickness of the second partition layer may be greater than or equal to 1000 angstroms and less than or equal to 2000 angstroms.

[0020] The display panel may further include a sacrificial pattern disposed between the anode and the pixel defining film and defining a sacrificial opening portion overlapping the light emitting opening portion.

[0021] The display panel may further include: a thin film encapsulation layer disposed on the light emitting element and including a plurality of thin films, wherein the thin film encapsulation layer includes an encapsulation inorganic pattern covering the light emitting element and partially contacting the partition wall.

[0022] An electronic device according to an embodiment of the present invention includes: a display device including a display area and a non-display area adjacent to the display area, the display area including a first area through which a light signal passes and a second area adjacent to the first area; and an electronic module, which is arranged on the lower side of the display device, overlaps with the first area, and receives the light signal, the display device includes: a base layer; a partition wall, which is arranged on the base layer and defines a partition wall opening; and a light-emitting element, including an anode, an intermediate layer, and a cathode in contact with the partition wall, and arranged in the partition wall opening, the partition wall including: a first partition wall layer, which is arranged on the base layer and is formed of a transparent conductive oxide; a second partition wall layer, which is arranged on the first partition wall layer and is formed of a metal or a silicon compound; and an organic film, which is arranged between the first partition wall layer and the second partition wall layer.

[0023] According to an embodiment of the utility model, a display panel manufacturing method includes: providing a preliminary display panel including a base layer, an anode arranged on the base layer, and a preliminary pixel defining film arranged on the base layer and covering the anode; forming an inorganic film defining an opening portion exposing the top of the preliminary pixel defining film on the preliminary display panel; forming a first preliminary partition wall layer overlapping at least the opening portion and including a transparent conductive oxide; forming a second preliminary partition wall layer including a metal or a silicon compound on the first preliminary partition wall layer; forming a photoresist pattern overlapping the opening portion on the second preliminary partition wall layer; using the photoresist pattern as a mask to etch the inorganic film, the first preliminary partition wall layer and the second preliminary partition wall layer to form a partition wall defining a partition wall opening portion overlapping the anode; and forming a cathode in the partition wall opening portion that contacts the light-emitting pattern and the partition wall.

[0024] The step of forming the partition wall may include: a step of etching the inorganic film, the first preliminary partition wall layer and the second preliminary partition wall layer once; and a step of etching the inorganic film twice, wherein the inorganic film is removed in the step of etching the inorganic film twice.

[0025] It may be that a first partition wall layer and a second partition wall layer are formed in the step of forming the partition wall, and the first partition wall layer includes: a first part, which is adjacent to the base layer; a second part, which is separated from the base layer and has a step with the first part; and a first side part, which connects the first part and the second part, and the outer side surface of the second part is closer to the center of the anode than the outer side surface of the first side part.

[0026] It may be that, in the step of forming the first preliminary partition layer, a groove portion overlapping the opening portion is formed in the first preliminary partition layer, and the display panel manufacturing method further includes a step of providing an organic substance to the groove portion to form an organic film before the step of forming the second preliminary partition layer.

[0027] The display panel of an embodiment can improve the transmittance of light signals to improve display quality. The electronic device of an embodiment can include a display panel with improved transmittance to improve reliability. The manufacturing method of a display panel of an embodiment can provide a manufacturing method of a display panel with improved transmittance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a three-dimensional diagram of an electronic device according to an embodiment of the present utility model.

[0029] Figure 2a It is an exploded perspective view of an electronic device according to an embodiment of the present utility model.

[0030] Figure 2b is a block diagram of an electronic device according to an embodiment of the present utility model.

[0031] Figure 3 It is a cross-sectional view of a display module according to an embodiment of the present invention.

[0032] Figure 4a It is a plan view of a display panel according to an embodiment of the utility model.

[0033] Figure 4b is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0034] Figure 5 It is a plan view of a part of the display area of ​​the display panel according to an embodiment of the present invention.

[0035] Figure 6 is a cross-sectional view of a display panel according to an embodiment of the present utility model.

[0036] Figure 7a is a cross-sectional view of a display panel according to an embodiment of the present utility model.

[0037] Figure 7b It is enlarged to show Figure 7a A magnified view of the AA' region.

[0038] Figure 8 is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0039] Figure 9a is a cross-sectional view of a display panel according to an embodiment of the present invention.

[0040] Figure 9b It is enlarged to show Figure 9a A magnified view of the BB' region.

[0041] Fig.10 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention.

[0042] Figures 11a to 11n It is a cross-sectional view showing a part of the steps of a method for manufacturing a display panel according to an embodiment of the present invention.

[0043] (Explanation of Reference Numerals)

[0044] 1000: Electronic device DD: Display device

[0045] DP: Display Panel BS: Base Layer

[0046] PDL: Pixel Definition Layer ED1, ED2, ED3: Light Emitting Elements

[0047] PW: Partition wall L1: First partition wall layer

[0048] L2: Second partition layer OF: Organic film DETAILED DESCRIPTION

[0049] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0050] In this specification, when any constituent element (or region, layer, part, etc.) is mentioned as being "on" other constituent elements, "connected to" or "combined to" other constituent elements, it means that it can be directly configured / connected / combined to other constituent elements or a third constituent element can be configured between them.

[0051] The same reference numerals refer to the same components. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content. "And / or" includes all combinations that can be defined by the associated components.

[0052] The terms "first", "second" and the like may be used to describe various constituent elements, but the constituent elements are not limited by the terms. The terms are used only for the purpose of distinguishing one constituent element from other constituent elements. For example, without departing from the scope of the invention, the first constituent element may be named as the second constituent element, and similarly, the second constituent element may be named as the first constituent element. Singular expressions include plural expressions unless otherwise expressly indicated in the context.

[0053] In addition, terms such as “below”, “lower side”, “above”, and “upper side” are used to explain the relationship between components shown in the drawings. These terms are relative concepts and are explained based on the directions shown in the drawings.

[0054] The terms "including" or "having" should be understood as being used to specify the existence of the features, numbers, steps, tasks, constituent elements, parts or their combinations recorded in the specification, and do not preclude the existence or additional possibilities of one or more other features or numbers, steps, tasks, constituent elements, parts or their combinations.

[0055] In this specification, "direct configuration" may mean that there is no additional layer, film, region, disk, etc. between a layer, film, region, disk, etc. part and another part. For example, "direct configuration" may mean that no additional member such as a bonding member is used between two layers or two parts.

[0056] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs. In addition, terms such as terms defined in commonly used dictionaries should be interpreted as having the same meanings as those in the context of the relevant technology, and should not be interpreted as too idealistic or too formalistic unless explicitly defined herein.

[0057] Hereinafter, a display device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

[0058] Figure 1 is a three-dimensional diagram of an electronic device 1000 according to an embodiment of the present invention.

[0059] Reference Figure 1 In this embodiment, the electronic device 1000 is exemplarily shown as a mobile phone. However, it is not limited thereto, and the electronic device 1000 may be a tablet, a monitor, a television, a car navigation system, a game console, or a wearable device.

[0060] The electronic device 1000 may display an image through the display area 1000A. The display area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The display area 1000A may also include curved surfaces respectively bent from at least two sides of the plane. However, the shape of the display area 1000A is not limited thereto. For example, the display area 1000A may also include only the plane, and the display area 1000A may also include four curved surfaces respectively bent from at least two, for example, four sides of the plane.

[0061] A portion of the display area 1000A may be defined as a sensing area 1000SA. Figure 1 One sensing area 1000SA is exemplarily shown in the figure, but the number of sensing areas 1000SA is not limited thereto. The sensing area 1000SA may be a part of the display area 1000A, but may have a high light transmittance compared to other areas in the display area 1000A except the sensing area 1000SA. Therefore, the sensing area 1000SA may be an area that transmits light while displaying an image. The light mentioned herein (hereinafter, the light signal) may include visible light, but is not limited thereto, and may include various forms that can sense signals, such as ultraviolet rays, infrared rays, etc., and is not limited to any one embodiment.

[0062] The electronic device 1000 may include an electronic optical module configured in an area overlapping with the sensing area 1000SA. The electronic optical module may receive an optical signal provided from the outside through the sensing area 1000SA, or output an optical signal through the sensing area 1000SA. For example, the electronic optical module may be a camera module, a sensor for measuring the distance between an object and a mobile phone such as a proximity sensor, a sensor for identifying a part of a user's body (e.g., a fingerprint, an iris, or a face), or a small lamp that outputs light, but is not particularly limited thereto.

[0063] The thickness direction of the electronic device 1000 may be the normal direction of the display region 1000A, that is, the third direction DR3. The front (or top) and back (or bottom) of the components constituting the electronic device 1000 may be defined based on the third direction DR3.

[0064] Figure 2a It is an exploded perspective view of an electronic device 1000 according to an embodiment of the present invention. Figure 2b is a block diagram of an electronic device 1000 according to an embodiment of the present invention.

[0065] like Figure 2a as well as Figure 2bAs shown, the electronic device 1000 may include a display device DD, an electronic module EM, an electronic optical module EOM, a power module PSM, and a housing HM. The electronic device 1000 may also include additional structures not shown.

[0066] The display device DD generates images and senses at least external inputs. The display device DD includes a window WM and a display module DM.

[0067] The window WM provides the front of the electronic device 1000. The window WM may include a glass film or a synthetic resin film as a base film. The window WM may also include an anti-reflection layer or an anti-fingerprint layer. The window WM may also include a frame pattern overlapping the non-display area NDA of the display panel DP. The window WM and the display module DM may be combined by an adhesive layer not shown.

[0068] The display module DM may include at least a display panel DP. Figure 2a In the embodiment, only the display panel DP is shown in the stacked structure of the display module DM, but the display module DM may actually include a plurality of structures disposed on the upper side of the display panel DP. The stacked structure of the display module DM will be described in detail later.

[0069] The display panel DP may include a display area DA and a non-display area NDA. The display area DA may correspond to Figure 1 The display area 1000A shown. The pixels PX are arranged in the display area DA. Specifically, the light emitting elements may be arranged in the display area DA, and the light emitting elements may not be arranged in the non-display area NDA. On the other hand, in this specification, "areas / parts and areas / parts corresponding to each other" means overlapping, and is not limited to the same area. The display area DA may include a first area A1 and a second area A2.

[0070] The first area A1 may overlap with the sensing area 1000SA of the electronic device 1000. Figure 2a , the first area A1 is shown to have a circular shape, but the embodiment is not limited thereto. Figure 2a Different from the above, the first area A1 may also have various shapes such as polygon, ellipse, figure with at least one curved edge or atypical shape. Alternatively, the first area A1 is called a component area, and the second area A2 is called a main display area or a general display area.

[0071] At least a portion of the first area A1 may have a higher transmittance than the second area A2. Alternatively, the resolution of the first area A1 may be lower than the resolution of the second area A2, but is not limited thereto. For example, at least a portion of the first area A1 may have a higher transmittance than the second area A2, and the resolution of the first area A1 is substantially the same as the resolution of the second area A2. The first area A1 may overlap with the electronic optical module EOM described later.

[0072] The display panel DP may include a plurality of pixels PX (refer to Figure 4a ). Multiple pixels PX (refer to Figure 4a ) may include a first pixel emitting light from a first area A1 and a second pixel emitting light from a second area A2. Each of the first pixel and the second pixel may be provided in plurality. In this case, each of the first and second pixels may include a red pixel, a green pixel, and a blue pixel, but may also include a white pixel according to an embodiment. It may be that the first pixel includes a first light-emitting element and a first pixel circuit driving the first light-emitting element, and the second pixel includes a second light-emitting element and a second pixel circuit driving the second light-emitting element.

[0073] The first area A1 can be Figure 1 The sensing area 1000SA shown in FIG. 1 overlaps or corresponds to the sensing area 1000SA shown in FIG. Figure 2a The electron optical module EOM is shown as overlapping regions on a plane. For example, external input (eg, light) can be provided to the electron optical module EOM through the first region A1, and output from the electron optical module EOM can be emitted to the outside through the first region A1.

[0074] In order to ensure the area of ​​the transmission area, a smaller number of pixels than the second area A2 may be provided to the first area A1. Within a unit area or the same area, the number of first pixels configured in the first area A1 may be less than the number of second pixels configured in the second area A2. For example, the resolution of the first area A1 may be about 1 / 2, 3 / 8, 1 / 3, 1 / 4, 2 / 9, 1 / 8, 1 / 9, 1 / 16, etc. of the resolution of the second area A2. For example, the resolution of the second area A2 may be about 400 ppi or more, and the resolution of the first area A1 may be about 200 ppi or 100 ppi. However, this is only an example and is not particularly limited thereto.

[0075] like Figure 2aAs shown, a driving chip DIC may be arranged on the non-display area NDA of the display panel DP. A flexible circuit substrate FCB may be combined with the non-display area NDA of the display panel DP. The flexible circuit substrate FCB may be connected to the main circuit substrate. The main circuit substrate may be an electronic component constituting the electronic module EM. The bending area BA of the non-display area NDA may be bent so that the flexible circuit substrate FCB is arranged on the lower side of the display area DA.

[0076] The driving chip DIC may include a driving element (eg, a data driving circuit) for driving the pixel PX. Figure 2a 2 shows a structure in which the driving chip DIC is mounted on the display panel DP, but the present invention is not limited thereto. For example, the driving chip DIC may also be mounted on a flexible circuit substrate FCB.

[0077] The electronic module EM and the power module PSM can be accommodated in the housing HM. The housing HM is combined with the display device DD, especially with the window WM to accommodate the other modules.

[0078] like Figure 2b As shown, the display device DD may include a display panel DP and a sensor SS. The sensor SS may include any one or more of an input sensor, an antenna sensor, and a fingerprint sensor.

[0079] The electronic module EM may include a control module E-10, a wireless communication module E-20, an image input module E-30, a sound input module E-40, a sound output module E-50, a memory E-60, and an external interface module E-70, etc. The electronic module EM may include a main circuit substrate, and the module may be mounted on the main circuit substrate, or electrically connected to the main circuit substrate through a flexible circuit substrate. The electronic module EM is electrically connected to the power supply module PSM.

[0080] The control module E-10 controls the overall operation of the electronic device 1000. For example, the control module E-10 activates or deactivates the display device DD in accordance with user input. The control module E-10 can control the image input module E-30, the sound input module E-40, the sound output module E-50, etc. in accordance with user input. The control module E-10 may include at least one microprocessor.

[0081] The wireless communication module E-20 can use Bluetooth or WiFi lines to send / receive wireless signals with other terminals. The wireless communication module E-20 can use general communication lines to send / receive sound signals. The wireless communication module E-20 can include multiple antenna modules.

[0082] The image input module E-30 processes the image signal and converts it into image data that can be displayed on the display device DD. The sound input module E-40 receives the external sound signal through the microphone in the recording mode, the speech recognition mode, etc. and converts it into electrical speech data. The sound output module E-50 converts the sound data received from the wireless communication module E-20 or the sound data stored in the memory E-60 and outputs it to the outside.

[0083] The external interface module E-70 serves as an interface for connecting to an external charger, a wired / wireless data port, a card slot (eg, a memory card, a SIM / UIM card), etc.

[0084] The power module PSM supplies power required for the overall operation of the electronic device 1000. The power module PSM may include a conventional battery device.

[0085] The electronic optical module EOM may be an electronic component that outputs or receives an optical signal. The electronic optical module EOM may include a camera module and / or a proximity sensor. The camera module captures an external head portrait through the sensing area 1000SA.

[0086] Figure 3 It is a cross-sectional view of a display module according to an embodiment of the present invention.

[0087] Reference Figure 3 The display module DM may include a display panel DP and an input sensor INS. Although not shown separately, the display device DD according to an embodiment of the present invention (see Figure 2a ) may also include a protective component arranged under the display panel DP or an anti-reflection component and / or a window component arranged on the input sensor INS.

[0088] The display panel DP may be a light-emitting display panel. However, this is exemplary and not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer in the organic light-emitting display panel may include an organic light-emitting substance. The light-emitting layer in the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described using an organic light-emitting display panel.

[0089] The display panel DP may include a base layer BL, a circuit element layer DP-CL configured on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly configured on the thin film encapsulation layer TFE. In this specification, "the A structure is directly configured on the B structure" means that no adhesive layer is configured between the A structure and the B structure.

[0090] The base layer BL may include at least one plastic sheet. The base layer BL may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate as a flexible substrate. Figure 2a The display area DA and the non-display area NDA described in the figure may be similarly defined on the base layer BL.

[0091] The circuit element layer DP-CL may include at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, and the like.

[0092] The display element layer DP-OLED may include a partition wall and a light emitting element. The light emitting element may include an anode, an intermediate layer and a cathode.

[0093] The thin film encapsulation layer TFE may include a plurality of thin films, some of which may be configured to improve optical efficiency, and some of which may be configured to protect the organic light emitting diode.

[0094] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single-layer or multi-layer conductive layer. In addition, the input sensor INS may include a single-layer or multi-layer insulating layer. The input sensor INS may sense the external input in a capacitive manner. However, it is exemplary and not limited thereto. For example, in one embodiment, the input sensor INS may also sense the external input in an electromagnetic induction manner or a pressure sensing manner. On the other hand, in another embodiment of the present invention, the input sensor INS may be omitted.

[0095] Figure 4a is a plan view of a display panel according to an embodiment of the utility model.

[0096] Reference Figure 4a In the display panel DP, a display area DA and a non-display area NDA around the display area DA can be defined. The display area DA and the non-display area NDA can be distinguished by whether or not pixels PX are configured. Pixels PX can be configured in the display area DA. A scanning driving unit SDV, a data driving unit, and a light emitting driving unit EDV can be configured in the non-display area NDA. The data driving unit can be a part of the circuit configured in the driver chip DIC.

[0097] The display panel DP may include pixels PX, initialization scan lines GIL1-GILm, compensation scan lines GCL1-GCLm, write scan lines GWL1-GWLm, black scan lines GBL1-GBLm, emission control lines ECL1-ECLm, data lines DL1-DLn, first and second control lines CSL1 and CSL2, a driving voltage line PL, and a plurality of pads PD. Here, m and n are natural numbers greater than or equal to 2.

[0098] The pixels PX may be connected to the initialization scan lines GIL1-GILm, the compensation scan lines GCL1-GCLm, the writing scan lines GWL1-GWLm, the black scan lines GBL1-GBLm, the emission control lines ECL1-ECLm, and the data lines DL1-DLn.

[0099] The initialization scan lines GIL1-GILm, the compensation scan lines GCL1-GCLm, the write scan lines GWL1-GWLm, and the black scan lines GBL1-GBLm may extend in the first direction DR1 and be electrically connected to the scan driving part SDV. The data lines DL1-DLn may extend in the second direction DR2 and be electrically connected to the driving chip DIC. The emission control lines ECL1-ECLm may extend in the first direction DR1 and be electrically connected to the emission driving part EDV.

[0100] The driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be disposed on different layers from each other. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0101] The first control line CSL1 may be connected to the scan driving part SDV, and the second control line CSL2 may be connected to the light emitting driving part EDV.

[0102] The driving chip DIC, the driving voltage line PL, the first control line CSL1, and the second control line CSL2 may be electrically connected to the pad PD. The circuit substrate FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may be a pad for connecting the circuit substrate FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1, and the second control line CSL2.

[0103] In addition, the pad PD may also include an input pad. The input pad may be used to connect the circuit substrate FCB to the input sensor INS (see Figure 3) pad. However, not limited to this, the input pad may be configured in the input sensor INS, thereby connecting the pad PD to a separate circuit substrate. Alternatively, the input sensor INS may be omitted, and the input pad may not be included.

[0104] Figure 4b is an equivalent circuit diagram of a pixel according to an embodiment of the present invention.

[0105] exist Figure 4b A plurality of pixels PX are shown as an example (see Figure 4a ) is an equivalent circuit diagram of one pixel PXij in FIG. Each of the plurality of pixels PX has the same circuit configuration, and thus a detailed description of the remaining pixels PX is omitted by describing the circuit configuration of the pixel PXij.

[0106] Reference Figure 4a as well as Figure 4b , the pixel PXij is connected to the i-th data line DLi among the data lines DL1-DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1-GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1-GCLm, the j-th write scan line GWLj among the write scan lines GWL1-GWLm, the j-th black scan line GBLj among the black scan lines GBL1-GBLm, the j-th light emission control line ECLj among the light emission control lines ECL1-ECLm, the first and second driving voltage lines VL1, VL2, and the first and second initialization voltage lines VL3, VL4. i is an integer greater than 1 and less than n, and j is an integer greater than 1 and less than m.

[0107] The pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example of the present invention, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing into the light emitting element ED in accordance with the data signal Di. The light emitting element ED may emit light at a predetermined brightness in accordance with the amount of current provided from the pixel circuit PDC.

[0108] The pixel circuit PDC may include first to seventh transistors T1, T2, T3, T4, T5, T6, T7, and first to third capacitors Cst, Cbst, Nbst. According to the present invention, the structure of the pixel circuit PDC is not limited to Figure 4b The embodiment shown. Figure 4b The pixel circuit PDC shown is just an example and the pixel circuit PDC may be implemented in a modified manner.

[0109] At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having a low-temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be a transistor having an oxide semiconductor layer. For example, the third and fourth transistors T3 and T4 may be oxide semiconductor transistors, and the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be LTPS transistors.

[0110] Specifically, in the case of the first transistor T1 that directly affects the brightness of the light-emitting element ED, it is configured to include a semiconductor layer composed of polycrystalline silicon with high reliability, and a high-resolution display device can be realized by it. On the other hand, oxide semiconductors have high carrier mobility and low leakage current, so even if the driving time is long, the voltage drop is not large. That is, when driven at a low frequency, the color change of the image according to the voltage drop is not large, so low-frequency driving can be performed. In this way, in the case of oxide semiconductors, there is an advantage of less leakage current, so at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 can be used as an oxide semiconductor, thereby preventing leakage current that can flow to the gate electrode while reducing power consumption.

[0111] Some of the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 may be P-type transistors, and the rest may be N-type transistors. For example, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, and T7 may be P-type transistors, and the third and fourth transistors T3 and T4 may be N-type transistors.

[0112] The structure of the pixel circuit PDC according to the utility model is not limited to Figure 4b The embodiment shown. Figure 4b The pixel circuit PDC shown is only an example, and the structure of the pixel circuit PDC can be implemented in a modified manner. For example, the first to seventh transistors T1, T2, T3, T4, T5, T6, T7 can all be P-type transistors or N-type transistors. Alternatively, the first, second, fifth and sixth transistors T1, T2, T5, T6 are P-type transistors, and the third, fourth and seventh transistors T3, T4, T7 are N-type transistors.

[0113] The jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj can respectively transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di can have the same value as that input to the display device DD (refer to Figure 2a )’s image signal corresponding to the voltage level.

[0114] The first and second driving voltage lines VL1 and VL2 can transmit the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 can transmit the first initialization voltage VINT and the second initialization voltage VAINT to the pixel PXij, respectively.

[0115] The first transistor T1 is connected between the first driving voltage line VL1 receiving the first driving voltage ELVDD and the light emitting element ED. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or, referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end of the first capacitor Cst (e.g., a first node N1). The first transistor T1 can receive the i-th data signal Di transmitted by the i-th data line DLi according to the switching operation of the second transistor T2 and supply a driving current to the light emitting element ED.

[0116] The second transistor T2 is connected between the data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 can be turned on according to the write scan signal GWj received through the j-th write scan line GWLj and transfer the i-th data signal Di transmitted from the i-th data line DLi to the first electrode of the first transistor T1. It can be that one end of the second capacitor Cbst is connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst is connected to the first node N1.

[0117] The third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th compensation scan line GCLj. The third transistor T3 can be turned on according to the j-th compensation scan signal GCj received through the j-th compensation scan line GCLj to connect the third electrode of the first transistor T1 and the second electrode of the first transistor T1 to each other so that the first transistor T1 is diode-connected. It can be that one end of the third capacitor Nbst is connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst is connected to the first node N1.

[0118] The fourth transistor T4 is turned on between the first initialization voltage line VL3 to which the first initialization voltage VINT is applied and the first node N1. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the j-th initialization scan line GILj. The fourth transistor T4 is turned on according to the j-th initialization scan signal GIj received through the j-th initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0119] The fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (for example, a gate electrode) connected to the j-th light emitting control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element ED, and a third electrode (for example, a gate electrode) connected to the j-th light emitting control line ECLj.

[0120] The fifth and sixth transistors T5 and T6 are simultaneously turned on according to the jth light emitting control signal EMj received through the jth light emitting control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 is compensated by the diode-connected first transistor T1 and can be transmitted to the light emitting element ED through the sixth transistor T6.

[0121] The seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VAINT, a second electrode connected to a second electrode of the sixth transistor T6, and a third electrode (eg, a gate electrode) connected to a black scan line GBLj. The second initialization voltage VAINT may have a voltage level lower than or equal to the first initialization voltage VINT.

[0122] One end of the first capacitor Cst may be connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst may be connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 transmitting the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0123] Figure 5 It is a plan view of a part of the display area of ​​the display panel according to an embodiment of the present invention.

[0124] Reference Figure 5 The display area DA may include first to third light emitting areas PXA-R, PXA-G, PXA-B and a peripheral area NPXA surrounding the first to third light emitting areas PXA-R, PXA-G, PXA-B. The first to third light emitting areas PXA-R, PXA-G, PXA-B may correspond to the light emitting elements ED1, ED2, ED3 (refer to Figure 7a ) provides light to the area. The first to third light emitting areas PXA-R, PXA-G, PXA-B can be arranged according to the direction of the display module DM (refer to Figure 2a ) is divided by the color of the light emitted from the outside.

[0125] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may provide light of first to third colors having colors different from each other. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the examples of the first to third colors of light are not necessarily limited to the examples.

[0126] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may be defined as regions where the upper surface of the anode is exposed through a light emitting opening described later. The peripheral region NPXA may set the boundaries of the first to third light emitting regions PXA-R, PXA-G, and PXA-B and prevent color mixing between the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0127] Each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B may be provided in plurality and have a predetermined arrangement form in the display area DA and are repeatedly configured. For example, the first and third light emitting regions PXA-R and PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light emitting region PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged with each other along the second direction DR2.

[0128] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0129] on the other hand, Figure 5 The arrangement of the first to third light emitting regions PXA-R, PXA-G, and PXA-B is shown as an example, but is not limited thereto and may be arranged in various forms. In one embodiment, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the following configuration: Figure 5 Alternatively, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may also have a stripe arrangement or a diamond pixel arrangement.

[0130] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have various shapes on a plane, for example, the first to third light emitting regions PXA-R, PXA-G, and PXA-B may have polygonal, circular, or elliptical shapes. Figure 5 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily shown.

[0131] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape as each other on a plane, or at least a portion thereof may have a different shape from each other. Figure 5 The first and third light emitting regions PXA-R and PXA-B having the same shape as each other on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily shown.

[0132] At least a portion of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light-emitting region PXA-R that emits red light may be larger than the area of ​​the second light-emitting region PXA-G that emits green light, and smaller than the area of ​​the third light-emitting region PXA-B that emits blue light. However, the size relationship between the areas of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B according to the light-emitting color is not limited to this, and may vary according to the design of the display module DM (refer to FIG. 2 ). In addition, it is not limited to this, and the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may also have the same area on a plane.

[0133] On the other hand, the display module DM (refer to Figure 2a The shapes, areas, and arrangements of the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can be determined based on the color of the emitted light, the display module DM (see Figure 2a ) size, structure and design into various, not limited to Figure 5 The embodiment shown.

[0134] Figure 6 FIG. 1 is a cross-sectional view of a display panel according to an embodiment of the present utility model. Figure 6 It is shown along Figure 5 The cross section is taken along the I-I' interception line. Figure 7a is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 7a It is along Figure 5 A cross-sectional view taken along line II-II'. Figure 7b It is enlarged to show Figure 7a On the other hand, in the description Figure 6 , Figure 7a as well as Figure 7b Time reference Figure 5 The description will be given below, and the description of the same figure numerals will be omitted.

[0135] Figure 6 The display area DA is shown in an enlarged manner (see Figure 5 ) within a light emitting area PXA, Figure 6 The light emitting area PXA may correspond to Figure 5 Any one of the first to third light emitting areas PXA-R, PXA-G, PXA-B.

[0136] Reference Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0137] The display panel DP may include a plurality of insulating layers and semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers may be formed by coating, evaporation, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers are selectively patterned by photolithography and etching. In this manner, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0138] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transfer region SCL, first to fifth insulating layers 10, 20, 30, 40, 50, an upper electrode EE, and a plurality of connection electrodes CNE1, CNE2.

[0139] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may enhance the bonding force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0140] A semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon. However, the semiconductor pattern is not limited thereto, and may also include amorphous silicon or metal oxide. Figure 6 Only a part of the semiconductor pattern is exemplarily shown, and the semiconductor pattern can also be arranged in a plurality of light emitting regions PXA-R, PXA-G, PXA-B (refer to Figure 5 ). The semiconductor pattern may pass through a plurality of light emitting regions PXA-R, PXA-G, PXA-B and be arranged in a specific pattern. The semiconductor pattern may have different electrical properties depending on whether it is doped or not. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a first region doped with a P-type dopant.

[0141] The first region is more conductive than the second region and substantially functions as an electrode or a signal line. The second region may substantially correspond to the active region (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be the active region of a transistor, another portion may be the source or drain of the transistor, and another portion may be a conductive region.

[0142] The source S, the active electrode A, and the drain D of the transistor TR1 may be formed from a semiconductor pattern. Figure 6 2 shows a portion of a signal transmission region SCL formed from a semiconductor pattern. Although not shown separately, the signal transmission region SCL may be connected to the drain D of the transistor TR1 in a plane.

[0143] The first to fifth insulating layers 10, 20, 30, 40, 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, 50 may be inorganic layers or organic layers.

[0144] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The upper electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode EE.

[0145] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 penetrating the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0146] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0147] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining layer PDL, a partition wall PW, and a dummy pattern DMP.

[0148] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode). Each of the first to third light emitting elements ED1, ED2, ED3 to be described later may include Figure 6 The description of the anode AE, the emission pattern EP, and the cathode CE can be applied to the anode, the emission pattern, and the cathode of each of the first to third light emitting elements to be described later.

[0149] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 by the connection contact hole CNT-3 defined by penetrating the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transfer region SCL through the first and second connection electrodes CNE1 and CNE2, and electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer or multi-layer structure. The anode AE ​​may include multiple layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter, the lower ITO layer), a layer including Ag disposed on the lower ITO layer (hereinafter, the Ag layer), and a layer including ITO disposed on the Ag layer (hereinafter, the upper ITO layer).

[0150] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. The sacrificial pattern SP may correspond to a portion of a layer provided in a formation process of a partition opening OP-P to be described later to prevent damage to the anode AE. A sacrificial opening OP-S exposing a portion of the top of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with the light emitting opening OP-E to be described later. The sacrificial pattern SP may include an amorphous transparent conductive oxide. For example, the sacrificial pattern SP may be zinc oxide (ZnOx) doped with aluminum (Al).

[0151] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining film PDL may define a light emitting opening OP-E. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0152] In addition, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to this embodiment, the upper surface of the anode AE ​​may be separated from the pixel defining film PDL in a cross section via the sacrificial pattern SP, thereby preventing the anode AE ​​from being damaged during the formation process of the light emitting opening OP-E.

[0153] On a plane, the area of ​​the light-emitting opening OP-E may be smaller than the area of ​​the sacrificial opening OP-S. That is, the inner side surface of the pixel defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, not limited to this, the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may also be substantially aligned with the inner side surface of the pixel defining film PDL defining the corresponding light-emitting opening OP-E. At this time, the light-emitting area PXA may also be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0154] The pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). For example, silicon nitride (SiN x ). The pixel defining layer PDL may be disposed between the anode AE ​​and the partition wall PW so as to block the electrical connection between the anode AE ​​and the partition wall PW.

[0155] The partition wall PW may be disposed on the pixel defining film PDL. The partition wall opening OP-P may be defined on the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE. The partition wall opening OP-P defined on the partition wall PW may include a first region A1 and a second region A2. The width in the first direction DR1 of the first region A1 may be different from the width in the first direction DR1 of the second region A2. The width in the first direction DR1 of the first region A1 may be wider than the width in the first direction DR1 of the second region A2. The second region A2 of the partition wall opening OP-P may be a region defining a tip.

[0156] The partition wall PW may have an undercut shape in cross section. The partition wall PW may include a first partition wall layer L1, an organic film OF, and a second partition wall layer L2. The partition wall PW may include a first partition wall layer L1, an organic film OF, and a second partition wall layer L2 sequentially stacked along a thickness direction, ie, a third direction DR3.

[0157] The first partition layer L1 may be disposed adjacent to the pixel defining film PDL. The first partition layer L1 may be disposed on the pixel defining film PDL. The first partition layer L1 may be disposed directly on the pixel defining film PDL. The first partition layer L1 may be in contact with the cathode CE. The cathode CE may be in contact with the first partition layer L1, thereby receiving the second driving voltage ELVSS (refer to Figure 4b ).

[0158] Reference Figure 6 as well as Figure 7b The first partition layer L1 may have a groove shape that is recessed to a predetermined step based on the third direction DR3. The first partition layer L1 may have a shape in which the center of the first partition layer L1 is recessed toward the pixel defining film PDL on a reference plane that is separated from the pixel defining film PDL and is equivalent to a predetermined step. The first partition layer L1 may include a first portion P1 disposed on the pixel defining film PDL, a second portion P2 that is separated from the pixel defining film PDL and has a step with the first portion P1, and a first side portion S1 connecting the first portion P1 and the second portion P2.

[0159] The first portion P1 may be disposed on the pixel defining film PDL. The first portion P1 may be directly disposed on the pixel defining film PDL. The first portion P1 may be formed to extend along a fourth direction DR4 parallel to the upper surface of the base layer BL. The first portion P1 may include a first lower surface LF1 adjacent to the pixel defining film PDL and a first upper surface UF1 opposite to the first lower surface LF1 and separated from the pixel defining film PDL. The first lower surface LF1 may be in contact with the pixel defining film PDL. The first lower surface LF1 may define the lowermost surface of the partition wall PW.

[0160] The first side surface portion S1 may extend from both ends of the first portion P1. The first side surface portion S1 may connect the first portion P1 and the second portion P2. The first side surface portion S1 may be a portion in contact with the cathode CE in the first partition layer L1.

[0161] The first side surface S1 of the first partition layer L1 may include a first outer side surface OS1 adjacent to the anode AE ​​and a first inner side surface IS1 opposite to the first outer side surface OS1 and spaced apart from the anode AE. The first outer side surface OS1 of the first side surface S1 may extend from the first lower surface LF1 of the first portion P1 to connect the first lower surface LF1 and the second lower surface LF2 of the second portion P2. The first inner side surface IS1 of the first side surface S1 may extend from the first upper surface UF1 of the first portion P1 to connect the first upper surface UF1 and the second upper surface UF2 of the second portion P2.

[0162] The first side surface portion S1 may be formed to have an inclination. Each of the first inner side surface IS1 and the first outer side surface OS1 of the first side surface portion S1 may be an inclined surface. In one embodiment, the inclination of the first inner side surface IS1 and the first outer side surface OS1 may be an obtuse angle. Here, the inclination of the first inner side surface IS1 and the first outer side surface OS1 may mean the angle formed by each of the first inner side surface IS1 and the first outer side surface OS1 and the top of the base layer BL. That is, the angle formed by the first inner side surface IS1 and the top of the base layer BL and the angle formed by the first outer side surface OS1 and the top of the base layer BL may be obtuse angles, respectively. However, the embodiment is not limited thereto, and the inclination of each of the first inner side surface IS1 and the first outer side surface OS1 may be a right angle or an acute angle.

[0163] The second portion P2 may have a step with the first portion P1 based on the third direction DR3 and be separated from the first portion P1. The first side portion S1 may include one end connected to the first portion P1 and the other end connected to the second portion P2, and the second portion P2 may be formed extending from the other end of the first side portion S1. The second portion P2 may be formed extending in a direction parallel to the first direction DR1.

[0164] The first portion P1 and the second portion P2 may have a first step h1 based on the third direction DR3. The first step h1 may be defined as a height difference between a first lower side LF1 of the first portion P1 and a second lower side LF2 of the second portion P2.

[0165] The second portion P2 of the first partition layer L1 may include a second lower surface LF2 extending from the first outer side surface OS1 of the first side portion S1, a second upper surface UF2 extending from the first inner side surface IS1 of the first side portion S1, and a second outer side surface OS2 connecting the second lower surface LF2 and the second upper surface UF2. The second lower surface LF2 of the second portion P2 and the second upper surface UF2 of the second portion P2 may be opposite to each other in the third direction DR3.

[0166] The first thickness d of the first portion P1 1 and a second thickness d of the second portion P2 2 However, the embodiment is not limited thereto, and the first thickness d of the first portion P1 is 1 and a second thickness d of the second portion P2 2 In one embodiment, the thickness of each of the first portion P1 and the second portion P2 may be 1000 angstroms to 2000 angstroms. On the other hand, the thickness of the first portion P1 may be defined as the height difference between the first lower surface LF1 and the first upper surface UF1 of the first portion P1. The thickness of the second portion P2 may be defined as the height difference between the second lower surface LF2 and the second upper surface UF2 of the second portion P2.

[0167] The second partition layer L2 may be disposed on the first partition layer L1. The second partition layer L2 may be provided on the first partition layer L1 to improve the toughness of the undercut shape of the partition PW by increasing the mechanical strength of the partition PW. The second partition layer L2 may be formed together with the second portion P2 of the first partition layer L1 at the tip formed by the partition PW.

[0168] The second partition layer L2 may be formed extending in a direction parallel to the first direction DR1. The second partition layer L2 may include a third lower surface LF3 adjacent to the first partition layer L1, a third upper surface UF3 opposite to the third lower surface LF3 and separated from the first partition layer L1, and a third outer side surface OS3 connecting the third lower surface LF3 and the third upper surface UF3. The third upper surface UF3 of the second partition layer L2 may form the uppermost surface of the partition PW and define the upper surface formed on the tip of the partition PW.

[0169] The third outer side surface OS3 of the second partition wall layer L2 may be aligned with the second outer side surface OS2 of the second portion P2 of the first partition wall layer L1 and the third direction DR3. The second outer side surface OS2 of the second portion P2 and the third outer side surface OS3 of the second partition wall layer L2 may define an alignment surface.

[0170] In one embodiment, a partition space GP may be formed in the partition wall PW. The partition space GP may be defined by the first portion P1 of the first partition wall layer L1, the first side portion S1 of the first partition wall layer L1, and a portion of the second partition wall layer L2. Specifically, the partition space GP may be defined by the first upper surface UF1 of the first portion P1, the first inner side surface IS1 extending from both ends of the first upper surface UF1, and a portion of the third lower surface LF3 of the second partition wall layer L2.

[0171] The organic film OF may be disposed between the first partition layer L1 and the second partition layer L2. The organic film OF may be disposed in the partition space GP formed in the partition PW. The organic film OF may fill at least a portion of the partition space GP. The organic film OF may be disposed in the partition space GP to enhance the mechanical strength and transparency of the partition PW. The first partition layer L1 has a groove shape that is concave equivalent to a predetermined step, and has weak mechanical strength, so it may be easily broken by external pressure, but as the organic film OF is disposed in the partition space GP formed in the first partition layer L1, the mechanical strength of the partition PW may be enhanced. In one embodiment, the organic film OF may fill the partition space GP as a whole. The organic film OF may contact each of the first upper surface UF1 of the first portion P1 and the first inner side surface IS1 of the first side portion S1.

[0172] The second partition wall layer L2 may be disposed on the first partition wall layer L1 and the organic film OF. The second partition wall layer L2 may be in contact with each of the second portion P2 of the first partition wall layer L1 and the organic film OF.

[0173] In one embodiment, the first outer side surface OS1 of the first side portion S1 defines a first area A1 of the adjacent opening portion OP-P, the second outer side surface OS2 of the second portion P2 defines a portion of the second area A2 of the adjacent opening portion OP-P, and the third outer side surface OS3 of the second adjacent layer L2 defines the remaining portion of the second area A2 of the adjacent opening portion OP-P.

[0174] In one embodiment, with the light emitting area PXA as a reference, the first outer side surface OS1 of the first side portion S1 may be relatively recessed compared to the second outer side surface OS2 of the second portion P2. The second outer side surface OS2 of the second portion P2 defining a portion of the second area A2 may be closer to the center of the anode AE ​​than the first outer side surface OS1 defining the first area A1. The second portion P2 protruding toward the light emitting area PXA may define a tip together with the second partition layer L2. The second outer side surface OSF1-2 may be configured to be adjacent to the center of the anode AE ​​in a direction, for example, in the first direction DR1, compared to the first outer side surface OSF1-1.

[0175] The first partition layer L1 may include a light-transmitting material. The first partition layer L1 may include a transparent conductive material for signal transmission. For example, the first partition layer L1 may include a transparent conductive oxide (TCO). The first partition layer L1 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and other transparent conductive oxides (TCO).

[0176] In one embodiment, the first partition layer L1 may include at least one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, indium zinc tin oxide, zinc oxide, and indium oxide. The first partition layer L1 may be composed of one of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, indium zinc tin oxide, zinc oxide, and indium oxide. In one embodiment, the first partition layer L1 may include indium tin oxide. The first partition layer L1 may be composed of indium tin oxide.

[0177] As the first partition layer L1 includes a transparent conductive oxide, the light transmittance of the partition PW can be improved. Figure 1) of the electronic device 1000( Figure 1 ) in the sensing area 1000SA( Figure 1 ) may require high transmittance. When the partition wall PW is formed of a material including an opaque metal, light blocking by the metal may occur and it may be difficult to ensure transmittance. According to the utility model, the first partition wall layer L1 includes a transparent conductive oxide, and as it has a groove shape having a recess equivalent to a predetermined step, the first partition wall layer L1 can have a film structure with high transmittance and a relatively thin thickness, so the amount of light transmitted through the partition wall PW can be increased and the transmittance can be improved. That is, as the first partition wall layer L1 includes a transparent conductive oxide, the transmittance of the light signal can be further improved in the first area A1 corresponding to the area where the light signal is transmitted from the display panel DP. As the partition wall PW includes the first partition wall layer L1 containing a transparent conductive oxide, the optical properties such as the transmittance of the image displayed by the display device DD can be improved.

[0178] Compared to the first partition layer L1, the second partition layer L2 has a low conductivity, but may include a material with high strength. The second partition layer L2 may include a material with a high Young's modulus of more than 300 GPa. The second partition layer L2 may include a material with a large Young's modulus, thereby reducing the deformation of the second partition layer L2. As the deformation of the top second partition layer L2 forming the tip decreases, the toughness of the undercut shape of the partition PW can be increased. Thus, the drooping shape of the tip of the partition PW can be reduced or removed, and the shape of the outer side surface of the partition PW that blocks the tip from contacting the cathode CE can be reduced or removed.

[0179] In one embodiment, the second partition layer L2 may include a metal substance. The third partition layer L3 may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The second partition layer L2 may include a substance different from the first partition layer L1. For example, the second partition layer L2 may include titanium (Ti). The thickness of the second partition layer L2 may be more than 1000 angstroms and less than 2000 angstroms.

[0180] In the partition wall PW of one embodiment, the second partition wall layer L2 may not include a metal substance. The second partition wall layer L2 may include a silicon compound. The second partition wall layer L2 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). For example, the second partition layer L2 may include silicon oxide (SiO x). The second partition layer L2 is different from the first partition layer L1 in that it does not contact the cathode CE and has a pointed portion to separate the cathode CE from each light emitting region PXA, and therefore may also include an insulating material, namely, a silicon-based compound.

[0181] The organic film OF may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and polyethylene resin. For example, the organic film OF may include polyimide (PI) or polyethylene terephthalate (PET).

[0182] The light-emitting pattern EP may be arranged on the anode AE. The light-emitting pattern EP may include a light-emitting layer including a light-emitting substance. The light-emitting pattern EP may also include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the anode AE ​​and the light-emitting layer, and may also include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light-emitting layer. The light-emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0183] The light emitting pattern EP may be patterned by being defined at the tip of the partition wall PW. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0184] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by being defined at a tip of the partition wall PW. The cathode CE may be in contact with the first outer side surface OS1 of the first partition wall layer L1.

[0185] The next wall PW can receive the second driving voltage ELVSS (refer to Figure 4b ), whereby the cathode CE can be electrically connected to the adjacent wall PW, thereby receiving the second driving voltage ELVSS (refer to Figure 4b ).

[0186] According to an embodiment of the present invention, the display panel DP may further include a capping pattern CP. The capping pattern CP may be disposed in the partition wall opening OP-P and disposed on the cathode CE. The capping pattern CP may be patterned by being formed at a tip of the partition wall PW.

[0187] exist Figure 6 The capping pattern CP is exemplarily shown as not contacting the third outer side surface OS3 of the second partition layer L2, but is not limited thereto. For example, the capping pattern CP may also be formed to contact the third outer side surface OS3 of the second partition layer L2. On the other hand, according to another embodiment of the present invention, the capping pattern CP may be omitted.

[0188] The dummy pattern DMP may be disposed on the partition wall PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first to third dummy patterns D1, D2, and D3 may be sequentially stacked on the second partition wall layer L2 of the partition wall PW along the third direction DR3.

[0189] The first dummy pattern D1 may include an organic substance. For example, the first dummy pattern D1 may include the same substance as the light emitting pattern EP. The first dummy pattern D1 may be formed simultaneously with the light emitting pattern EP through one process and may be formed separately from the light emitting pattern EP by the undercut shape of the partition wall PW.

[0190] The second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed simultaneously with the cathode CE through one process and may be formed separately from the cathode CE by the undercut shape of the partition wall PW.

[0191] The third dummy pattern D3 may include the same material as the capping pattern CP. The third dummy pattern D3 may be formed simultaneously with the capping pattern CP through one process, and may be formed separately from the capping pattern CP by the undercut shape of the partition wall PW.

[0192] The dummy pattern DMP may define a dummy opening portion OP-D. The dummy opening portion OP-D may correspond to the light emitting opening portion OP-E. The dummy opening portion OP-D may include first to third regions sequentially arranged in the third direction DR3. The first region of the dummy opening portion OP-D may be defined by the inner side surface S1-D of the first dummy pattern D1, the second region may be defined by the inner side surface S2-D of the second dummy pattern D2, and the third region may be defined by the inner side surface S3-D of the third dummy pattern D3. On a plane, each of the first to third dummy patterns D1, D2, and D3 may be a closed line shape surrounding the light emitting region PXA.

[0193] exist Figure 6 The inner side surfaces of the first to third dummy patterns D1 , D2 , D3 are aligned with the third outer side surface OS3 of the second partition layer L2 , but the present invention is not limited thereto. The first to third dummy patterns D1 , D2 , D3 may also cover the third outer side surface OS3 of the second partition layer L2 .

[0194] The thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower encapsulation inorganic pattern LIL, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL.

[0195] The lower package inorganic pattern LIL may correspond to the light emitting opening OP-E. The lower package inorganic pattern LIL may cover the light emitting element ED and the dummy pattern DMP, and a portion thereof may be disposed inside the partition opening OP-P. According to one embodiment, the lower package inorganic pattern LIL may contact each of the first outer side surface OS1 of the first partition layer L1, the second outer side surface OS2, and the third outer side surface OS3 of the second partition layer L2.

[0196] The encapsulation organic film OL may cover the lower encapsulation inorganic pattern LIL and provide a flat upper surface. The upper encapsulation inorganic film UIL may be disposed on the encapsulation organic film OL.

[0197] The lower encapsulation inorganic pattern LIL and the upper encapsulation inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the encapsulation organic film OL may protect the display element layer DP-OLED from foreign matter such as dust particles.

[0198] Figure 7a A first light emitting region PXA-R, a second light emitting region PXA-G, and a third light emitting region PXA-B are shown in an enlarged manner. Figure 6 The description in the first light emitting region PXA can be equally applied to each of the first to third light emitting regions PXA-R, PXA-G, and PXA-B.

[0199] Reference Figure 7a According to the present embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, ED3, sacrificial patterns SP1, SP2, SP3, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0200] The light-emitting elements ED1, ED2, and ED3 may include a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3. The first light-emitting element ED1 may include a first anode AE1, a first light-emitting pattern EP1, and a first cathode CE1. The second light-emitting element ED2 may include a second anode AE2, a second light-emitting pattern EP2, and a second cathode CE2. The third light-emitting element ED3 may include a third anode AE3, a third light-emitting pattern EP3, and a third cathode CE3. The first to third anodes AE1, AE2, and AE3 may be provided in a plurality of patterns. In one embodiment, the first light-emitting pattern EP1 may provide red light, the second light-emitting pattern EP2 may provide green light, and the third light-emitting pattern EP3 may provide blue light.

[0201] The pixel defining film PDL may define the first to third light emitting openings OP1-E, OP2-E, and OP3-E. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The first light emitting region PXA-R may be defined as a region exposed by the first light emitting opening OP1-E in the upper surface of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The second light emitting region PXA-G may be defined as a region exposed by the second light emitting opening OP2-E in the upper surface of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3. The third light emitting region PXA-B may be defined as a region exposed by the third light emitting opening OP3-E in the upper surface of the third anode AE3.

[0202] The sacrificial patterns SP1, SP2, SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first to third sacrificial patterns SP1, SP2, SP3 may be disposed on the first to third anodes AE1, AE2, AE3, respectively. The first to third sacrificial openings OP1-S, OP2-S, OP3-S corresponding to the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively, may be defined in the first to third sacrificial patterns SP1, SP2, SP3.

[0203] In this embodiment, the first to third partition openings OP1-P, OP2-P, OP3-P corresponding to the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively, may be defined in the partition wall PW. Each of the first to third partition openings OP1-P, OP2-P, OP3-P may include Figure 6 The first area A1 (see Figure 6 ) and the second area A2 (refer to Figure 6). The partition wall PW may include a first partition wall layer L1, an organic film OF, and a second partition wall layer L2. The first partition wall layer L1 may include a first region A1 defining first to third partition wall openings OP1-P, OP2-P, OP3-P (see Figure 6 ) of the first side surface portion S1 (refer to Figure 7b ) of the first outer side surface OS1 (refer to Figure 7b ) and define a second area A2 (refer to Figure 6 ) of a second portion P2 of the second outer side surface OS2 (refer to Figure 7b The second partition layer L2 may include a second region A2 defining the first to third partition openings OP1-P, OP2-P, and OP3-P (see Figure 6 ) of the remaining portion of the third outer side surface OS3 (refer to Figure 7b ).

[0204] The first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P. The first to third cathodes CE1, CE2, and CE3 are respectively connected to the first side surface S1 (refer to Figure 7b )touch.

[0205] In this embodiment, the first to third cathodes CE1, CE2, CE3 can be formed by the second portion P2 of the first partition layer L1 forming the tip (refer to Figure 7b ) is physically separated from the second partition layer L2 and formed in each light emitting opening portion OP1-E, OP2-E, OP3-E, and is connected to the first side portion S1 of the first partition layer L1 (refer to Figure 7b ) are in contact with each other, thereby being electrically connected to each other and receiving a common voltage. The first partition layer L1 that each of the first to third cathodes CE1, CE2, and CE3 contacts has a relatively high conductivity compared to the second partition layer L2, thereby reducing the contact resistance with the first to third cathodes CE1, CE2, and CE3. Thus, a common cathode voltage can be uniformly provided to the light-emitting regions PXA-R, PXA-G, and PXA-B.

[0206] According to the present invention, the plurality of light emitting patterns EP1, EP2, EP3 can be patterned and deposited in pixel units by defining the tip of the partition wall PW. That is, the plurality of light emitting patterns EP1, EP2, EP3 can be formed together using an open mask, but can be easily divided into pixel units by the partition wall PW.

[0207] On the contrary, when a plurality of light-emitting patterns EP1, EP2, and EP3 are patterned by using a fine metal mask (FMM), a supporting spacer protruding from a conductive partition wall is provided to support the fine metal mask. In addition, since the fine metal mask is separated from the patterned base surface by a height equivalent to the partition wall and the spacer, the realization of high resolution may be limited. In addition, since the fine metal mask is in contact with the spacer, after the patterning process of the plurality of light-emitting patterns EP1, EP2, and EP3, foreign matter remains on the spacer, or the spacer is damaged due to the imprint of the fine metal mask. As a result, a poor display panel may be formed.

[0208] According to this embodiment, the partition wall PW is included, so that the light emitting elements ED1, ED2, and ED3 can be easily physically separated, thereby preventing current leakage or driving errors between adjacent light emitting regions PXA-R, PXA-G, and PXA-B, and each light emitting element ED1, ED2, and ED3 can be driven independently.

[0209] In particular, in the case where there is no Figure 2a ) is patterned with a mask that contacts the internal structure in the display panel DP, thereby providing a display panel DP with reduced defective rate and improved process reliability. Even if a separate supporting spacer protruding from the partition wall PW is not provided, the area of ​​the light-emitting regions PXA-R, PXA-G, and PXA-B can be refined as the patterning is performed, thereby providing a display panel DP that can easily achieve high resolution.

[0210] In addition, when manufacturing a large-area display panel DP, by omitting the large-area mask manufacturing, it is possible to provide a display panel DP that reduces process costs and improves process reliability without being adversely affected by the large-area mask.

[0211] The capping patterns CP1, CP2, CP3 may include a first capping pattern CP1, a second capping pattern CP2, and a third capping pattern CP3. The first to third capping patterns CP1, CP2, CP3 may be disposed on the first to third cathodes CE1, CE2, CE3, respectively, and disposed in the first to third partition openings OP1-P, OP2-P, OP3-P.

[0212] The dummy patterns DMP may include a plurality of first dummy patterns D1 , a plurality of second dummy patterns D2 , and a plurality of third dummy patterns D3 .

[0213] The first dummy pattern D1 may include 1-1 to 1-3 dummy patterns D11, D12, D13 surrounding the first to third light emitting regions PXA-R, PXA-G, PXA-B on a plane, respectively. The 1-1 to 1-3 dummy patterns D11, D12, D13 may include the same material as the first to third light emitting patterns EP1, EP2, EP3, respectively, and be formed by the same process as the first to third light emitting patterns EP1, EP2, EP3.

[0214] The second dummy pattern D2 may include 2-1st to 2-3rd dummy patterns D21, D22, D23 surrounding the first to third light emitting regions PXA-R, PXA-G, PXA-B on a plane, respectively. The 2-1st to 2-3rd dummy patterns D21, D22, D23 may include the same material as the first to third cathodes CE1, CE2, CE3, respectively, and be formed by the same process as the first to third cathodes CE1, CE2, CE3.

[0215] The third dummy pattern D3 may include 3-1st to 3-3rd dummy patterns D31, D32, D33 surrounding the first to third light emitting regions PXA-R, PXA-G, PXA-B on a plane, respectively. The 3-1st to 3-3rd dummy patterns D31, D32, D33 may include the same material as the first to third capping patterns CP1, CP2, CP3, respectively, and be formed by the same process as the first to third capping patterns CP1, CP2, CP3.

[0216] The dummy pattern DMP may define first to third dummy openings OP1-D, OP2-D, OP3-D corresponding to the first to third light-emitting openings OP1-E, OP2-E, OP3-E, respectively. The first dummy opening OP1-D may be defined by the inner side surfaces of the 1-1st, 2-1st, and 3-1st dummy patterns D11, D21, and D31, the second dummy opening OP2-D may be defined by the inner side surfaces of the 1-2nd, 2-2nd, and 3-2nd dummy patterns D12, D22, and D32, and the third dummy opening OP3-D may be defined by the inner side surfaces of the 1-3rd, 2-3rd, and 3-3rd dummy patterns D13, D23, and D33.

[0217] The thin film encapsulation layer TFE may include lower encapsulation inorganic patterns LIL1, LIL2, LIL3, an encapsulation organic film OL, and an upper encapsulation inorganic film UIL. In the present embodiment, the lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may include a first lower encapsulation inorganic pattern LIL1, a second lower encapsulation inorganic pattern LIL2, and a third lower encapsulation inorganic pattern LIL3. The first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 may correspond to the first to third light emitting openings OP1-E, OP2-E, OP3-E, respectively.

[0218] The first lower package inorganic pattern LIL1 may cover the first light emitting element ED1 and the 1-1st, 2-1st and 3-1st dummy patterns D11, D21 and D31, and a portion thereof may be arranged inside the first partition opening OP1-P. The second lower package inorganic pattern LIL2 may cover the second light emitting element ED2 and the 1-2nd, 2-2nd and 3-2nd dummy patterns D12, D22 and D32, and a portion thereof may be arranged inside the second partition opening OP2-P. The third lower package inorganic pattern LIL3 may cover the third light emitting element ED3 and the 1-3rd, 2-3rd and 3-3rd dummy patterns D13, D23 and D33, and a portion thereof may be arranged inside the third partition opening OP3-P. The first to third lower package inorganic patterns LIL1, LIL2 and LIL3 are provided in the form of patterns separated from each other.

[0219] Figure 8 as well as Figure 9a FIG. 1 is a cross-sectional view of a display panel according to an embodiment of the present invention. Figure 8 It is shown along Figure 5 The cross section is taken from I-I'. Figure 9a Shown along Figure 5 The II-II' intercept line is a cross section of the block. Figure 9b It is enlarged to show Figure 9a The enlarged view of the BB' region. Figure 8 , Figure 9a as well as Figure 9b When describing a display panel according to an embodiment of the present invention, Figure 6 , Figure 7a as well as Figure 7b The aforementioned structures are given the same figure marks and detailed descriptions are omitted.

[0220] Reference Figure 8 , Figure 9a as well as Figure 9b According to an embodiment of the present invention, a display panel and Figure 6Compared with the display panel shown in FIG. 1 , the difference is that the organic film OF is omitted in the partition wall PW-1. The second partition wall layer L2-1 can be directly arranged on the first partition wall layer L1-1. The second partition wall layer L2-1 can have a shape extending along the second portion P2, the first side portion S1 and the first portion P1 of the first partition wall layer L1-1. Thus, the second partition wall layer L2-1 can have a groove shape that is recessed with respect to the third direction DR3 and is equivalent to a predetermined step.

[0221] The second partition layer L2-1 may include a third portion P3 configured on the first portion P1 of the first partition layer L1-1, a fourth portion P4 separated from the first portion P1 and having a step with the third portion P3, and a second side portion S2 connecting the third portion P3 and the fourth portion P4. The third portion P3 of the second partition layer L2-1 may be directly configured on the first portion P1 of the first partition layer L1-1. The fourth portion P4 may have a step with the third portion P3 based on the third direction DR3 and be separated from the third portion P3. The fourth portion P4 may be directly configured on the second portion P2 of the first partition layer L1-1. The second side portion S2 may connect the third portion P3 and the fourth portion P4.

[0222] The thickness of the third portion P3 and the fourth portion P4 may be substantially the same. However, the embodiment is not limited thereto, and the thickness of the third portion P3 and the fourth portion P4 may be different from each other. In one embodiment, the thickness of each of the third portion P3 and the fourth portion P4 may be 1000 angstroms to 2000 angstroms. On the other hand, the thickness of the third portion P3 may be defined as the height difference between the bottom of the third portion P3 and the top of the third portion P3. The thickness of the fourth portion P4 may be defined as the height difference between the bottom of the fourth portion P4 and the top of the fourth portion P4.

[0223] In one embodiment, the outer side surface OS-2 of the second portion P2 of the first partition layer L1-1 and the outer side surface OS-3 of the third portion P3 of the second partition layer L2-1 may be aligned in the third direction DR3. The third portion P3 of the second partition layer L2-1 may be formed together with the first portion P1 of the first partition layer L1-1 at the tip formed by the partition PW.

[0224] Fig.10 is a flow chart of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11n FIG. 1 is a cross-sectional view showing a portion of the steps of a method for manufacturing a display panel according to an embodiment of the present invention. Figures 11a to 11n When, refer to Figures 1 to 9b The same / similar reference numerals are used for the same / similar structures, and duplicate description is omitted.

[0225] Reference Fig.10According to an embodiment of the present invention, a display panel manufacturing method includes the steps of providing a preliminary display panel (S100), forming an inorganic film (S200), forming a first preliminary partition layer (S300), forming a second preliminary partition layer (S400), forming a photoresist pattern (S500), forming a partition (S600), and forming a cathode (S700).

[0226] Reference Fig.11a The display panel manufacturing method according to the present embodiment may include the step of providing a preliminary display panel (S100). The preliminary display panel provided in the present embodiment may include a base layer BL, a circuit element layer DP-CL, first to third anodes AE1, AE2, AE3, first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I, and a preliminary pixel defining film PDL-1.

[0227] The circuit element layer DP-CL can be formed by forming an insulating layer, a semiconductor layer and a conductive layer by coating, evaporation, etc., and selectively patterning the insulating layer, the semiconductor layer and the conductive layer by photolithography and etching processes to form a general circuit element manufacturing process such as a semiconductor pattern, a conductive pattern and a signal line.

[0228] The first anode AE1 and the first preliminary sacrificial pattern SP1-I may be formed by the same patterning process, the second anode AE2 and the second preliminary sacrificial pattern SP2-I may be formed by the same patterning process, and the third anode AE3 and the third preliminary sacrificial pattern SP3-I may be formed by the same patterning process.

[0229] The preliminary pixel defining film PDL-1 may be disposed on the base layer BL. The preliminary pixel defining film PDL-1 may entirely cover the first to third anodes AE1, AE2, AE3 and the first to third preliminary sacrificial patterns SP1-I, SP2-I, SP3-I.

[0230] Reference Fig.11a as well as Fig.11b According to the display panel manufacturing method of the present embodiment, the step of forming an inorganic film 10F on the preliminary display panel (S200) may include the step of forming a preliminary inorganic film 10F on the preliminary pixel defining film PDL-1 and the step of patterning the preliminary inorganic film PIOF to form the preliminary inorganic film PIOF having an opening portion IOP exposing the upper surface of the preliminary pixel defining film PDL-1.

[0231] Reference Fig.11a, the preliminary inorganic film PIOF may overlap with the first to third anodes AE1, AE2, and AE3. The step of forming the preliminary inorganic film PIOF may be performed by an evaporation process of an inorganic substance. The preliminary inorganic film PIOF may be formed on the preliminary pixel defining film PDL-1 by evaporating an inorganic substance on the preliminary pixel defining film PDL-1. The inorganic substance used to form the preliminary inorganic film PIOF may include a substance formed by at least one selected from the group formed by oxygen (O), nitrogen (N), carbon (C), and hydrogen (H) and silicon (Si). The inorganic substance used to form the preliminary inorganic film PIOF may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon carbon nitride (SiCN), silicon carbide oxide (SiOC) and silicon carbon nitride oxide (SiCON). For example, the inorganic substance forming the preliminary inorganic film PIOF may include silicon nitride (SiN x ).

[0232] Reference Fig.11b , a step (S200) of forming an inorganic film IOF by etching the preliminary inorganic film PIOF may be performed. An area of ​​the preliminary inorganic film PIOF may be removed by etching or the like to form an inorganic film IOF having an opening IOP defined therein. The opening IOP may be formed by penetrating the inorganic film IOF to expose a portion of the upper surface of the preliminary pixel defining film PDL-1. Fig.11a as well as Fig.11b In the embodiment, the case where the inorganic film 10F is formed by an etching process is shown as an example, but the embodiment is not limited to this, and the inorganic film 10F may be formed to have an opening portion IOP during manufacture.

[0233] The inorganic film IOF may overlap each of the first to third anodes AE1, AE2, and AE3 in a plane. The opening portion IOP formed in the inorganic film IOF may not overlap each of the first to third anodes AE1, AE2, and AE3. However, the invention is not limited thereto, and the opening portion IOP may also overlap at least a portion of the first to third anodes AE1, AE2, and AE3.

[0234] The inner side surface of the inorganic film IOF defining the opening portion IOP may be formed to have an inclination. That is, the inner side surface of the inorganic film IOF may be an inclined surface. The opening portion IOP may have a shape in which the width increases from the bottom of the inorganic film IOF to the top of the inorganic film IOF. The inner side surface of the inorganic film IOF may be formed to form an acute angle with the top of the preliminary pixel defining film PDL-1 as a reference. However, the shape of the inner side surface of the inorganic film IOF is not limited thereto. Fig.11bUnlike the example shown in the figure, the inner side surface of the inorganic film 10F is formed to have a stepped shape, but it may be formed to form a right angle with respect to the upper surface of the preliminary pixel defining film PDL-1.

[0235] The situation that the inner side surface of the inorganic film IOF has an inclination means that the cross section formed by penetrating the inorganic film IOF configured on the preliminary pixel defining film PDL-1 has an inclination. In order to form the inclined surface, a halftone mask or a slit mask can be used in the process of patterning the inorganic film IOF, but the embodiment is not limited thereto. As the inner side surface of the inorganic film IOF is formed to have an inclination, when the first preliminary partition layer PL1 is formed, the first preliminary partition layer PL1 can easily cover the inner side surface of the opening portion IOP.

[0236] Afterwards, refer to Fig.11c According to an embodiment of the present invention, a display panel manufacturing method may include a step (S300) of forming a first preliminary partition layer PL1 on an inorganic film IOF. After the step of forming the inorganic film IOF, a step of forming a first preliminary partition layer PL1 including a transparent conductive material on the inorganic film IOF may be performed. The step of forming the first preliminary partition layer PL1 may be performed by a vapor deposition process of a transparent conductive material. In this embodiment, the transparent conductive material forming the first preliminary partition layer PL1 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), zinc oxide (ZnO) or indium oxide (In 2 O 3 The transparent conductive material forming the first preliminary partition wall layer PL1 may be indium tin oxide.

[0237] The first preliminary partition layer PL1 may be disposed on the inorganic film IOF and the preliminary pixel definition film PDL-1. The first preliminary partition layer PL1 may be formed to overlap at least the opening portion IOP. The first preliminary partition layer PL1 may be formed along the upper surface of the preliminary pixel definition film PDL-1 exposed through the upper surface of the inorganic film IOF, the inner side surface of the inorganic film IOF, and the opening portion IOP.

[0238] The first preliminary partition wall layer PL1 may have a groove shape that is recessed by a predetermined step with reference to the third direction DR3 in the portion overlapping with the opening IOP. The first groove portion HP1 having a shape recessed from a reference surface corresponding to the upper surface of the inorganic film IOF toward the base layer BL may be formed in the portion overlapping with the opening IOP.

[0239] Afterwards, refer to Fig.11dThe display panel manufacturing method according to an embodiment of the present invention may further include the step of forming an organic film OF on the first preliminary partition wall layer PL1. The organic film OF may be disposed in the first groove HP1 formed in the first preliminary partition wall layer PL1.

[0240] The step of forming the organic film OF may include the step of providing an organic substance in the first groove HP1 formed in the first preliminary partition wall layer PL1. The step of forming the organic film OF may also include the step of curing the organic substance provided in the first groove HP1. The organic film OF is arranged in the first groove HP1 so as to enhance the partition wall PW formed later (refer to Fig.11h )'s mechanical strength, as long as it does not affect the next-wall PW after curing (refer to Fig.11h ) can be used without restriction. For example, the organic material used to form the organic film OF can use acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, polyurethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin or polyethylene resin, etc. For example, the organic material used to form the organic film OF may include polyimide (P1) or polyethylene terephthalate (PET).

[0241] The organic film OF may be formed by heat curing or photocuring after providing an organic substance for forming the organic film OF in the first groove HP1. The organic substance provided in the first groove HP1 may be in a liquid form before curing. For example, the organic film OF may be formed by providing a liquid polymer resin in the first groove HP1 and ultraviolet curing the liquid polymer resin provided in the first groove HP1. The polymer resin for forming the organic film OF may be provided in the first groove HP1, and heat or light may be provided to the provided polymer resin to finally form the organic film OF. The polymer resin for forming the organic film OF may be provided in various ways. For example, the polymer resin may be provided by a method such as an inkjet printing method or a dispensing method.

[0242] The organic film OF may fill the first groove portion HP1. The organic film OF may fill the entire first groove portion HP1. However, not limited thereto, the organic film OF may also fill a portion of the first groove portion HP1.

[0243] Afterwards, refer to Fig.11e The display panel manufacturing method according to an embodiment of the present invention may include a step ( S400 ) of forming a second preliminary partition wall layer PL2 on the first preliminary partition wall layer PL1 to form a preliminary partition wall PPW.

[0244] The step of forming the second preliminary partition layer PL2 can be performed by a vapor deposition process of a conductive material. In one embodiment, the conductive material forming the second preliminary partition layer PL2 can be a metal material. For example, the conductive material forming the second preliminary partition layer PL2 can be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. For example, the metal forming the second preliminary partition layer PL2 can be titanium (Ti).

[0245] In one embodiment, the second preliminary partition wall layer PL2 may not include a metal substance. The second preliminary partition wall layer PL2 may be formed of a silicon compound. For example, the second preliminary partition wall layer PL2 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). For example, the second preliminary partition layer PL2 may include silicon oxide (SiO x ).

[0246] The second preliminary partition layer PL2 may be disposed on the first preliminary partition layer PL1 and the organic film OF. As the organic film OF is disposed in the first groove HP1 of the first preliminary partition layer PL1, the second preliminary partition layer PL2 may be formed to have a flat shape on the first preliminary partition layer PL1. However, not limited thereto, when the organic film OF is disposed only to fill a portion of the first groove HP1, the second preliminary partition layer PL2 may also have a shape that is recessed by a predetermined step based on the third direction DR3 in the portion overlapping the opening IOP.

[0247] In the step of forming the second preliminary partition wall layer PL2 , the preliminary partition wall PPW including the first preliminary partition wall layer PL1 , the organic film OF, and the second preliminary partition wall layer PL2 may be formed.

[0248] Afterwards, refer to Fig.11f According to an embodiment of the present invention, the display panel manufacturing method may include a step of forming a first photoresist pattern PR1 on the preliminary partition wall PPW (S500). The first photoresist pattern PR1 may be formed by patterning the preliminary photoresist layer using a photomask after forming a preliminary photoresist layer on the preliminary partition wall PPW. Through the patterning process, an optical opening portion OP-PR1 may be formed in the first photoresist pattern PR1. The optical opening portion OP-PR1 may overlap with the first to third anodes AE1, AE2, and AE3.

[0249] The first photoresist pattern PR1 may overlap with the opening OP in a plane. In a plane, the first photoresist pattern PR1 may overlap with the opening OP in its entirety. The plane area of ​​the first photoresist pattern PR1 may be greater than the plane area of ​​the opening IOP. For example, the plane area below the first photoresist pattern PR1 may be greater than the plane area of ​​the top end of the opening IOP. The bottom of the first photoresist pattern PR1 may overlap with a portion of the top of the inorganic film IOF in a plane. Thus, in the step of etching the inorganic film IOF, the first preliminary partition layer PL1, and the second preliminary partition layer PL2 described later, a portion of the first and second preliminary partition layers PL1 and PL2 disposed on the inorganic film IOF may remain after the etching process. A portion of the first and second preliminary partition layers PL1 and PL2 remaining after the etching process may form a tip in the partition PW formed later.

[0250] Afterwards, refer to Figure 11f to Figure 11h According to an embodiment of the present invention, the display panel manufacturing method may include etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 to form a partition PW defining the partition openings OP1-P, OP2-P and OP3-P (S500). The step of forming the partition (S500) may include etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 once and etching the inorganic film IOF twice.

[0251] Reference Fig.11f as well as Figure 11g The step of etching the inorganic film IOF, the first preliminary partition layer PL1, and the second preliminary partition layer PL2 once may include the step of etching the inorganic film IOF, the first preliminary partition layer PL1, and the second preliminary partition layer PL2 using the first photoresist pattern PR1 as a mask.

[0252] The step of etching the first preliminary partition layer PL1 and the second preliminary partition layer PL2 once may include using the first photoresist pattern PR1 as a mask and performing dry etching (dry etching) or wet etching (wet etching) on ​​the first preliminary partition layer PL1 and the second preliminary partition layer PL2. In one embodiment, the step of etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 once may include the step of dry etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2. Alternatively, the step of etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 once may be performed twice. For example, the step of etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 may include a dry etching step and a wet etching step performed in sequence.

[0253] In this embodiment, the etching process can be performed in an etching environment in which the etching selectivity between the inorganic film IOF, the first preliminary partition layer PL1, and the second preliminary partition layer PL2 is substantially the same. Figure 7b ) Part 2 (refer to Figure 7b )'s second outer side surface OS2 (refer to Figure 7b ) and the second partition layer L2 (refer to Figure 7b ) of the third outer side surface OS3 (refer to Figure 7b ) can be substantially aligned.

[0254] Afterwards, refer to Fig.11h After the step of etching the inorganic film IOF, the first preliminary partition layer PL1 and the second preliminary partition layer PL2 once, the step of etching the inorganic film IOF twice can be performed. The step of etching the inorganic film IOF twice can include using the first photoresist pattern PR1 as a mask and dry etching the inorganic film IOF to remove the inorganic film IOF. Dry etching can be implemented in a plasma etching device. Methods such as ion beam etching, inductively coupled plasma etching and reactive ion etching can be applied as plasma etching.

[0255] The two etching processes in this embodiment can be performed in an environment where the etching selectivity between the inorganic film IOF and the first and second preliminary partition layers PL1 and PL2 is large. The etching rate of the inorganic film IOF can be greater than the etching rate of each of the first and second preliminary partition layers PL1 and PL2. As a result, the inorganic film IOF is etched to a greater extent than each of the first preliminary partition layer PL1 and the second preliminary partition layer PL2, and thus, in the partition PW formed later, the first side surface portion S1 ( Figure 7b ) method to remove the inorganic film IOF.

[0256] In one embodiment, the inorganic film IOF may include a material different from the first and second preliminary partition layers PL1 and PL2. The inorganic film IOF may include a material having a high etching selectivity for the first and second preliminary partition layers PL1 and PL2. For example, the inorganic film IOF may include silicon nitride (SiN x ), the first preliminary partition wall layer PL1 includes indium tin oxide, and the second preliminary partition wall layer PL2 includes silicon oxide (SiO x ).

[0257] The step of etching the inorganic film IOF twice may include using the first photoresist pattern PR1 as a mask and dry etching the inorganic film IOF. The dry etching may be performed using the etching selectivity between the inorganic film IOF and the first and second preliminary partition layers PL1, PL2. The inorganic film IOF may be selectively removed using the etching selectivity between the inorganic film IOF and the first and second preliminary partition layers PL1, PL2. When the inorganic film IOF and the first preliminary partition layer PL1 or the second preliminary partition layer PL2 are formed of the same material, in the step of etching the inorganic film IOF twice, a portion of the first preliminary partition layer PL1 or the second preliminary partition layer PL2 may be removed together. However, as described in the utility model, as the inorganic film IOF is composed of a material different from the first and second preliminary partition layers PL1, PL2, the first and second preliminary partition layers PL1, PL2 may be kept from being etched by the etching selectivity, and the inorganic film IOF may be etched and removed.

[0258] The step of etching the inorganic film 10F twice may include the step of selectively removing the inorganic film 10F by using reactive radicals generated from plasma of the process gas. The process gas used in the dry etching process may be SiF 4 CF 4 , C 3 F 8 , C 2 F 6 , CHF 3 ,CClF 3, O 2 NF 3 and SF 6 In addition, the process gas may also include Ar or N which does not directly participate in the etching reaction in order to improve the etching reactivity or improve the etching uniformity. 2 And other inert gases.

[0259] If a plasma etching device is used to supply plasma of a process gas into a reaction chamber, the inorganic film IOF is etched by reactive radicals generated from the plasma, and the first preliminary partition wall layer PL1 and the second preliminary partition wall layer PL2 may not be etched. For example, when the inorganic film IOF includes silicon nitride (SiN x ), the first preliminary partition wall layer PL1 includes a transparent conductive oxide, and the second preliminary partition wall layer PL2 includes silicon oxide (SiO x ) when using silicon oxide (SiO x ) and transparent conductive oxides and silicon nitride (SiN x ) have different etching characteristics, so that the first and second preliminary partition walls PL1 and PL2 can be maintained and the silicon nitride (SiN x In order to improve the etching selectivity of the inorganic film IOF for the first and second preliminary partition walls PL1 and PL2, process conditions such as process gas, process pressure and process temperature may be appropriately adjusted.

[0260] Refer again Fig.11h In the second etching process, the inorganic film IOF is removed to form a partition wall PW including the first partition wall layer L1, the organic film OF, and the second partition wall layer L2. The first partition wall layer L1 may have a shape corresponding to the opening IOP.

[0261] Refer to Fig.11f as well as Fig.11h A portion of the first preliminary partition wall layer PL1 disposed on the preliminary pixel definition film PDL-1 exposed through the opening IOP may form a first portion P1 of the first partition wall layer L1 (see Figure 7b A portion of the first preliminary partition layer PL1 disposed on the inner side of the inorganic film IOF defining the opening IOP may form a first side surface portion S1 of the first partition layer L1 (see Figure 7b A portion of the first preliminary partition layer PL1 disposed on the inorganic film IOF may form a second portion P2 of the first partition layer L1 (see Figure 7b ).

[0262] In the second etching process, the inorganic film IOF can be removed to expose the first side surface portion S1 (see Figure 7b) of the first outer side surface OS1. In the second etching process, the first and second preliminary partition layers PL1 and PL2 may not be etched and may be retained, and the second portion P2 of the first partition layer L1 formed thereby (see Figure 7b ) and the third outer side surface OS3 of the second partition layer L2 may each have a shape that is convex toward the center direction of the anodes AE1, AE2, and AE3 compared to the first outer side surface OS1.

[0263] like Fig.11h As shown, after the step of etching the inorganic film IOF twice, a partition wall PW defining partition wall openings OP1-P, OP2-P, and OP3-P can be formed. The partition wall openings OP1-P, OP2-P, and OP3-P can include a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P. The first partition wall opening OP1-P can be formed to overlap with the first anode AE1, the second partition wall opening OP2-P can be formed to overlap with the second anode AE2, and the third partition wall opening OP3-P can be formed to overlap with the third anode AE3.

[0264] Each of the partition wall openings OP1-P, OP2-P, and OP3-P may include a first region A1 and a second region A2 sequentially arranged in the thickness direction, i.e., the third direction DR3. The first partition wall layer L1 may include a first side surface portion S1 (see FIG. 1 ) defining the first region A1 of the first to third partition wall openings OP1-P, OP2-P, and OP3-P. Figure 7b ) and a second outer side surface OS2 defining a first portion P1 of a portion of the second area A2. The second partition layer L2 may include a third outer side surface OS3 defining the remaining portion of the second area A2 of the first to third partition openings OP1-P, OP2-P, OP3-P.

[0265] Afterwards, refer to Fig.11i The display panel manufacturing method according to the present embodiment may include the steps of etching the pixel definition film PDL and etching the preliminary sacrificial patterns SP1-I, SP2-I, SP3-I (refer to Fig.11h ). The etching process of the pixel defining film PDL can be performed by dry etching, and the first photoresist pattern PR1 and the partition wall PW can be used as masks for etching. Light-emitting openings OP1-E, OP2-E, and OP3-E corresponding to the partition wall openings OP1-P, OP2-P, and OP3-P can be formed in the pixel defining film PDL. The light-emitting openings OP1-E, OP2-E, and OP3-E can include a first light-emitting opening OP1-E, a second light-emitting opening OP2-E, and a third light-emitting opening OP3-E.

[0266] The etching process of the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I can be performed by wet etching, and the first photoresist pattern PR1 and the partition wall PW can be used as masks for etching. The sacrificial patterns SP1, SP2, and SP3 formed by etching the preliminary sacrificial patterns SP1-I, SP2-I, and SP3-I can form sacrificial openings OP1-S, OP2-S, and OP3-S overlapping with the light-emitting openings OP1-E, OP2-E, and OP3-E.

[0267] The sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. A first sacrificial opening OP1-S overlapping with the first light-emitting opening OP1-E may be formed in the first sacrificial pattern SP1, a second sacrificial opening OP2-S overlapping with the second light-emitting opening OP2-E may be formed in the second sacrificial pattern SP2, and a third sacrificial opening OP3-S overlapping with the third light-emitting opening OP3-E may be formed in the third sacrificial pattern SP3. Through the first sacrificial opening OP1-S and the first light-emitting opening OP1-E, at least a portion of the first anode AE1 may be exposed from the first sacrificial pattern SP1 and the pixel defining film PDL. Through the second sacrificial opening OP2-S and the second light-emitting opening OP2-E, at least a portion of the second anode AE2 may be exposed from the second sacrificial pattern SP2 and the pixel defining film PDL. Through the third sacrificial opening OP3-S and the third light-emitting opening OP3-E, at least a portion of the third anode AE3 may be exposed from the third sacrificial pattern SP3 and the pixel defining film PDL.

[0268] The etching process of the sacrificial patterns SP1, SP2, SP3 can be performed in an environment where the etching selectivity between the sacrificial patterns SP1, SP2, SP3 and the anodes AE1, AE2, AE3 is large, thereby preventing the anodes AE1, AE2, AE3 from being etched together. That is, the sacrificial patterns SP1, SP2, SP3 having a higher etching rate than the anodes AE1, AE2, AE3 are arranged between the pixel defining film PDL and the anodes AE1, AE2, AE3, thereby preventing the anodes AE1, AE2, AE3 from being etched together and damaged during the etching process.

[0269] Afterwards, refer to Fig.11j According to the display panel manufacturing method of the present embodiment, the method may include removing the first photoresist pattern PR1 (refer to Fig.11i), after that, in the first partition wall opening OP1-P, a first light emitting pattern EP1 and a first cathode CE1 are sequentially formed on the first anode AE1 to form a first light emitting element ED1. The display panel manufacturing method according to an embodiment may further include the step of forming a first capping pattern CP1 on the first light emitting element ED1. The first capping pattern CP1 may be formed to be arranged in the first partition wall opening OP1-P.

[0270] In the step of forming the first light emitting element ED1, a first preliminary dummy layer DMP1-I may be formed on the partition wall PW. The first preliminary dummy layer DMP1-I may be formed by the same process as the first light emitting element ED1 and the first capping pattern CP1. The first preliminary dummy layer DMP1-I may be formed above the partition wall PW and in the second and third partition wall openings OP2-P and OP3-P.

[0271] The first preliminary dummy layer DMP1-I may include a 1-1st dummy layer D1-1I, a 2-1st dummy layer D2-1I, and a 3-1st dummy layer D3-1I. The 1-1st dummy layer D1-1I may be formed by the same process as the first light emitting pattern EP1, the 2-1st dummy layer D2-1I may be formed by the same process as the first cathode CE1, and the 3-1st dummy layer D3-1I may be formed by the same process as the first capping pattern CP1. The first preliminary dummy layer DMP1-I may be formed by separating the first light emitting element ED1 and the first capping pattern CP1 by forming a partition wall PW of a pointed portion.

[0272] Afterwards, refer to Figure 11k According to an embodiment of the present invention, the method for manufacturing a display panel may include, after forming the first light emitting element ED1, forming a preliminary lower encapsulation inorganic pattern LIL-I covering the first light emitting element ED1.

[0273] The preliminary lower encapsulation inorganic pattern LIL-I may cover the first light emitting element ED1 and the first preliminary dummy layer DMP1-I. A portion of the first preliminary dummy layer DMP1-I may be disposed in the first partition opening OP1-P. The first preliminary dummy layer DMP1-I may contact the first capping pattern CP1 and the 3-1st dummy layer D3-1I.

[0274] Reference Figure 11k as well as Figure 11lAccording to an embodiment, a display panel manufacturing method may include the step of patterning a preliminary lower encapsulation inorganic pattern LIL-I and a first preliminary dummy layer DMP1-I. The step of patterning the preliminary lower encapsulation inorganic pattern LIL-I and the first preliminary dummy layer DMP1-I may include the step of forming a second photoresist pattern PR2, the step of patterning the preliminary lower encapsulation inorganic pattern LIL-I so as to form a lower encapsulation inorganic pattern LIL, and the step of patterning the first preliminary dummy layer DMP1-I so as to form a dummy pattern D1.

[0275] In the step of forming the second photoresist pattern PR2, the second photoresist pattern PR2 may be formed by patterning the second preliminary photoresist layer using a photomask after forming the second preliminary photoresist layer. Through the patterning process, the second photoresist pattern PR2 is formed in a pattern form corresponding to the first light emitting opening portion OP1-E.

[0276] The step of patterning the preliminary lower package inorganic pattern LIL-I can remove the portion of the preliminary lower package inorganic pattern LIL-I that does not overlap with the second photoresist pattern PR2 by dry etching the preliminary lower package inorganic pattern LIL-I. That is, patterning can be performed to remove the portion of the preliminary lower package inorganic pattern LIL-I that does not overlap with the first anode AE1. A first lower package inorganic pattern LIL1 that overlaps with the first light-emitting opening OP1-E can be formed from the patterned preliminary lower package inorganic pattern LIL-I.

[0277] The step of patterning the first preliminary dummy layer DMP1-I may dry-etch the 1-1st dummy layer D1-1I, the 2-1st dummy layer D2-1I, and the 3-1st dummy layer D3-1I, thereby removing portions of the 1-1st dummy layer D1-1I, the 2-1st dummy layer D2-1I, and the 3-1st dummy layer D3-1I that do not overlap with the second photoresist pattern PR2. That is, patterning may be performed to remove portions of the 1-1st dummy layer D1-1I, the 2-1st dummy layer D2-1I, and the 3-1st dummy layer D3-1I that do not overlap with the first anode AE1. The 1-1, 2-1 and 3-1 dummy patterns D11, D21 and D31 overlapping the first light emitting opening OP1-E can be formed from the patterned 1-1, 2-1 and 3-1 dummy layers D1-1I, D2-1I and D3-1I. The 1-1, 2-1 and 3-1 dummy patterns D11, D21 and D31 can have a plane surrounding the corresponding light emitting area PXA (refer to Figure 6 ) of the closed line shape.

[0278] The step of patterning the first preliminary dummy layer DMP1-I may further include the step of wet etching the 1-1, 2-1 and 3-1 dummy layers D1-1I, D2-1I and D3-1I after the step of dry etching the 1-1, 2-1 and 3-1 dummy layers D1-1I, D2-1I and D3-1I.

[0279] In the step of patterning the first preliminary dummy layer DMP1-I, patterning may be performed to remove the portion of the first preliminary dummy layer DMP1-I that does not overlap with the first anode AE1. The first preliminary dummy layer DMP1-I formed in the second and third partition openings OP2-P and OP3-P may be removed by the patterning process. In addition, the first to third dummy layers D1-1I, D2-1I, and D3-1I formed on the partition PW that does not overlap with the first light-emitting opening OP1-E may also be removed by the patterning process. The first light-emitting pattern EP1 and the first cathode CE1 that overlap with the first light-emitting opening OP1-E may be formed from the patterned first preliminary dummy layer DMP1-I. After the patterning process, the first anode AE1, the first light-emitting pattern EP1, and the first cathode CE1 formed in the first light-emitting opening OP1-E and the first partition opening OP1-P may constitute the first light-emitting element ED1.

[0280] Afterwards, refer to Figure 11m According to an embodiment of the present invention, the display panel manufacturing method may include the steps of forming a second light emitting element ED2 and a third light emitting element ED3. Removing the second photoresist pattern PR2 ( Figure 11l ) After that, the second light emitting element ED2 and the third light emitting element ED3 may be formed in sequence. The process of forming the second light emitting element ED2 and the third light emitting element ED3 may be the same as that of forming the Figure 11j to Figure 11l The process of the first light emitting element ED1 described above is substantially the same. Figure 7a The display panel DP shows the first to third light emitting elements ED1, ED2, ED3, the first to third dummy patterns D1, D2, D3 and the first to third lower encapsulation inorganic patterns LIL1, LIL2, LIL3 of the plurality of light emitting regions PXA-R, PXA-G, PXA-B.

[0281] Although not shown, the step of forming the organic film OF may be omitted in the display panel manufacturing method according to one embodiment. The step of forming the organic film OF may be omitted in the display panel manufacturing method according to one embodiment and the step of forming the second preliminary partition wall layer PL2 may be performed immediately after the step of forming the first preliminary partition wall layer PL1. In this case, the shape of the partition wall formed in the step of forming the partition wall (S600) may be the same as that in Figure 9b The same as the next-door PW described in . Figure 11n According to an embodiment of the present invention, a display panel manufacturing method may include the steps of forming an encapsulation organic film OL and an upper encapsulation inorganic film UIL.

[0282] The above description is made with reference to the preferred embodiments of the utility model, but it is understood by those skilled in the art or those with general knowledge in the technical field that various modifications and changes can be made to the utility model without exceeding the concept of the utility model and the scope of the technical field recorded in the attached claims. Therefore, the technical scope of the utility model is not limited to the contents recorded in the detailed description of the specification, but should be determined by the claims.

Claims

1. A display panel, characterized in that: include: basal layer; A pixel defining film is disposed on the base layer and defines a light-emitting opening; A partition wall is disposed on the pixel defining film and defines a partition wall opening corresponding to the light emitting opening; as well as A light emitting element includes an anode, an intermediate layer, and a cathode in contact with the partition wall and arranged in the partition wall opening. The partition wall comprises: a first partition layer, disposed on the pixel defining film and formed of a transparent conductive oxide; and a second partition layer, disposed on the first partition layer and formed of a metal or a silicon compound, The first partition layer comprises: The first part is configured on the pixel defining film; a second portion, which is separated from the pixel defining film and has a step with the first portion; and The first side portion connects the first portion and the second portion.

2. The display panel according to claim 1, characterized in that: The partition opening comprises: The first area is configured with the light emitting element; and a second region having a smaller width than said first region, The first side surface of the first partition layer includes: a first outer side surface defining the first region, The second portion of the first partition layer includes a second outer side surface defining the second region.

3. The display panel according to claim 1, characterized in that: The cathode is in contact with the first side surface portion of the first partition layer.

4. The display panel according to claim 1, characterized in that: The partition wall further includes an organic film disposed between the first partition wall layer and the second partition wall layer.

5. The display panel according to claim 4, characterized in that: The first portion of the first partition layer is directly disposed on the pixel defining film.

6. The display panel according to claim 4, characterized in that: A partition space defined by the first portion, the first side portion, and a portion of the second partition layer is formed in the partition layer. The organic film is configured to fill the partitioned space.

7. The display panel according to claim 4, characterized in that: The second partition layer is disposed on the first portion and the organic film.

8. The display panel according to claim 1, characterized in that: An outer side surface of the second portion and an outer side surface of the second partition layer define an alignment surface.

9. The display panel according to claim 1, characterized in that: The second partition wall layer is directly disposed on the first partition wall layer.

10. An electronic device, characterized in that: include: A display device, comprising a display area and a non-display area adjacent to the display area, wherein the display area comprises a first area through which an optical signal passes and a second area adjacent to the first area; as well as an electronic module, which is disposed at the lower side of the display device and overlaps with the first area, and receives the optical signal, The display device comprises: basal layer; a partition wall disposed on the base layer and defining a partition wall opening; and A light emitting element includes an anode, an intermediate layer, and a cathode in contact with the partition wall and arranged in the partition wall opening. The partition wall comprises: A first partition layer is disposed on the base layer and is formed of a transparent conductive oxide; a second partition layer, disposed on the first partition layer and formed of a metal or a silicon compound; and The organic film is disposed between the first partition wall layer and the second partition wall layer.

Images