Server mainboard supporting PCIE4.0 various topologies

Abstract

The utility model discloses a server mainboard supporting various topologies of PCIE 4.0, belongs to the technical field of servers, and aims to solve the technical problem of how to improve the transmission rate and the transmission bandwidth of PCIE. A GPU module and a mainboard module are configured on the server mainboard, the GPU module and the mainboard module are connected through a Slimline high-speed cable in a laminated mode, two CPUs are configured on the mainboard module, each CPU at least provides one group of PCIE 4.0 * 16, and one CPU provides two groups of PCIE 4.0 * 16 buses.

Description

Technical Field

[0001] The utility model relates to the technical field of servers, in particular to a server mainboard supporting multiple topologies of PCIE4.0. Background Art

[0002] PCIe4.0 multiple topologies support the expansion of three commonly used GPU topology modes. It can expand the PCIe4.0 signal provided by the CPU to meet the Balance, Common, and Cascade modes, and meet the data collection and processing needs of different fields such as big data, cloud computing, and artificial intelligence. However, most of the PCIe topologies of products on the market are PCIe3.0 and PCIe2.0 transmission, with low transmission rates and bandwidth.

[0003] How to improve the transmission rate and transmission bandwidth of PCIe is a technical problem that needs to be solved. Summary of the invention

[0004] The technical task of the utility model is to address the above shortcomings and provide a server motherboard that supports multiple topologies of PCIE4.0 to solve the technical problem of how to improve the transmission rate and transmission bandwidth of PCIe.

[0005] The utility model discloses a server motherboard supporting multiple topologies of PCIE4.0. A GPU module and a motherboard module are configured on the server motherboard. The GPU module and the motherboard module are connected in a stacked manner through a Slimline high-speed cable. Two CPUs are configured on the motherboard module. Each CPU provides at least one group of PCIE4.0×16, and one of the CPUs provides two groups of PCIE4.0×16 buses.

[0006] Preferably, the CPU serving as the main CPU provides two sets of PCIE4.0×16 buses.

[0007] As a preferred embodiment, the two CPUs are respectively CPU0 and CPU1, and CPU0 and CPU1 each output a group of PCIE4.0×16 signals to connect to the GPU module;

[0008] The remaining 1 PCIE4.0×4, the remaining 2 PCIE4.0×8 or 1 PCIE4.0×16 of CPU0 and the 2 PCIE4.0×4, the remaining 2 PCIE4.0×8 or 1 PCIE4.0×16 of CPU1 are used for expansion of other PCIE devices.

[0009] As a preferred embodiment, the two CPUs are CPU0 and CPU1, and CPU0 outputs 2 groups of PCIE4.0×16 signals to connect to the GPU module;

[0010] The remaining 2 groups of PCIE4.0×4, the remaining 4 groups of PCIE4.0×8 or 2 groups of PCIE4.0×16 of CPU1 and the remaining 1 group of PCIE4.0×4 of CPU0 are used for expansion of other PCIE devices.

[0011] Preferably, the two CPUs are CPU0 and CPU1 respectively, and CPU0 or CPU1 outputs a set of PCIE4.0×16 signals to connect to the expansion board;

[0012] CPU0 and CPU1 have a total of 6 groups of PCIE4.0×8 signals and 3 groups of PCIE4.0×4 signals remaining for expansion of other PCIE devices.

[0013] The utility model provides a server motherboard supporting multiple topologies of PCIE4.0, which has the following advantages:

[0014] 1. The PCIe4.0 signal provided by the CPU can be expanded to meet the Balance, Common, and Cascade modes to meet the data collection and processing needs in different fields such as big data, cloud computing, and artificial intelligence;

[0015] 2. Both CPUs provide 2 sets of PCIE4.0×16 signals, which can meet the expansion of three common GPU topology modes: Balance, Common, and Cascade. Especially in the Common topology mode, the main CPU can be connected to the PCIE Switch on the GPU board through 2 sets of PCIE4.0×16 signals to realize the expansion of the GPU in Common mode, without occupying the PCIE4.0×8 signal of the main CPU. The main CPU can provide 2 sets of PCIE4.0×16 signals, which are directly connected to the GPU board, effectively improving data communication and processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] The utility model is further described below in conjunction with the accompanying drawings.

[0018] Figure 1 This is an architecture diagram of a server motherboard supporting multiple topologies of PCIE4.0 in Balance mode according to an embodiment of the present invention;

[0019] Figure 2This is an architecture diagram of a server motherboard supporting multiple topologies of PCIE4.0 in Commmon mode according to an embodiment of the present invention;

[0020] Figure 3 This is an architecture diagram of a server motherboard supporting multiple topologies of PCIE4.0 in Cascade mode according to an embodiment of the present invention;

[0021] Figure 1 In Balance mode, CPU0 and CPU1 each send out 1 set of PCIE4.0×16 signals to connect to the GPU board, CPU0 has 2 sets of PCIE4.0×8 (or 1 set of PCIE4.0×16) and 1 set of PCIE4.0×4 remaining, CPU1 has 2 sets of PCIE4.0×8 (or 1 set of PCIE4.0×16) and 2 sets of PCIE4.0×4 remaining, which are used for other PCIE device expansion;

[0022] Figure 2 In the medium Commmon mode, CPU0 outputs 2 sets of PCIE4.0×16 signals to connect to the GPU board, CPU1 has 4 sets of PCIE4.0×8 (or 2 sets of PCIE4.0×16), 2 sets of PCIE4.0×4, and CPU0 has 1 set of PCIE4.0×4 remaining, which is used for other PCIE device expansion;

[0023] Figure 3 In the Cascade mode, CPU0 or CPU1 outputs 1 set of PCIE4.0×16 signals to connect to the expansion board, and CPU0 and CPU1 have a total of 6 sets of PCIE4.0×8 signals and 3 sets of PCIE4.0×4 signals remaining for expansion of other PCIE devices. DETAILED DESCRIPTION

[0024] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention. In the absence of conflict, the embodiments of the present invention and the technical features in the embodiments may be combined with each other.

[0025] The embodiment of the utility model provides a server motherboard supporting multiple topologies of PCIE4.0, which is used to solve the technical problem of how to improve the transmission rate and transmission bandwidth of PCIe.

[0026] Embodiment 1:

[0027] The utility model discloses a server motherboard supporting multiple topologies of PCIE4.0. A GPU module and a motherboard module are configured on the server motherboard. The GPU module and the motherboard module are connected in a stacked manner through a Slimline high-speed cable. Two CPUs are configured on the motherboard module. Each CPU provides at least one group of PCIE4.0×16, and one of the CPUs provides two groups of PCIE4.0×16 buses.

[0028] In this embodiment, the CPU serving as the main CPU provides two sets of PCIE4.0×16 buses.

[0029] In this embodiment, the two CPUs are CPU0 and CPU1 respectively. CPU0 and CPU1 each output one group of PCIE4.0×16 signals to connect to the GPU module; the remaining one group of PCIE4.0×4, the remaining two groups of PCIE4.0×8 or one group of PCIE4.0×16 of CPU0 and the two groups of PCIE4.0×4, the remaining two groups of PCIE4.0×8 or one group of PCIE4.0×16 of CPU1 are used for expansion of other PCIE devices.

[0030] Table 1: GPU linear acceleration ratio of server motherboard in Balance mode

[0031]

[0032] The above connection method can realize the expansion of GPU in Balance mode. In this mode, GPU expansion maximizes CPU utilization and provides greater uplink bandwidth. It is suitable for HPC, VDI, and public cloud scenarios, but remote GPU P2P communication is limited by the UPI communication bottleneck between CPUs. It is suitable for cloud scenarios with high requirements for CPU core count and virtualization. The NUMA architecture ensures the performance balance of each GPU and maximizes the benefits of cloud vendors. At the same time, it meets the algorithm model in which the CPU and GPU participate in more tasks at the same time. For example, the linear acceleration ratio of inception3 GPU is the highest compared with other topologies.

[0033] The two CPUs are CPU0 and CPU1. CPU0 outputs 2 sets of PCIE4.0×16 signals to connect to the GPU module; the remaining 2 sets of PCIE4.0×4, the remaining 4 sets of PCIE4.0×8 or 2 sets of PCIE4.0×16 of CPU1 and the remaining 1 set of PCIE4.0×4 of CPU0 are used for expansion of other PCIE devices.

[0034] Table 2: GPU linear acceleration ratio of server motherboard in Commmon mode

[0035]

[0036] The above connection method can realize the expansion of GPU in Commmon mode. In this mode, GPU expansion has better GPU peer P2P communication performance. Remote GPU communication does not require UPI communication across CPUs, and the CPU-to-GPU throughput is high, with two PCIEx16s. It is suitable for P2P communication intensive training algorithm models with more CPU tasks, such as Resnet101 / 50 GPU linear acceleration ratio is the highest compared to other topologies.

[0037] The two CPUs are CPU0 and CPU1. CPU0 or CPU1 outputs one set of PCIE4.0×16 signals to connect to the expansion board. CPU0 and CPU1 have a total of 6 sets of PCIE4.0×8 signals and 3 sets of PCIE4.0×4 signals left for expansion of other PCIE devices.

[0038] Table 3: GPU linear acceleration ratio of server motherboard in Cascade mode

[0039]

[0040] The above connection method can realize the expansion of Cascade mode GPU. In this mode, the GPU expansion switch cascade provides the strongest GPU peer-to-peer P2P communication without crossing CPU nodes, but the CPU to GPU throughput is small, with only one PCIE x16. It is suitable for P2P parameter-intensive training algorithm models with less CPU participation, such as VGG-16, which has the highest GPU linear acceleration ratio compared to other topologies.

[0041] Because the CPU processor has no matching bridge chip, all IO expansion interfaces need to be expanded through the CPU's own PCIE or PCIESWITCH. In this embodiment, both CPUs provide 2 sets of PCIE4.0×16 signals, which can meet the expansion of three common GPU topology modes: Balance, Common, and Cascade. Especially in the Common topology mode, the main CPU can be connected to the PCIE Switch on the GPU board through 2 sets of PCIE4.0×16 signals to achieve the expansion of the GPU in Common mode. In this solution, the PCIE4.0×8 signal of the main CPU is not occupied. The main CPU can provide 2 sets of PCIE4.0×16 signals, which are directly connected to the GPU board, effectively improving data communication and processing efficiency.

[0042] The present invention has been shown and described in detail above through the accompanying drawings and preferred embodiments. However, the present invention is not limited to these disclosed embodiments. Based on the above multiple embodiments, those skilled in the art can know that the means in the above different embodiments can be combined to obtain more embodiments of the present invention, and these embodiments are also within the protection scope of the present invention.

Claims

1. A server motherboard supporting multiple topologies of PCIE4.0, characterized in that: The server motherboard is equipped with a GPU module and a motherboard module. The GPU module and the motherboard module are connected in a stacked manner through a Slimline high-speed cable. The motherboard module is equipped with two CPUs. Each CPU provides at least one set of PCIE4.0×16, and one of the CPUs provides two sets of PCIE4.0×16 buses.

2. A server motherboard supporting multiple topologies of PCIE4.0 according to claim 1, characterized in that: The CPU as the main CPU provides two sets of PCIE4.0×16 buses.

3. A server motherboard supporting multiple topologies of PCIE4.0 according to claim 1, characterized in that: The two CPUs are CPU0 and CPU1. CPU0 and CPU1 each output a set of PCIE4.0×16 signals to connect to the GPU module. The remaining 1 PCIE4.0×4, the remaining 2 PCIE4.0×8 or 1 PCIE4.0×16 of CPU0 and the 2 PCIE4.0×4, the remaining 2 PCIE4.0×8 or 1 PCIE4.0×16 of CPU1 are used for expansion of other PCIE devices.

4. The server motherboard supporting multiple topologies of PCIE 4.0 according to claim 1, characterized in that: The two CPUs are CPU0 and CPU1. CPU0 outputs 2 sets of PCIE4.0×16 signals to connect to the GPU module. The remaining 2 groups of PCIE4.0×4, the remaining 4 groups of PCIE4.0×8 or 2 groups of PCIE4.0×16 of CPU1 and the remaining 1 group of PCIE4.0×4 of CPU0 are used for expansion of other PCIE devices.

5. The server motherboard supporting multiple topologies of PCIE 4.0 according to claim 1, characterized in that: The two CPUs are CPU0 and CPU1 respectively. CPU0 or CPU1 outputs a set of PCIE4.0×16 signals to connect to the expansion board; CPU0 and CPU1 have a total of 6 groups of PCIE4.0×8 signals and 3 groups of PCIE4.0×4 signals remaining for expansion of other PCIE devices.

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