Server board card, monitoring system of server board card, server and monitoring system of server

Abstract

The embodiment of the utility model discloses a server board card, a monitoring system of the server board card, a server and a monitoring system of the server. The server board card comprises a board card element; the processor is used for acquiring parameters of the board card element, and when it is determined that the state of the board card element is abnormal based on the parameters, abnormal record data is generated based on the identifier of the server board card and the parameters; and the memory is used for storing the abnormal record data. The abnormal record data of the board card element can be conveniently obtained without reproducing the board card problem, so that the risk of disassembling and welding the server board card is avoided, and the normal operation of the server is also ensured. In a server scene of multiple board cards, based on the abnormal record data associated with the board card identifier, accurate distinguishing among the abnormal record data of the multiple board cards is realized.

Description

Technical Field

[0001] The utility model relates to the technical field of boards, and more specifically to a server board and a monitoring system thereof, a server and a monitoring system thereof. Background Art

[0002] A server board is usually a printed circuit board that can be inserted into a slot in a server to control the operation of hardware or software. For example, a server board may include a graphics accelerator card, an artificial intelligence (AI) computing card, a server motherboard, or an edge computing card, etc.

[0003] In the prior art, if a board works abnormally in a server, an engineer needs to remove the board from the server, connect the board to an oscilloscope, or connect the board to a Joint Test Action Group (JTAG) tool by welding, and then reproduce the board problem to obtain the register value of the chip by the JTAG tool, or use an oscilloscope to test power stability or signal stability.

[0004] However, due to the need to perform additional processing such as disassembly and welding, as well as considering changes in the system environment where the board is located, it is difficult to reproduce the board problem, resulting in difficulty in obtaining monitoring data when the board is abnormal. Utility Model Content

[0005] The utility model provides a server board and a monitoring system thereof, a server and a monitoring system thereof, which are helpful to conveniently obtain monitoring data when the board is abnormal.

[0006] The technical solution of the utility model implementation is as follows:

[0007] A server board, comprising:

[0008] Board components;

[0009] A processor, configured to obtain parameters of the board component, and when it is determined based on the parameters that the state of the board component is abnormal, generate abnormal record data based on the identifier of the server board and the parameters;

[0010] A memory is used to store the abnormal record data.

[0011] In one embodiment, the memory is used to provide the abnormal record data in response to a data read request issued by the data read-write device via a serial communication interface connected to the data read-write device; or

[0012] The memory is used to provide the abnormal record data in response to a data read request issued by the data read and write device via a system management bus (SMBus) connected to a baseboard management controller (BMC) and an Ethernet connection between the baseboard management controller and a data read and write device, wherein the baseboard management controller is included in the server where the server board is located.

[0013] In one embodiment, the processor is used to obtain a timestamp when the state of the board component is abnormal via an internal clock of the processor or an external clock of the processor, and include the timestamp in the abnormal record data.

[0014] A monitoring system for a server board, comprising:

[0015] The server board comprises: a board element; a processor for monitoring parameters of the board element, and when it is determined based on the parameters that the state of the board element is abnormal, generating abnormal record data based on the identifier of the server board and the parameters; and a memory for storing the abnormal record data;

[0016] A data reading and writing device is used to read the abnormal record data from the memory via a data connection with the memory.

[0017] A server, comprising:

[0018] N server boards, each of which has its own identifier, and the nth server board among the N server boards comprises:

[0019] Board components;

[0020] a processor, configured to monitor the parameters of the board component, and when it is determined based on the parameters that the state of the board component is abnormal, generate abnormal record data of the nth server board based on the identifier of the nth server board and the parameters;

[0021] A memory, used for storing the abnormal record data of the nth server board;

[0022] Where N is a positive integer of at least 2, and the value range of n is [1, N].

[0023] In one embodiment, the memory in the nth server board is used to provide the abnormal record data of the nth server board in response to a data read request issued by the data read-write device via a serial communication interface connected to the data read-write device; or

[0024] The memory in the nth server board is used to provide abnormal record data of the nth server board in response to a data read request issued by the data read and write device via a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and a data read and write device, wherein the baseboard management controller is included in the server.

[0025] In one embodiment, the processor in the nth server board is used to obtain a timestamp when the state of a board component in the nth server board is abnormal via the internal clock of the processor or the external clock of the processor, and include the timestamp in the abnormal record data of the nth server board.

[0026] In one embodiment, the board component includes at least one of the following:

[0027] Power module; power interface module; functional chip;

[0028] The parameters of the board component include at least one of the following:

[0029] Voltage value; current value; temperature value; register status value.

[0030] A server monitoring system, comprising:

[0031] A server, comprising N server boards, wherein the N server boards have respective identifiers, and the nth server board among the N server boards comprises:

[0032] Board components;

[0033] a processor, configured to monitor the parameters of the board component, and when it is determined based on the parameters that the state of the board component is abnormal, generate abnormal record data of the nth server board based on the identifier of the nth server board and the parameters;

[0034] A memory, used for storing the abnormal record data of the nth server board;

[0035] Where N is a positive integer of at least 2, and the value range of n is [1, N];

[0036] A data reading and writing device has a data connection with the N server boards, and is used to read the abnormal record data of the N server boards from the N memories of the N server boards via the data connection, and based on the identification of the t-th server board, extract the parameters of the board component in the t-th server board from the abnormal record data of the N server boards, where t is a set value.

[0037] In one embodiment, the processor in the nth server board is used to obtain a timestamp when the state of a board component in the nth server board is abnormal via the internal clock of the processor or the external clock of the processor, and include the timestamp in the abnormal record data of the nth server board.

[0038] It can be seen from the above technical solution that the server board of the embodiment of the utility model includes: a board component; a processor for obtaining the parameters of the board component, and when the state of the board component is determined to be abnormal based on the parameters, generating abnormal record data based on the identification and parameters of the server board; a memory for storing abnormal record data. It can be seen that the embodiment of the utility model realizes a server board with the ability to self-record abnormal data, and can easily obtain abnormal record data without reproducing the board abnormality, avoiding the risk of disassembling and welding the server board, and ensuring the normal operation of the server.

[0039] Moreover, in a server scenario with multiple boards, based on the abnormal record data associated with the board identification, accurate distinction between the abnormal record data of multiple boards is achieved, which facilitates accurate positioning of the board where the problem actually occurs.

[0040] In addition, the board of the embodiment of the utility model can also provide abnormal record data through local connection or remote connection. In the local connection mode, the engineer performing local debugging does not need to disassemble the server and reproduce the abnormality, which improves the convenience of operation. In the remote connection mode, the engineer performing remote debugging does not need to go to the server site, which improves the convenience of operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is an exemplary structural diagram of a server board according to an embodiment of the utility model.

[0042] Figure 2 It is an exemplary structural diagram of an AI computing board according to an embodiment of the present utility model.

[0043] Figure 3 It is a first exemplary structural diagram of a monitoring system for a server board according to an embodiment of the utility model.

[0044] Figure 4 It is a second exemplary structural diagram of the monitoring system of the server board according to the embodiment of the utility model.

[0045] Figure 5 It is an exemplary structural diagram of a server according to an embodiment of the present utility model.

[0046] Figure 6 It is a first exemplary structural diagram of a server monitoring system according to an embodiment of the present utility model.

[0047] Figure 7 It is a second exemplary structural diagram of the server monitoring system according to the implementation mode of the utility model. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the utility model clearer, the utility model is further described in detail below with reference to the accompanying drawings.

[0049] For the sake of brevity and intuitiveness in description, the scheme of the utility model is explained below by describing several representative implementations. A large number of details in the implementations are only used to help understand the scheme of the utility model. However, it is obvious that the technical scheme of the utility model may not be limited to these details when implemented. In order to avoid unnecessarily blurring the scheme of the utility model, some implementations are not described in detail, but only a framework is given. In the following, "including" means "including but not limited to", and "according to..." means "at least according to..., but not limited to only according to...". Due to the language habits of Chinese, when the number of a component is not specifically specified below, it means that the component can be one or more, or can be understood as at least one.

[0050] The processing mechanism for server card anomalies has always been a major problem that has troubled engineers. The current common practices include: if a card anomalies occur in a server, first remove the card from the server, then solder the card with a JTAG tool or connect it to an oscilloscope, then reproduce the anomaly, and use the JTAG tool to obtain the chip register value at the time of the anomaly, or use an oscilloscope to test the power supply stability or signal stability, and then perform debugging and other work.

[0051] The applicant analyzed the above process of the prior art and found that there are at least the following disadvantages:

[0052] (1) Maintenance personnel need to shut down the server on site, which affects the normal use of the server.

[0053] (2) Maintenance personnel need to perform physical operations such as disassembly and welding on the board, which poses a risk of damaging the board.

[0054] (3) It is difficult to reproduce anomalies. For example, if an anomaly is reproduced on a server, it will delay the normal use of the server; if an anomaly is reproduced on other platforms, it may not be possible to reproduce the anomaly due to environmental changes and other factors.

[0055] (4) When a server has multiple boards, it is difficult to accurately locate the board that actually has a problem. For example, when anomalies occur randomly on certain boards in the server, all boards need to be soldered with JTAG tools or the boards (such as the board power supply or the suspected abnormal signal source) need to be connected to an oscilloscope, which further increases the difficulty of solving the problem.

[0056] In the embodiment of the utility model, when an abnormality occurs in a board, it is not devoted to reproducing the abnormality as in the prior art, but based on the collaborative processing between the processor and the memory arranged in the board, the abnormal record data is stored automatically, thereby realizing a server board with the ability to self-record abnormal data. The board can provide abnormal record data to the outside of the board through local connection or remote connection. Therefore, the abnormal record data can be easily obtained without reproducing the board problem, avoiding the risk of disassembling and welding the server board, and ensuring the normal operation of the server. In addition, for a server scenario containing multiple boards, based on the abnormal record data associated with each board identifier, accurate distinction between the abnormal record data of multiple boards is achieved.

[0057] The above disclosure details the technical defects existing in the prior art, the causes of the technical defects, and the thinking and analysis process of overcoming the technical defects. In fact, the cognition of the above technical defects is not common knowledge in the field, but a novel discovery made by the applicant in research. In addition, the cause tracing of the technical defects and the thinking and analysis process of overcoming the technical defects are also the gradual analysis results of the applicant in the actual research process, and are not common knowledge in the field.

[0058] Figure 1 FIG. 1 is an exemplary structural diagram of a server card according to an embodiment of the present utility model. Figure 1 In the embodiment, the server board 100 includes: a board element 101; a processor 102, which is used to obtain parameters of the board element 101, and when it is determined based on the parameters that the state of the board element 101 is abnormal, generates abnormal record data based on the identification and parameters of the server board 100; and a memory 103, which is used to store the abnormal record data.

[0059] In the embodiment of the present utility model, the server board 100 can be implemented as a sound card, a graphics accelerator card, an AI computing card, a server motherboard or an edge computing card, etc. Moreover, the server board 100 can be implemented as a board based on Field Programmable Gate Array (FPGA) technology or a board based on Application Specific Integrated Circuit (ASIC) technology. In addition, the server including the server board 100 can be implemented as a network server with networking capability, and can also be implemented as a local terminal device (such as a computer) without networking capability or an edge computing device arranged at the edge of the network, and the embodiment of the present utility model is not limited to this.

[0060] The board element 101 can be any element that needs to be detected in the server board 100. For example, the board element 101 can be implemented as: a power module, a power interface module and a functional chip, etc. The power module is used to directly provide power to the server board 100. The power interface module can be implemented as a power interface for accessing power from outside the server board 100. The functional chip is a chip that performs specific operations in the server board 100, such as an AI computing chip, etc. The number of board elements 101 can be one or more. When the number of board elements 101 is multiple, after the processor 102 obtains the parameters of each board element 101, the corresponding board element identifier can be added to the parameters of each board element 101, thereby distinguishing the parameters of each board element.

[0061] The processor 102 may include a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), or a microcontroller unit (MCU), etc.

[0062] In one embodiment, the board element 101 is implemented as a power module (e.g., a battery) arranged in the server board 100 for providing power to the server board 100. The processor 102 reads the parameters of the power module (e.g., voltage value, current value, or temperature value, etc.) regularly or in real time. The processor 102 compares the read parameters with the pre-set normal interval of the parameters. When the read parameters are in the normal interval of the parameters, the processor 102 determines that the power module is normal; when the read parameters are not in the normal interval of the parameters, the processor 102 determines that the power module is abnormal. When the processor 102 determines that the state of the power module is abnormal, the processor 102 generates abnormal record data based on the identifier (usually a unique identifier) ​​of the server board 100 and the read parameters. For example, the processor 102 associates the identifier of the board 100 with the parameters to generate abnormal record data. Specific association methods may include: appending the identification of the board 100 to the file name of the parameter file used to save the parameters; appending the identification of the board 100 to the file header of the parameter file used to save the parameters; appending the identification of the board 100 to the file tail of the parameter file used to save the parameters; and so on.

[0063] In one embodiment, the board element 101 is implemented as a chip arranged in the server board 100 for performing specific operations, such as an AI computing chip. The processor 102 can read the state value of each register in the AI ​​computing chip. The processor 102 compares the state value of each register with the normal state value of the corresponding register set in advance. When the state value read from the register is consistent with the normal state value, the processor 102 determines that the state of the register is normal; when the state value read from the register is inconsistent with the normal state value, the processor 102 determines that the state of the register is abnormal. When the processor 102 determines that the state of the register is abnormal, the processor 102 generates abnormal record data based on the identifier of the server board 100 (usually a unique identifier) ​​and the state value of the register (the identifier of the register can also be added). For example, the processor 102 can associate the identifier of the board 100 with the state value of the register to generate abnormal record data. Specific association methods may include: appending the identification of the board 100 to the file name of the status value file used to save the status value; appending the identification of the board 100 to the file header of the status value file used to save the status value; appending the identification of the board 100 to the file tail of the status value file used to save the status value; and so on.

[0064] In one embodiment, the processor 102 is used to obtain a timestamp when the state of the board component 101 is abnormal via the internal clock of the processor 102 or the external clock of the processor 102, and include the timestamp in the abnormal record data. For example, when the processor 102 determines that the board component 101 is abnormal, it reads its own clock or the external clock to determine the current timestamp, and then adds the timestamp to the abnormal record data. Based on the abnormal record data with the timestamp added, the specific time when the abnormality occurs can be clearly determined, which is convenient for subsequent debugging.

[0065] Preferably, the memory 103 for storing abnormal record data can be implemented as a non-volatile memory. For example, the memory 103 can be implemented as a read-only memory (ROM), a programmable read-only memory (PROM), an electrically alterable read-only memory (EAROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM) or a flash memory, etc.

[0066] In one embodiment, the memory 103 is used to read and write data via a data read and write device ( Figure 1 A serial communication interface (not shown) is used to respond to a data read request issued by a data read-write device and provide abnormal record data to the data read-write device. For example, the serial communication interface can be implemented as an internal integrated circuit (Inter-Integrated Circuit, I2C) interface, etc. Therefore, the memory 103 can receive a data read request from a local data read-write device via the serial communication interface. The memory 103 can also respond to the data read request and provide abnormal record data to a local data read-write device via the serial communication interface. The local data read-write device can display abnormal data and perform debugging and other tasks using the abnormal record data. In this local connection mode, engineers performing debugging do not need to disassemble the server and reproduce the abnormality, which improves the convenience of operation.

[0067] In one embodiment, the memory 103 is used to provide abnormal record data in response to a data read request issued by the data read-write device via a system management bus connected to the BMC and an Ethernet connection between the BMC and the data read-write device, wherein the BMC is included in the server where the server board 100 is located. Therefore, the memory 103 can receive a data read request issued by a remotely located data read-write device via the BMC and the Ethernet connection, and provide abnormal record data to the data read-write device in a remote connection mode in response to the data read request, so that the data read-write device can further remotely display the abnormal data and perform remote debugging and other tasks using the abnormal record data. In the remote connection mode, the engineer performing remote debugging does not need to arrive at the server site, which improves the convenience of operation.

[0068] The following uses an AI computing board as an example to illustrate the implementation of the present invention. Figure 2 It is an exemplary structural diagram of an AI computing board according to an embodiment of the present utility model.

[0069] exist Figure 2 In the embodiment, the AI ​​computing board 200 includes: a power module 201; an AI computing chip 204; a processor 202; and a memory 203. The power module 201 and the AI ​​computing chip 204 are both board components. The processor 202 obtains parameters representing the electrical properties of the power module 201 (for example, voltage value, current value, or power value, etc.) and the register state value in the AI ​​computing chip 204.

[0070] The processor 202 compares the parameters read from the power module 201 with the pre-set normal interval of the parameters. When the read parameters are within the normal interval of the parameters, the processor 202 determines that the state of the power module 201 is normal; when the read parameters are not within the normal interval of the parameters, the processor 202 determines that the state of the power module 201 is abnormal. When the processor 202 determines that the state of the power module 201 is abnormal, the processor 202 generates abnormal record data based on the identifier (usually a unique identifier) ​​of the server board 200 and the parameters of the power module 201. The abnormal record data is saved in the memory 203 in a file format. For example, assuming that the identifier of the board 200 is ABC, the processor 202 sets the file name of the file used to save the parameters of the power module 201 to: ABC-Power, where the field "ABC" is used to characterize the board 200; the field "Power" is used to characterize the power module 201. In the file ABC-Power, the parameters of the power module 201 can be specifically saved in the form of a table or the like.

[0071] The processor 202 can read the state value of each register in the AI ​​computing chip 204. The processor 202 compares the state value of each register with the normal state value of the corresponding register that is preset. When the state value read from the register is consistent with the normal state value, the processor 202 determines that the state of the register is normal; when the state value read from the register is inconsistent with the normal state value, the processor 202 determines that the state of the register is abnormal. When the processor 202 determines that the state of the register is abnormal, the processor 102 generates abnormal record data based on the identifier of the server board 100 (usually a unique identifier) ​​and the state value of the register (the identifier of the register can also be added). For example, assuming that the identifier of the board 200 is ABC, the processor 202 sets the file name of the file used to save the register value of the AI ​​computing chip 204 to: ABC-AIChip, where the field "ABC" is used to characterize the board 200; the field "AIChip" is used to characterize the AI ​​computing chip 204. In the file ABC-AIChip, the register value in the AI ​​computing chip 204 can be specifically saved in the form of a table or the like.

[0072] exist Figure 2 In the present invention, an AI computing board is taken as an example to illustrate the implementation mode of the present invention. Those skilled in the art can realize that this description is only exemplary and is not used to limit the protection scope of the implementation mode of the present invention.

[0073] The embodiment of the utility model also proposes a monitoring system for a server board. The monitoring system for the server board includes: a server board, including: a board component; a processor, used to monitor the parameters of the board component, and when the state of the board component is determined to be abnormal based on the parameters, abnormal record data is generated based on the identification and parameters of the server board; a memory, used to store the abnormal record data; a data read-write device, used to read the abnormal record data from the memory via a data connection with the memory. In one embodiment, the memory is used to provide abnormal record data in response to a data read request issued by the data read-write device via a serial communication interface connected to the data read-write device. In one embodiment, the memory is used to provide abnormal record data in response to a data read request issued by the data read-write device via a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and the data read-write device, wherein the baseboard management controller is included in the server where the server board is located.

[0074] Figure 3 It is a first exemplary structural diagram of a monitoring system for a server board according to an embodiment of the utility model. Figure 3 A schematic diagram showing a server board providing abnormal record data via a local connection. Figure 3 The monitoring system of the server board in the system includes: Figure 1 The server board 100 and the data reading and writing device 300 shown in the figure, wherein the memory 103 in the server board 100 is wiredly connected to the data reading and writing device 300 located locally on the server board 100 via a serial communication interface (e.g., an I2C interface). The data reading and writing device 300 can access the memory 103 to read the abnormal record data of the server board 100.

[0075] Optionally, in another local connection form: the local data reading and writing device 300 is connected to the processor 102 located in the server board 100. The data reading and writing device 300 accesses the memory 103 via the processor 102 to read the abnormal record data of the server board 100.

[0076] In the local connection mode, engineers performing local debugging do not need to dismantle the server and reproduce abnormalities, which improves operational convenience.

[0077] Figure 4 It is a second exemplary structural diagram of the monitoring system of the server board according to the embodiment of the utility model. Figure 4 A schematic diagram showing a server board providing abnormal record data via a remote connection. Figure 4 The monitoring system of the server board in the system includes: Figure 1 The server board 100 and the data read-write device 300 shown in the figure, wherein the memory 103 in the server board 100 is connected to the BMC 104 located in the server where the server board 100 is located via the system management bus. The BMC 104 is connected to the remotely located data read-write device 300 via Ethernet. The data read-write device 300 can remotely access the memory 103 to read the abnormal record data of the server board 100. In the remote connection mode, the engineer performing remote debugging does not need to arrive at the server site, which improves the convenience of operation.

[0078] The embodiment of the utility model also proposes a server with multiple server boards, wherein each server board has the ability to self-record abnormal data.

[0079] Figure 5 FIG. 1 is an exemplary structural diagram of a server according to an embodiment of the present utility model. Figure 5 In the embodiment, the server 500 includes: N server boards, each of the N server boards has its own identifier, and each server board has the following identifier: Figure 1The structure shown. Exemplarily, the nth server board 100 among the N server boards includes: a board element 101; a processor 102, which is used to monitor the parameters of the board element 101, and when the state of the board element 101 is determined to be abnormal based on the parameters, the abnormal record data of the nth server board is generated based on the identifier 100 and the parameters of the nth server board; a memory 103, which is used to store the abnormal record data of the nth server board; wherein N is a positive integer of at least 2, and the value range of n is [1, N]. It can be seen that each of the N server boards can generate its own abnormal record data. Moreover, the abnormal record data of the N server boards can be distinguished based on their respective server board identifiers. Therefore, when an abnormality occurs randomly on one or some server boards in the server 500, the server board where the problem actually occurs can be accurately located.

[0080] In one embodiment, the memory 103 in the nth server board is used to provide the abnormal record data of the nth server board in response to a data read request issued by the data read and write device via a serial communication interface connected to the data read and write device. In one embodiment, the memory 103 in the nth server board is used to provide the abnormal record data of the nth server board in response to a data read request issued by the data read and write device via a system management bus connected to the BMC and an Ethernet connection between the BMC and the data read and write device, wherein the BMC is included in the server 500.

[0081] In one embodiment, the processor 102 in the nth server board is used to obtain the timestamp when the state of the board component in the nth server board is abnormal through the internal clock of the processor 102 or the external clock of the processor 102, and include the timestamp in the abnormal record data of the nth server board. Therefore, based on the abnormal record data with the timestamp attached, the specific time when the abnormality occurs can be clearly determined, which is convenient for subsequent debugging work.

[0082] In one embodiment, the board element includes at least one of the following: a power module; a power interface module; a functional chip, etc.; the parameters of the board element include at least one of the following: a voltage value; a current value; a temperature value; a status value of a register, etc.

[0083] Figure 6 It is a first exemplary structural diagram of a server monitoring system according to an embodiment of the present utility model. Figure 6 A schematic diagram showing a server including multiple server boards providing abnormal record data via a local connection. Figure 6 The monitoring system of the server in the embodiment includes: a server 500, including N such as Figure 1The server board 100 shown; the data reading and writing device 300, wherein N is a positive integer of at least 2, and the value range of n is [1, N]. The memory 103 in the nth server board 100 is wired to the data reading and writing device 300 located locally on the site of the server 500 via a serial communication interface (e.g., an I2C interface). The data reading and writing device 300 can access the memory in each server board in the server 500 to read the abnormal record data of each server board. In the local connection mode, engineers performing local debugging do not need to disassemble the server and reproduce the abnormality, which improves the convenience of operation. Moreover, based on the abnormal record data associated with the board identification, accurate distinction between the abnormal record data of multiple boards is achieved.

[0084] Figure 7 It is a second exemplary structural diagram of the server monitoring system according to the implementation mode of the utility model. Figure 7 A schematic diagram showing a server including multiple server boards providing abnormal record data via a remote connection. Figure 7 The monitoring system of the server in the embodiment includes: a server 500, including N such as Figure 1 The server board 100 shown; the data reading and writing device 300, wherein N is a positive integer of at least 2, and the value range of n is [1, N], wherein the memory 103 in the nth server board 100 is connected to the BMC 104 in the server 500 via the system management bus. The BMC 104 is connected to the remotely located data reading and writing device 300 via Ethernet. The data reading and writing device 300 can access the memory in each server board in the server 500 to read the abnormal record data of each server board in the server 500. For example: when it is desired to read the abnormal record data of the tth server board, the parameters of the board element in the tth server board can be extracted from the abnormal record data of the N server boards based on the identification of the tth server board. In the remote connection mode, the engineer performing remote debugging does not need to arrive at the server site, which improves the convenience of operation. Moreover, based on the abnormal record data associated with the board identification, accurate distinction between the abnormal record data of multiple boards is achieved.

[0085] It should be noted that not all modules in the above structural diagrams are necessary, and some steps or modules in the above description can be ignored according to actual needs. The execution order of each step is not fixed and can be adjusted as needed. The division of each module is only for the convenience of describing the functional division adopted. In actual implementation, a module can be implemented by multiple modules, and the functions of multiple modules can also be implemented by the same module. These modules can be located in the same device or in different devices.

[0086] The hardware modules in each embodiment can be implemented mechanically or electronically. For example, a hardware module may include a specially designed permanent circuit or logic device (such as a dedicated processor, such as an FPGA or ASIC) for performing a specific operation. The hardware module may also include a programmable logic device or circuit (such as a general-purpose processor or other programmable processor) temporarily configured by software to perform a specific operation. As for whether to implement the hardware module mechanically, or using a dedicated permanent circuit, or using a temporarily configured circuit (such as configured by software), it can be decided based on cost and time considerations.

[0087] In this article, "schematic" means "serving as an example, an example or an illustration", and any diagram or implementation method described as "schematic" in this article should not be interpreted as a more preferred or more advantageous technical solution. In order to make the drawings concise, only the parts related to the utility model are schematically shown in each figure, and do not represent the actual structure of the product. In addition, in order to make the drawings concise and easy to understand, in some figures, only one of the parts with the same structure or function is schematically drawn, or only one of them is marked. In this article, "one" does not mean that the number of the relevant parts of the utility model is limited to "only one", and "one" does not mean that the number of the relevant parts of the utility model is "more than one". In this article, "upper", "lower", "front", "back", "left", "right", "inside", "outside", etc. are only used to indicate the relative position relationship between the relevant parts, rather than to limit the absolute position of these relevant parts.

[0088] The above is only a preferred embodiment of the utility model, and is not intended to limit the protection scope of the utility model. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the utility model shall be included in the protection scope of the utility model.

Claims

1. A server card, characterized in that: include: Board components; A processor, configured to obtain parameters of the board component, and when it is determined based on the parameters that the state of the board component is abnormal, generate abnormal record data based on the identifier of the server board and the parameters; A memory, used for storing the abnormal record data; The memory is used to provide the abnormal record data to the data reading and writing device in response to a data reading request issued by the data reading and writing device via a serial communication interface connected to the data reading and writing device; or The memory is used to provide the abnormal record data to the data reading and writing device in response to a data reading request issued by the data reading and writing device via a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and the data reading and writing device, wherein the baseboard management controller is included in the server where the server board is located.

2. The server board according to claim 1, characterized in that: The processor is used to obtain a timestamp when the state of the board component is abnormal via an internal clock of the processor or an external clock of the processor, and include the timestamp in the abnormal record data.

3. A server board monitoring system, characterized in that: include: The server board comprises: a board element; a processor for monitoring parameters of the board element, and when it is determined based on the parameters that the state of the board element is abnormal, generating abnormal record data based on the identifier of the server board and the parameters; and a memory for storing the abnormal record data; A data reading and writing device, used for reading the abnormal record data from the memory via a data connection with the memory; The memory is used to provide the abnormal record data to the data reading and writing device in response to a data reading request issued by the data reading and writing device via a serial communication interface connected to the data reading and writing device; or The memory is used to provide the abnormal record data to the data reading and writing device in response to a data reading request issued by the data reading and writing device via a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and the data reading and writing device, wherein the baseboard management controller is included in the server where the server board is located.

4. A server, characterized in that: include: N server boards, each of which has its own identifier, and the nth server board among the N server boards comprises: Board components; A processor is used to monitor the parameters of the board component, and when it is determined based on the parameters that the state of the board component is abnormal, based on the identifier of the nth server board and the parameters Generate abnormal record data of the nth server board; A memory, used for storing the abnormal record data of the nth server board; Where N is a positive integer of at least 2, and the value range of n is [1, N]; The memory in the nth server board is used to provide the abnormal record data of the nth server board to the data reading and writing device in response to a data reading request issued by the data reading and writing device via a serial communication interface connected to the data reading and writing device; or The memory in the nth server board is used to provide the data reading and writing device with abnormal record data of the nth server board via a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and a data reading and writing device, in response to a data reading request issued by the data reading and writing device, wherein the baseboard management controller is included in the server.

5. The server according to claim 4, characterized in that: The processor in the nth server board is used to obtain a timestamp when the state of a board component in the nth server board is abnormal via the internal clock of the processor or the external clock of the processor, and include the timestamp in the abnormal record data of the nth server board.

6. The server according to any one of claims 4-5, characterized in that: The board component includes at least one of the following: Power module; power interface module; functional chip; The parameters of the board component include at least one of the following: Voltage value; current value; temperature value; register status value.

7. A server monitoring system, characterized in that: include: A server, comprising N server boards, wherein the N server boards have respective identifiers, and the nth server board among the N server boards comprises: Board components; A processor is used to monitor the parameters of the board components, and when the parameters are determined based on the When determining that the state of the board component is abnormal, generating abnormal record data of the nth server board based on the identifier of the nth server board and the parameters; A memory, used for storing the abnormal record data of the nth server board; Where N is a positive integer of at least 2, and the value range of n is [1, N]; A data reading and writing device has a data connection with the N server boards, and is used to read the abnormal record data of the N server boards from the N memories of the N server boards via the data connection, and extract the parameters of the board component in the t-th server board from the abnormal record data of the N server boards based on the identification of the t-th server board, wherein t is a set value; the data connection includes a serial communication interface or a system management bus connected to a baseboard management controller and an Ethernet connection between the baseboard management controller and the data reading and writing device.

8. The server monitoring system according to claim 7, characterized in that: The processor in the nth server board is used to obtain a timestamp when the state of a board component in the nth server board is abnormal via the internal clock of the processor or the external clock of the processor, and include the timestamp in the abnormal record data of the nth server board.

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