Current sharing circuit and current sharing system based on parallel connection of uninterruptible power supplies

Abstract

The utility model discloses a current sharing circuit and a current sharing system based on parallel connection of uninterruptible power supplies, and belongs to the technical field of power supplies, the current sharing circuit comprises a plurality of sampling circuits and a current sharing circuit, each sampling circuit is respectively connected with a power circuit and an on-site digital signal processor in each uninterruptible power supply, and the current sharing circuit is connected with the on-site digital signal processor. The average current circuit is respectively connected with each sampling circuit and the local digital signal processor in each uninterruptible power supply; the sampling circuit is used for collecting a current signal of a power circuit in the uninterruptible power supply connected with the sampling circuit, converting the current signal into a voltage signal and sending the voltage signal to the average current circuit and the local digital signal processor in the uninterruptible power supply connected with the sampling circuit; the average current circuit is used for outputting an average voltage signal according to the voltage signal sent by each sampling circuit and respectively sending the average voltage signal to each local digital signal processor; according to the utility model, the current-sharing operation of each uninterruptible power supply can be realized, and the stability and robustness of the operation are ensured.

Description

Technical Field

[0001] The utility model belongs to the technical field of power supply, and particularly relates to a current sharing circuit and a current sharing system based on uninterruptible power supplies in parallel. Background Art

[0002] The inverter converts DC power (battery, storage bottle) into AC power (usually 220V, 50Hz sine wave). It consists of an inverter bridge, control logic and filter circuit. The inverter in the power supply system has become an indispensable part of the power supply. The parallel operation of the inverter can achieve power supply redundancy, that is, when the capacity of the power supply is greater than a certain value required by the load, when a part of the power supply fails, the power supply is still uninterrupted, which greatly improves the capacity and reliability of the power supply system.

[0003] The rapid development and widespread application of signal technology have put higher and higher requirements on the quality and reliability of its power supply. The realization of high-reliability and large-capacity power supply by connecting multiple circuits in parallel is considered to be one of the important directions for the development of power electronics technology today. Taking the construction of communication secondary power supply as an example, from the initial single circuit power supply to 1+1 redundancy, the N+1 method has now been widely recognized. The circuitized parallel operation of uninterruptible power supply is an inevitable trend, which can improve the capacity, reliability and economy of uninterruptible power supply. However, solving the stability and robustness of the current-sharing operation of multiple inverters in parallel has become a current difficulty. Summary of the invention

[0004] In order to solve the above problems, the utility model proposes a current sharing circuit and a current sharing system based on parallel connection of uninterruptible power supplies, which can realize current sharing operation of each uninterruptible power supply and ensure the stability and robustness of the operation of the uninterruptible power supply.

[0005] In the first aspect, the utility model proposes a current-sharing circuit based on parallel connection of uninterruptible power supplies, comprising a plurality of sampling circuits and an average current circuit, each of the sampling circuits being respectively connected to a power circuit and an on-site digital signal processor in each uninterruptible power supply, and the average current circuit being respectively connected to each of the sampling circuits and an on-site digital signal processor in each uninterruptible power supply;

[0006] The sampling circuit is used to collect the current signal of the power circuit in the connected uninterruptible power supply, and convert the current signal into a voltage signal and send it to the average current circuit and the local digital signal processor in the connected uninterruptible power supply;

[0007] The average current circuit is used to output an average voltage signal according to the voltage signal sent by each sampling circuit, and send the average voltage signal to each of the local digital signal processors respectively.

[0008] In an optional embodiment, the average current circuit includes a plurality of effective value circuits and an average voltage circuit; each of the effective value circuits is respectively connected to a corresponding sampling circuit, each of the effective value circuits is also respectively connected to an average voltage circuit, and the average voltage circuit is respectively connected to the local digital signal processor in each of the uninterruptible power supplies;

[0009] The effective value circuit is used to output an effective value signal corresponding to the voltage signal according to the voltage signal sent by the corresponding sampling circuit;

[0010] The average voltage circuit is used to output an average voltage signal according to the effective value signal sent by each effective value circuit, and send the average voltage signal to an on-site digital signal processor.

[0011] In an optional embodiment, each of the effective value circuits includes a peak circuit and a proportional amplifier circuit connected in series in sequence; the peak circuit is connected to a sampling circuit in a corresponding uninterruptible power supply, and the proportional amplifier circuit is connected to the average voltage circuit;

[0012] The peak circuit is used to determine a peak signal corresponding to a voltage signal sent by a sampling circuit in a corresponding uninterruptible power supply, and send the peak signal to a proportional amplification circuit;

[0013] The proportional amplifier circuit is used to determine the effective value signal corresponding to the peak signal and send the effective value signal to the average voltage circuit.

[0014] In an optional embodiment, the peak circuit includes a first resistor, a second resistor, a first capacitor, a second capacitor, a first diode, a second diode, a first operational amplifier, and a second operational amplifier;

[0015] The first end of the first resistor is connected to the sampling circuit, the first end of the first capacitor is grounded, the second end of the first resistor and the second end of the first capacitor are respectively connected to the non-inverting input end of the first operational amplifier; the inverting input end of the first operational amplifier is respectively connected to the first end of the first diode and the first end of the second resistor, and the output end of the first operational amplifier is respectively connected to the second end of the first diode and the first end of the second diode;

[0016] The second end of the second diode and the first end of the second capacitor are respectively connected to the non-inverting input terminal of the second operational amplifier, and the second end of the second capacitor is grounded; the inverting input terminal of the second operational amplifier is respectively connected to the second end of the second resistor and the output terminal of the second operational amplifier; the output terminal of the second operational amplifier is also connected to the input terminal of the proportional amplifier circuit.

[0017] In an optional implementation, the proportional amplification circuit includes a third resistor, a fourth resistor, a fifth resistor and a third operational amplifier;

[0018] The first end of the third resistor is connected to the output end of the peak circuit, the second end of the third resistor and the first end of the fifth resistor are respectively connected to the inverting input end of the third operational amplifier, and the second end of the fifth resistor is connected to the output end of the third operational amplifier;

[0019] The non-inverting input terminal of the third operational amplifier is connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is grounded.

[0020] In an optional implementation, the average voltage circuit includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth resistor, a seventh resistor and an eighth resistor;

[0021] The first end of the first controllable switch, the first end of the third controllable switch and the first end of the third capacitor are connected together, and the second end of the third capacitor is grounded; the second end of the third controllable switch is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the output end of the first effective value circuit;

[0022] The second end of the first controllable switch, the first end of the second controllable switch, the first end of the fourth controllable switch and the first end of the fourth capacitor are connected together, and the second end of the fourth capacitor is grounded; the second end of the fourth controllable switch is connected to the first end of the seventh resistor, and the second end of the seventh resistor is connected to the output end of the second effective value circuit;

[0023] The second end of the second controllable switch, the first end of the fifth controllable switch and the first end of the fifth capacitor are connected together and respectively connected to each of the local digital signal processors, and the second end of the fifth capacitor is grounded; the second end of the fifth controllable switch is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the output end of the third effective value circuit.

[0024] In an optional implementation, the sampling circuit includes a ninth resistor, a first end of the ninth resistor is connected to the power circuit, and a second end of the ninth resistor is respectively connected to the local digital signal processor and a corresponding peak circuit.

[0025] In an optional embodiment, the average current circuit also includes a timer circuit, a voltage equalizing trigger circuit and a capacitor charging trigger circuit, the timer circuit is respectively connected to the voltage equalizing trigger circuit and the capacitor charging trigger circuit, and the voltage equalizing trigger circuit and the capacitor charging trigger circuit are respectively connected to the average voltage circuit.

[0026] In the second aspect, the utility model proposes a current sharing system based on uninterruptible power supplies in parallel, comprising a host computer, a plurality of uninterruptible power supplies in parallel, and a current sharing circuit based on uninterruptible power supplies in parallel as described in any one of the first aspects, each of the uninterruptible power supplies comprising an on-site digital signal processor and a power circuit; the host computer is respectively connected to the on-site digital signal processor in each of the uninterruptible power supplies, the on-site digital signal processor in each of the uninterruptible power supplies is connected to the power circuit in the uninterruptible power supply, and each of the power circuits is respectively connected to a load; each sampling circuit in the current sharing circuit based on uninterruptible power supplies in parallel is respectively connected to the power circuit and the on-site digital signal processor in each uninterruptible power supply; the average current circuit in the current sharing circuit based on uninterruptible power supplies in parallel is respectively connected to each of the on-site digital signal processors;

[0027] The host computer is used to send a power signal to each of the uninterruptible power supplies;

[0028] The local digital signal processor is used to adjust the current of the power signal according to the average voltage signal sent by the average current circuit and the voltage signal sent by the connected sampling circuit, so that the current of the power signal output by the local digital signal processor in each uninterruptible power supply is consistent;

[0029] The power circuit is used to generate an AC signal according to the adjusted power signal, and send the AC signal to a load.

[0030] The technical solution provided by the embodiment of the utility model has the following beneficial effects: the utility model is based on the current balancing circuit and current balancing system of the uninterruptible power supply in parallel, the current balancing circuit based on the uninterruptible power supply in parallel includes a sampling circuit and an average current circuit, by adding a sampling circuit in each uninterruptible power supply, collecting the current signal of the power circuit through the sampling circuit, and converting the current signal into a voltage signal and sending it to the average current circuit and the local digital signal processor in the connected uninterruptible power supply, the average current circuit outputs an average voltage signal according to the voltage signal sent by each sampling circuit, and then feeds the average voltage signal back to the local digital signal processor, and the local digital signal The digital signal processor adjusts the power signal according to the average voltage circuit fed back by the average current circuit and the voltage signal fed back by the sampling circuit, so that the current output by each local digital signal processor is consistent, and current sharing is achieved; in this way, the power signal current after inversion by each power circuit is balanced, thereby ensuring the stability and robustness of the circuitized uninterruptible power supply operation; the utility model does not change the output external characteristics of the circuitized uninterruptible power supply parallel system, does not affect the effect of feedback waveform control, and has a good inhibitory effect on the circulating current caused by the difference in the main circuit parameters of the inverter in the uninterruptible power supply; it can replace the parallel machine reactance, has a good instantaneous current sharing control effect, and has a broad application prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A system schematic diagram provided for an embodiment of the utility model;

[0032] Figure 2 A system schematic diagram of an average current circuit provided by an embodiment of the utility model;

[0033] Figure 3 A circuit schematic diagram of an effective value circuit provided by an embodiment of the utility model;

[0034] Figure 4 A circuit schematic diagram of an average voltage circuit provided by an embodiment of the utility model;

[0035] Figure 5 A system schematic diagram of an uninterruptible power supply cabinet provided for an embodiment of the utility model;

[0036] Figure 6 A simplified single inverter model provided for an embodiment of the utility model;

[0037] Figure 7 A schematic diagram of a single circuit uninterruptible power supply constant voltage single closed loop control circuit provided by an embodiment of the utility model;

[0038] Figure 8 A control block diagram of a first circuit provided in an embodiment of the utility model;

[0039] Fig. 9 A control block diagram of a second circuit provided in an embodiment of the utility model;

[0040] Fig.10 Schematic diagram of a multi-circuit current-sharing dual-parameter closed-loop control system provided by an embodiment of the utility model;

[0041] Fig.11 The embodiment of the utility model provides Fig.10 Structure diagram of

[0042] Fig.12 A schematic diagram of a multi-circuit parallel system provided for an embodiment of the utility model;

[0043] Fig.13 A simulation result diagram of an effective value circuit provided by an embodiment of the utility model;

[0044] Fig.14 Another simulation result diagram of the effective value circuit provided by the embodiment of the utility model;

[0045] Fig.15 A circuit schematic diagram of a timer circuit provided in an embodiment of the utility model;

[0046] Fig.16 A simulation circuit diagram of an average voltage circuit provided by an embodiment of the utility model;

[0047] Fig.17 Another simulation circuit diagram of the average voltage circuit provided by the embodiment of the utility model;

[0048] Fig.18 A partial circuit schematic diagram of a voltage-sharing trigger circuit provided in an embodiment of the utility model;

[0049] Fig.19 Another part of the circuit schematic diagram of the voltage-sharing trigger circuit provided by the embodiment of the utility model;

[0050] Fig. 20 A schematic diagram of a capacitor charging trigger circuit provided by an embodiment of the utility model;

[0051] Fig.21 A simulation result diagram of a timer circuit provided by an embodiment of the utility model;

[0052] Fig. 22 This is a simulation result diagram of the average voltage circuit provided in an embodiment of the utility model.

[0053] In the figure: 1-first circuit; 2-second circuit; 10-sampling circuit; 20-average current circuit; 21-effective value circuit; 211-peak circuit; 212-proportional amplifier circuit; 22-average voltage circuit; 30-uninterruptible power supply; 301-on-site digital signal processor; 302-power circuit; 40-load; 51-input switch; 52-PFC / IGBT rectifier; 53-maintenance bypass switch; 54-battery; 55-inverter; 56-bypass static switch; 57-output switch; 61-average current calculator; 70-host computer; 100-current sharing circuit based on uninterruptible power supply parallel connection. DETAILED DESCRIPTION

[0054] The present invention will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0055] Reference Figure 1 The utility model proposes a current balancing circuit 100 based on parallel connection of uninterruptible power supplies, comprising a plurality of sampling circuits 10 and an average current circuit 20, each sampling circuit 10 is respectively connected to a power circuit 302 and an on-site digital signal processor 301 in each uninterruptible power supply 30, and the average current circuit 20 is respectively connected to each sampling circuit 10 and an on-site digital signal processor 301 in each uninterruptible power supply 30;

[0056] The sampling circuit 10 is used to collect the current signal of the power circuit 302 in the connected uninterruptible power supply 30, and convert the current signal into a voltage signal and send it to the average current circuit 20 and the local digital signal processor 301 in the connected uninterruptible power supply 30;

[0057] The average current circuit 20 is used to output an average voltage signal according to the voltage signal sent by each sampling circuit 10, and send the average voltage signal to each local digital signal processor 301 respectively.

[0058] Preferably, refer to Figure 2 The average current circuit 20 of this embodiment includes a plurality of effective value circuits 21 and an average voltage circuit 22; each effective value circuit 21 is respectively connected to the corresponding sampling circuit 10, each effective value circuit 21 is respectively connected to the average voltage circuit 22, and the average voltage circuit 22 is connected to the local digital signal processor 301; the effective value circuit 21 is used to output an effective value signal corresponding to the voltage signal according to the voltage signal sent by the corresponding sampling circuit 10; the average voltage circuit 22 is used to output an average voltage signal according to the effective value signal sent by each effective value circuit 21, and send the average voltage signal to the local digital signal processor 301; Figure 2 The average current circuit 20 includes an effective value circuit 21 and an average voltage circuit 22. The effective value circuit further includes a peak value circuit 211 and a proportional amplifier circuit 212. The peak value circuit 211 is used to determine the peak value signal corresponding to the voltage signal, and the proportional amplifier circuit 212 is used to determine the effective value signal corresponding to the voltage signal according to the peak value signal, thereby converting the voltage signal into an effective value signal. Finally, the average voltage circuit 22 determines the average voltage according to the effective value signals of each channel.

[0059] Further, refer to Figure 2 , Figure 2 The first effective value circuit, the second effective value circuit, ... the Nth effective value circuit are listed in the embodiment. Through these circuits, the actual current average value is converted into the voltage average value. Each effective value circuit 21 includes a peak circuit 211 and a proportional amplifier circuit 212 connected in series; the peak circuit 211 is connected to the corresponding sampling circuit 10, and the proportional amplifier circuit 212 is connected to the average voltage circuit 22;

[0060] The peak value circuit 211 is used to determine the peak value signal corresponding to the voltage signal sent by the corresponding sampling circuit 10, and send the peak value signal to the proportional amplification circuit 212;

[0061] The proportional amplifier circuit 212 is used to determine the effective value signal corresponding to the peak signal and send the effective value signal to the average voltage circuit 22 .

[0062] In a possible embodiment, reference Figure 3 , a specific circuit diagram of one of the effective value circuits 21 is given, wherein the peak circuit 211 includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a first diode D1, a second diode D2, a first operational amplifier U1 and a second operational amplifier U2;

[0063] The first end of the first resistor R1 is connected to the input voltage, the first end of the first capacitor C1 is grounded, the second end of the first resistor R1 and the second end of the first capacitor C1 are respectively connected to the non-inverting input end of the first operational amplifier U1; the inverting input end of the first operational amplifier U1 is respectively connected to the first end of the first diode D1 and the first end of the second resistor R2, and the output end of the first operational amplifier U1 is respectively connected to the second end of the first diode D1 and the first end of the second diode D2;

[0064] The second end of the second diode D2 and the first end of the second capacitor C2 are respectively connected to the in-phase input end of the second operational amplifier U2, and the second end of the second capacitor C2 is grounded; the inverting input end of the second operational amplifier U2 is respectively connected to the second end of the second resistor R2 and the output end of the second operational amplifier U2; the output end of the second operational amplifier U2 is also connected to the input end of the proportional amplifier circuit 212. Figure 3 As shown, the output end of the second operational amplifier U2 is connected to the first end of the third resistor R3 in the proportional amplifier circuit 212 .

[0065] exist Figure 3 In, V p is the output voltage of the peak circuit 211, that is, the peak signal. Figure 3 The circuit shown in the figure is simulated. When the output voltage signal V of the sampling circuit 10 is i =3×1.414, the peak signal V p The simulation results are as follows Fig.13 In the figure, waveform b2 represents Vi, and waveform b1 represents Vp.

[0066] Further, refer to Figure 3 , the proportional amplifier circuit 212 includes a third resistor R3, a fourth resistor R4, a fifth resistor R5 and a third operational amplifier U3;

[0067] A first end of the third resistor R3 is connected to the output end of the second operational amplifier U2, a second end of the third resistor R3 and a first end of the fifth resistor R5 are respectively connected to the inverting input end of the third operational amplifier U3, and a second end of the fifth resistor R5 is connected to the output end of the third operational amplifier U3;

[0068] A non-inverting input terminal of the third operational amplifier U3 is connected to a first terminal of a fourth resistor R4, and a second terminal of the fourth resistor R4 is grounded.

[0069] exist Figure 3In the example, the output voltage Vrms of the third operational amplifier U3 is the output voltage of the proportional amplifier circuit 212, that is, the effective value signal. i =3×1.414, the simulation result of the effective value signal Vrms is as follows Fig.14 In the figure, waveform b3 represents Vrms, and waveform b4 represents Vi.

[0070] Furthermore, this embodiment takes the output voltages Vrms1, Vrms2, and Vrms3 of three effective value circuits as an example to illustrate the average value circuit. Figure 4 , the average voltage circuit 22 includes a first controllable switch S1, a second controllable switch S2, a third controllable switch S3, a fourth controllable switch S4, a fifth controllable switch S5, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth resistor R6, a seventh resistor R7 and an eighth resistor R8;

[0071] A first end of the first controllable switch S1, a first end of the third controllable switch S3 and a first end of the third capacitor C3 are connected together, and a second end of the third capacitor C3 is grounded; a second end of the third controllable switch S3 is connected to a first end of a sixth resistor R6, and a second end of the sixth resistor R6 is connected to an output end Vrms1 of the first effective value circuit;

[0072] The second end of the first controllable switch S1, the first end of the second controllable switch S2, the first end of the fourth controllable switch S4 and the first end of the fourth capacitor C4 are connected together, and the second end of the fourth capacitor C4 is grounded; the second end of the fourth controllable switch S4 is connected to the first end of the seventh resistor R7, and the second end of the seventh resistor R7 is connected to the output end Vrms2 of the second effective value circuit;

[0073] The second end of the second controllable switch S2, the first end of the fifth controllable switch S5 and the first end of the fifth capacitor C5 are connected together and respectively connected to each local digital signal processor 301, and the second end of the fifth capacitor C5 is grounded; the second end of the fifth controllable switch S5 is connected to the first end of the eighth resistor R8, and the second end of the eighth resistor R8 is connected to the output end Vrms3 of the third effective value circuit.

[0074] Figure 4 The output voltage Vav is the average voltage signal. Figure 4 The switches S1 to S5 are all controllable switches. To this end, the average current circuit 20 of this embodiment further includes a timer circuit, a voltage balancing trigger circuit and a capacitor charging trigger circuit, the timer circuit is respectively connected to the voltage balancing trigger circuit and the capacitor charging trigger circuit, and the voltage balancing trigger circuit and the capacitor charging trigger circuit are respectively connected to the average voltage circuit.

[0075] Specifically, Fig.15 For the timer circuit, Figure 18-19 It is a voltage-balanced trigger circuit. Fig. 20 To charge the capacitor trigger circuit. Fig.15 As shown, the timer circuit includes a timer U4A, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a sixth capacitor and a seventh capacitor. The VCC terminal of the timer U4A is connected to the power supply VCC, the RST terminal of the timer U4A is also connected to the power supply VCC, the DIS terminal and the RST terminal of the timer U4A are respectively connected to the two ends of the tenth resistor R10, the DIS terminal of the timer U4A is connected to the first end of the eleventh resistor R11, the TRI terminal and the THR terminal of the timer U4A are short-circuited and then connected to the second end of the eleventh resistor R11, the first end of the sixth capacitor C6 is connected to the TRI terminal of the timer U4A, the first end of the seventh capacitor C7 is connected to the CON terminal of the timer U4A, the second end of the sixth capacitor C6 is connected to the second end of the seventh capacitor C7 and are respectively grounded, the GND terminal of the timer U4A is grounded, the OUT terminal of the timer U4A is connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 is connected to the power supply VCC.

[0076] The period of timer U4A in the timer circuit is 210ms and the duty cycle is 33%. Fig.21 This is a simulation result diagram of the timer resistor. In the figure, waveform b5 represents tri and waveform b6 represents timer.

[0077] The voltage-balanced trigger circuit includes first triggers S1A, S1B, an eighteenth resistor R18 and a nineteenth resistor R19. Fig.18 is a circuit diagram of the first trigger S1A, wherein the first terminal of the first trigger S1A is connected to Fig.17 The Vc1 terminal in the Fig.17 The Vc2 terminal in the circuit, the 13th terminal is connected to the OUT terminal of the timer U4A via the inverter U5A, the 7th terminal is grounded, the 2nd terminal is also connected to one end of the eighteenth resistor R18, and the other end of the eighteenth resistor R18 is grounded.

[0078] Fig.19 The 4th terminal of the first trigger S1B is connected to Fig.17 The Vc2 in the circuit is connected to the OUT terminal of the timer U4A through the inverter U5B, and the 3rd terminal is connected to the Fig.17 The third end of Vc3 is also connected to one end of a nineteenth resistor R19, and the other end of the nineteenth resistor R19 is grounded.

[0079] After the timer circuit is connected to the first triggers S1A and S1B, it is triggered at a low level to control the on and off of the controllable switch through the two triggers, so that the output voltage Vav is an average voltage.

[0080] The timer circuit also controls the capacitor charging trigger circuit through a high level to trigger the charging of the third capacitor C3, the fourth capacitor C4 and the fifth capacitor C5. Fig. 20 As shown in FIG. 1 , a capacitor charging trigger circuit for charging the third capacitor C3 is provided, including a second trigger S2A and a twentieth resistor R20. The first terminal of the second trigger S2A is connected to Fig.17 The SW1 terminal in the Fig.17 The 13th terminal is connected to the OUT terminal of the timer U4A, the 7th terminal is grounded, the 2nd terminal is also connected to the first terminal of the 20th resistor R20, and the second terminal of the 20th resistor R20 is grounded. The capacitor trigger circuit for triggering the charging of the fourth capacitor C4 and the fifth capacitor C5 is Fig. 20 The circuit structure is the same as in , and will not be repeated here.

[0081] The timer circuit, voltage-equalizing trigger circuit and average voltage circuit are simulated below.

[0082] Fig.16 and Fig.17 The simulation circuit corresponds to the average voltage circuit when simulating in the simulation software. Take the output voltage of the three-way proportional amplifier circuit Vrms1 = 3V, Vrms2 = 4V, Vrms4 = 5V as an example for simulation. Fig.16 is the corresponding power supply circuit. The final simulation results are as follows Fig. 22 shown. Fig. 22 In the figure, channel A is Vc1, channel B is Vc2, channel C is Vc3, and channel D is Vav. The simulation results show that Vav = 3.937V, which is close to the theoretical average voltage (3+4+5) / 3 = 4V, and its voltage loss is the equivalent resistance loss of the voltage-equalizing capacitor.

[0083] Preferably, the sampling circuit 10 includes a ninth resistor R9 (not shown in the figure), a first end of the ninth resistor is connected to the power circuit 302, and a second end of the ninth resistor is respectively connected to the local digital signal processor 301 and the corresponding peak circuit 211.

[0084] Reference Figure 1 The present embodiment proposes a current sharing system based on uninterruptible power supplies in parallel, including a host computer 70, a plurality of uninterruptible power supplies 30 (UPS modules) in parallel, and the aforementioned current sharing circuit 100 based on uninterruptible power supplies in parallel, each uninterruptible power supply 30 including an on-site digital signal processor 301 (on-site DSP) and a power circuit 302.

[0085] The connection relationship between each circuit is as follows: the host computer 70 is connected to the local digital signal processor 301 in each uninterruptible power supply 30, the local digital signal processor 301 in each uninterruptible power supply 30 is connected to the power circuit 302 in the uninterruptible power supply 30, and each power circuit 302 is connected to the load 40; the sampling circuit 10 in the current equalization circuit 100 based on the uninterruptible power supply in parallel is connected to the power circuit 302 in the uninterruptible power supply 30 and the local digital signal processor 301 in the uninterruptible power supply 30; the average current circuit 20 in the current equalization circuit 100 based on the uninterruptible power supply in parallel is connected to each sampling circuit 10 and each local digital signal processor 301. Figure 1 Two groups of uninterruptible power supplies 30 are shown. In actual applications, multiple groups of uninterruptible power supplies 30 may be connected in parallel between the two groups of uninterruptible power supplies 30.

[0086] The host computer 70 is used to send a power signal to each uninterruptible power supply 30; the power signal is a sine wave reference signal, and in some possible embodiments, it can also be a pulse width modulation wave (PWM wave), a square wave or other types of waves. In practical applications, the host computer 70 can be a digital signal processor. Figure 1 As shown, the host computer 70 sends power supply signals (modulated waves) through the output bus. The output end of the power circuit 302 of each uninterruptible power supply 30 is connected to the L line (live line) and the N line (neutral line), and the load 40 is connected to the L line and the N line respectively.

[0087] The sampling circuit 10 is used to collect the current signal of the power circuit 302 in the connected uninterruptible power supply 30, and convert the current signal into a voltage signal and send it to the average current circuit 20 and the local digital signal processor 301; in some possible embodiments, the sampling purpose of the sampling circuit 10 can be achieved using a resistor.

[0088] The average current circuit 20 is used to output an average voltage signal according to the voltage signal sent by each sampling circuit 10, and send the average voltage signal to each local digital signal processor 301 respectively; this embodiment obtains the effective value of each voltage signal through the effective value circuit 21, and then obtains the average voltage of each path through the average voltage circuit.

[0089] The local digital signal processor 301 is used to adjust the current of the power signal according to the average voltage signal and the voltage signal sent by the connected sampling circuit 10, so that the current of the power signal output by the local digital signal processor 301 in each uninterruptible power supply 30 is consistent; preferably, the local digital signal processor 301 generates a corresponding modulation waveform based on the average current corresponding to the average voltage signal and the current corresponding to the voltage signal sent by the connected sampling circuit 10, and refers to the difference between the two currents, so as to facilitate the use of the waveform to control the action of the switch tube and complete current sharing.

[0090] The power circuit 302 is used to generate an AC output after current sharing according to the adjusted power signal, and send the AC output to the load 40 .

[0091] The design principle of this embodiment is further described below.

[0092] like Figure 5 As shown, it is a system schematic diagram of an uninterruptible power supply cabinet (box) of this embodiment. The uninterruptible power supply cabinet is provided with three switches, one is an input switch 51, one is an output switch 57, and the other is a maintenance bypass switch 53. The PFC / IGBT rectifier 52 rectifies the 220V mains power, and the battery 54 is used to store electric energy. When the power is off, the battery 54 provides direct current, and the inverter 55 converts the direct current into alternating current, and outputs it to the power load through the bypass static switch 56 and the output switch 57.

[0093] The simplified single inverter model is as follows: Figure 6 As shown, the two ends of the DC power supply are connected to the inverter bridge respectively, and the inverter bridge is connected in series with the inductor L and then in parallel with the capacitor C. Figure 7 As shown, Figure 7 In the figure, R(s) is a proportional-integral-derivative (PID) regulator and Hf(s) is a voltage sampling controller.

[0094] When the switching frequency is high, the harmonics near and above the switching frequency are ignored, and the bridge converter is a proportional amplification link k inv However, due to the existence of factors such as dead zone, the SPWM output of the inverter bridge will produce a deviation voltage u e , and contains a large number of low-order harmonics. Nonlinear loads will cause the output current i o Contains a large number of harmonics, which is also an important reason for waveform distortion. These two factors exist as disturbance terms to simplify the analysis process. Figure 7 The sub-circuit modeling is divided into two parts, the first circuit 1 and the second circuit 2. The control block diagram of the first circuit 1 introducing instantaneous voltage feedback is as follows Figure 8 shown.

[0095] The second circuit 2 can directly draw the corresponding control block diagram, considering the existence of the deviation voltage u e and the output current i o The negative feedback is introduced, and this diagram has completely constituted a closed-loop control of a single circuit, such as Fig. 9 shown.

[0096] Multi-circuit current sharing dual-parameter closed-loop control Fig.10 As shown, where i H1 is i p and i o1The difference between the total output current and the current equalization regulator is H(S). The average value of the total output current in the parallel circuit is taken as the reference term i p , when studying parallel circuit current sharing or considering nonlinear loads, u e Although the disturbance term exists, it is considered weakly, u e It has been used as a circuit-level voltage quality control quantity. The transfer function control structure diagram is as follows: Fig.11 As shown. The current loop responds quickly, making each circuit i k tend to i p , and finally the voltage loop is stabilized.

[0097] Fig.12 This is a multi-circuit parallel system diagram. This structure is easy to connect in parallel. The failure of any circuit does not affect the operation of other circuits. This structure adds an average current calculator 61, which is equivalent to Figure 1 The sampling circuit 10 and the average current circuit 20 are combined. Fig.12 On the basis of, this application has been further deepened, and the average current feedback is introduced into the voltage instantaneous feedback control system of each inverter. The instantaneous current sharing control is under a single circuit closed loop, and the instantaneous circulating current is introduced. The difference between the instantaneous average current obtained from the current sharing bus and the circuit's own output current is the circuit's instantaneous circulating current. The instantaneous current sharing closed-loop control directly adjusts the command voltage and the impedance regulator H(s) according to the instantaneous circulating current, so that the module output current is consistent with the average output current of the system, thereby realizing load balancing of each inverter module in the parallel system.

[0098] Reference Figure 1 In this embodiment, the inverters in the uninterruptible power supplies 30 receive the power signal (sine wave reference signal) uniformly sent by the host computer 70 and output it.

[0099] Since the modules are connected in parallel, the output voltage is forced to be the same voltage, but the output current of each interrupter component is different. The output current i oj The corresponding AC voltage signal is converted into the corresponding AC voltage signal, which is introduced into the average current circuit 20. The average current circuit 20 obtains the average voltage according to the voltage signals of each channel, and then feeds the average voltage back to the local digital signal processor 301 in each channel, so that each local digital signal processor 301 controls the power circuit 302 in its own circuit to make the AC signal current output by each power circuit 302 consistent, thus achieving current sharing. In the implementation method, the voltage signal corresponds to Fig.10 and Fig.11 The output current i oj , the average voltage corresponds to Fig.10 and Fig.11 The average current i p ,i oj and i p These are the two parameters corresponding to the “double parameters” in this embodiment.

[0100] In specific implementation, the voltage amplitude and frequency of the sampling circuit 10 are controlled by the local digital signal processor 301, and its modulation wave is uniformly sent by the host computer 70. The voltage phase lock is sent by the host computer 70 to the local digital signal processor 301 to ensure the same phase, and the sampling circuit 10 is used to detect again to form a closed loop. The host computer 70 should also check the phase of the mains power and have a phase lock function.

[0101] The current sharing circuit 100 based on the uninterruptible power supply in parallel of this embodiment can adjust the circulating current impedance characteristics to be purely resistive through the regulator H(s), without changing the output external characteristics of the parallel system, without affecting the effect of the instantaneous value feedback waveform control, and has a good inhibitory effect on the circulating current caused by the difference in the parameters of the inverter main circuit in the uninterruptible power supply 30. Digital control based on digital signal processor can replace the parallel electromechanical reactance, and the current sharing control strategy using a dual-parameter closed loop has a good instantaneous current sharing control effect. This current sharing control strategy has a good application prospect in modular uninterruptible power supplies with N+1 redundant parallel control.

[0102] It is known from common technical knowledge that the present invention can be implemented by other embodiments that do not deviate from its spirit or essential features. Therefore, the embodiments disclosed above are only illustrative in all respects and are not exclusive. All changes within the scope of the present invention or within the scope equivalent to the present invention are included in the present invention.

Claims

1. A current sharing circuit based on uninterruptible power supplies in parallel, characterized in that: It includes a plurality of sampling circuits and an average current circuit, each of the sampling circuits is respectively connected to a power circuit and an on-site digital signal processor in each uninterruptible power supply, and the average current circuit is respectively connected to each of the sampling circuits and an on-site digital signal processor in each uninterruptible power supply; The sampling circuit is used to collect the current signal of the power circuit in the connected uninterruptible power supply, and convert the current signal into a voltage signal and send it to the average current circuit and the local digital signal processor in the connected uninterruptible power supply; The average current circuit is used to output an average voltage signal according to the voltage signal sent by each sampling circuit, and send the average voltage signal to each of the local digital signal processors respectively.

2. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 1, characterized in that: The average current circuit includes a plurality of effective value circuits and an average voltage circuit; each of the effective value circuits is respectively connected to a corresponding sampling circuit, each of the effective value circuits is also respectively connected to an average voltage circuit, and the average voltage circuit is respectively connected to the local digital signal processor in each of the uninterruptible power supplies; The effective value circuit is used to output an effective value signal corresponding to the voltage signal according to the voltage signal sent by the corresponding sampling circuit; The average voltage circuit is used to output an average voltage signal according to the effective value signal sent by each effective value circuit, and send the average voltage signal to an on-site digital signal processor.

3. According to the current-sharing circuit based on uninterruptible power supply parallel connection in claim 2, each of the effective value circuits comprises a peak circuit and a proportional amplifier circuit connected in series in sequence; the peak circuit is connected to a corresponding sampling circuit, and the proportional amplifier circuit is connected to the average voltage circuit; The peak circuit is used to determine a peak signal corresponding to a voltage signal sent by a corresponding sampling circuit, and send the peak signal to a proportional amplification circuit; The proportional amplifier circuit is used to determine the effective value signal corresponding to the peak signal and send the effective value signal to the average voltage circuit.

4. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 3, characterized in that: The peak circuit includes a first resistor, a second resistor, a first capacitor, a second capacitor, a first diode, a second diode, a first operational amplifier and a second operational amplifier; The first end of the first resistor is connected to the sampling circuit, the first end of the first capacitor is grounded, the second end of the first resistor and the second end of the first capacitor are respectively connected to the non-inverting input end of the first operational amplifier; the inverting input end of the first operational amplifier is respectively connected to the first end of the first diode and the first end of the second resistor, and the output end of the first operational amplifier is respectively connected to the second end of the first diode and the first end of the second diode; The second end of the second diode and the first end of the second capacitor are respectively connected to the non-inverting input terminal of the second operational amplifier, and the second end of the second capacitor is grounded; the inverting input terminal of the second operational amplifier is respectively connected to the second end of the second resistor and the output terminal of the second operational amplifier; the output terminal of the second operational amplifier is also connected to the input terminal of the proportional amplifier circuit.

5. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 3, characterized in that: The proportional amplification circuit includes a third resistor, a fourth resistor, a fifth resistor and a third operational amplifier; The first end of the third resistor is connected to the output end of the peak circuit, the second end of the third resistor and the first end of the fifth resistor are respectively connected to the inverting input end of the third operational amplifier, and the second end of the fifth resistor is connected to the output end of the third operational amplifier; The non-inverting input terminal of the third operational amplifier is connected to the first terminal of the fourth resistor, and the second terminal of the fourth resistor is grounded.

6. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 2, characterized in that: The average voltage circuit includes a first controllable switch, a second controllable switch, a third controllable switch, a fourth controllable switch, a fifth controllable switch, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth resistor, a seventh resistor and an eighth resistor; The first end of the first controllable switch, the first end of the third controllable switch and the first end of the third capacitor are connected together, and the second end of the third capacitor is grounded; the second end of the third controllable switch is connected to the first end of the sixth resistor, and the second end of the sixth resistor is connected to the output end of the first effective value circuit; The second end of the first controllable switch, the first end of the second controllable switch, the first end of the fourth controllable switch and the first end of the fourth capacitor are connected together, and the second end of the fourth capacitor is grounded; the second end of the fourth controllable switch is connected to the first end of the seventh resistor, and the second end of the seventh resistor is connected to the output end of the second effective value circuit; The second end of the second controllable switch, the first end of the fifth controllable switch and the first end of the fifth capacitor are connected together and respectively connected to each of the local digital signal processors, and the second end of the fifth capacitor is grounded; the second end of the fifth controllable switch is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the output end of the third effective value circuit.

7. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 3, characterized in that: The sampling circuit comprises a ninth resistor, a first end of the ninth resistor is connected to the power circuit, and a second end of the ninth resistor is respectively connected to the local digital signal processor and a corresponding peak circuit.

8. The current-sharing circuit based on uninterruptible power supplies in parallel according to claim 6, characterized in that: The average current circuit also includes a timer circuit, a voltage equalizing trigger circuit and a capacitor charging trigger circuit. The timer circuit is connected to the voltage equalizing trigger circuit and the capacitor charging trigger circuit respectively, and the voltage equalizing trigger circuit and the capacitor charging trigger circuit are connected to the average voltage circuit respectively.

9. A current sharing system based on uninterruptible power supplies in parallel, characterized in that: It comprises a host computer, a plurality of uninterruptible power supplies connected in parallel, and a current-sharing circuit based on uninterruptible power supplies connected in parallel as claimed in any one of claims 1 to 8, each of the uninterruptible power supplies comprising an on-site digital signal processor and a power circuit; the host computer is respectively connected to the on-site digital signal processor in each of the uninterruptible power supplies, the on-site digital signal processor in each of the uninterruptible power supplies is connected to the power circuit in the uninterruptible power supply, and each of the power circuits is respectively connected to a load; each sampling circuit in the current-sharing circuit based on uninterruptible power supplies connected in parallel is respectively connected to the power circuit and the on-site digital signal processor in each uninterruptible power supply; the average current circuit in the current-sharing circuit based on uninterruptible power supplies connected in parallel is respectively connected to each of the on-site digital signal processors; The host computer is used to send a power signal to each of the uninterruptible power supplies; The local digital signal processor is used to adjust the current of the power signal according to the average voltage signal sent by the average current circuit and the voltage signal sent by the connected sampling circuit, so that the current of the power signal output by the local digital signal processor in each uninterruptible power supply is consistent; The power circuit is used to generate an AC signal according to the adjusted power signal, and send the AC signal to a load.

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