Adjustable pulse generator

Abstract

The utility model provides an adjustable pulse generator. The adjustable pulse generator comprises an input unit, a control unit and a driving circuit, the input unit is used for receiving a PWM signal parameter value input by a user; the control unit is used for outputting a PWM signal with a preset frequency and a preset duty ratio based on a PWM signal parameter value input by a user; and the driving circuit is used for modulating the PWM signal output by the control unit so as to drive the power semiconductor device to be tested. According to the adjustable pulse generator provided by the invention, parameters such as the frequency and the duty ratio of the pulse signal are adjustable, the circuit structure is simple, the cost is relatively low, and the size of a test tool is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor device testing, and in particular to an adjustable pulse generator. Background Art

[0002] IGBT (Insulated Gate Bipolar Transistor) is a composite fully controlled voltage-driven power semiconductor device composed of BJT (Bipolar Junction Transistor) and MOSFET (Metal Oxide-Semiconductor FET). It has the advantages of both the high input impedance of MOSFET and the low on-state voltage drop of GTR (Giant Transistor).

[0003] Before using IGBT, in order to verify whether the parameters and performance of IGBT meet the requirements, it is necessary to perform a double pulse drive wave test on IGBT. However, existing IGBT double pulse test tools are often too large, costly, complicated to operate, and the output double pulse waveform frequency, duty cycle and other parameters cannot be adjusted. Utility Model Content

[0004] The present application provides an adjustable pulse generator, aiming to solve the problems of existing pulse testing tools, such as large size, high cost, complex operation and fixed and non-adjustable pulse parameters.

[0005] The present application provides an adjustable pulse generator for power semiconductor drive testing, the adjustable pulse generator comprising an input unit, a control unit and a drive circuit;

[0006] The input unit is used to receive a PWM signal parameter value input by a user;

[0007] The control unit is used to output a PWM signal with a preset frequency and a preset duty cycle based on a PWM signal parameter value input by a user;

[0008] The driving circuit is used to modulate the PWM signal output by the control unit to drive the power semiconductor device to be tested.

[0009] In one example, the PWM signal parameters include a frequency division coefficient and a comparison value.

[0010] In one example, the driving circuit is connected to the power semiconductor device to be tested using an optical fiber.

[0011] In one example, the driving circuit includes a data buffer generator and an optical transmitter;

[0012] The data buffer generator is used to receive the PWM signal output by the control unit and modulate the received PWM signal;

[0013] The optical transmitter is used to output the modulated signal generated by the data buffer generator to the power semiconductor device to be tested.

[0014] In one example, the data buffer generator includes a multi-channel signal input pin and a multi-channel signal output pin, and the optical transmitter includes a multi-channel optical transmitter;

[0015] The multi-channel signal input pin is used to receive the multi-channel PWM signals output by the control unit;

[0016] The multi-channel signal output pins are connected to the multi-channel optical transmitters in a one-to-one correspondence to output the multi-channel modulated signals generated by the data buffer generator to the power semiconductor device to be tested.

[0017] In one example, the data buffer generator includes an enable pin;

[0018] The enable pin is configured to enable the output of the data buffer generator when receiving a first level signal, and to enable the output of the data buffer generator to be in a high impedance mode when receiving a second level signal.

[0019] In one example, a level signal generating circuit is also included;

[0020] The level signal generating circuit is configured to receive an enable signal to generate the first level signal or the second level signal.

[0021] In one example, the level signal generating circuit includes a switch circuit and a pull-up circuit;

[0022] The first electrode terminal of the switch circuit is connected to one end of the pull-up circuit and the enable pin, the second electrode terminal of the switch circuit is grounded, the control end of the switch circuit is used to receive an enable signal, and the other end of the pull-up circuit is connected to a power supply voltage.

[0023] In one example, a display unit connected to the control unit is further included, and the display unit is used to display one of the following: a PWM signal parameter value, a PWM signal frequency, and a PWM signal duty cycle.

[0024] In one example, a power supply circuit and a voltage regulating circuit are also included;

[0025] The power supply circuit is used to provide a power supply voltage;

[0026] The voltage regulating circuit is used to regulate the power supply voltage provided by the power supply circuit, and output the regulated voltage to supply power to the control unit and the drive circuit.

[0027] The adjustable pulse generator provided in the present application has adjustable parameters such as the frequency and duty cycle of the pulse signal, a simple circuit structure, low cost, and a reduced size of the test tool. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0029] Figure 1 is a block diagram of an adjustable pulse generator provided in an embodiment of the present application;

[0030] Figure 2 It is a pulse signal modulation schematic diagram provided in an embodiment of the present application;

[0031] Figure 3 It is a schematic diagram of a driving circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present application. The terms used in this specification in the specification of the present application are only for the purpose of describing specific embodiments and are not used to limit the present application. The term "and / or" used in this specification includes any and all combinations of one or more related listed items.

[0033] Figure 1 It is a block diagram of an adjustable pulse generator provided in an embodiment of the present application.

[0034] like Figure 1 As shown, the embodiment of the present application provides an adjustable pulse generator for power semiconductor drive testing. The adjustable pulse generator includes:

[0035] The power supply circuit is used to provide power supply voltage. For example, the power supply circuit includes a lithium battery, the voltage of the lithium battery is between 3.6 and 4.2V, and the power supply circuit integrates a boost circuit to output a 5V voltage to the back-end circuit.

[0036] The voltage regulating circuit is used to regulate the power supply voltage provided by the power supply circuit and output the regulated voltage to power the control unit, the display unit, the drive circuit, etc. For example, the 5V voltage provided by the power supply circuit is regulated to output a stable 3.3V voltage to the control unit, the display unit, and the drive circuit. The voltage regulating circuit may include a common three-terminal linear regulator or other DC-DC conversion circuits.

[0037] The control unit is used to output a PWM (Pulse Width Modulation) signal with a preset frequency and a preset duty cycle. The control unit can be a microcontroller such as STM32.

[0038] The driving circuit is connected to the power semiconductor device to be tested by using an optical fiber; the driving circuit is used to modulate the PWM signal output by the control unit to drive the power semiconductor device to be tested.

[0039] In one example, the adjustable pulse generator further includes an input unit for receiving a PWM signal parameter value input by a user; the control unit can output a PWM signal with a preset frequency and a preset duty cycle based on the PWM signal parameter value input by the user.

[0040] The PWM signal parameters include a frequency division coefficient and a comparison value.

[0041] like Figure 2 As shown, by enabling the internal timer of STM32, the CNT count is started, and the CNT count frequency is related to the main control frequency of the control unit. In the initial state, when the CNT count is less than the comparison value CRRX, the control unit output port outputs a high-level signal; when the CNT count is greater than or equal to the comparison value CRRX, the control unit outputs a low-level signal; when the CNT count is equal to the system frequency division coefficient ARR, the CNT count is reset and the control unit returns to the initial state; that is, changing the system frequency division coefficient ARR can change the frequency of the output PWM signal, and changing the comparison value CRRX can change the duty cycle of the PWM signal.

[0042] For example, assuming that the main control frequency F of STM32 is 72MHz, the system frequency division coefficient ARR is 1000, and the comparison value CRRX is 500, the frequency of the output PWM signal is F / ARR=72kHz, and the duty cycle of the output PWM signal is CRRX / ARR*100%=50%.

[0043] In one example, the adjustable pulse generator further includes a display unit connected to the control unit, and the display unit and the control unit can be connected in communication using an SPI communication protocol. The display unit is used to display one of the following: a PWM signal parameter value, a PWM signal frequency, and a PWM signal duty cycle.

[0044] In one example, the driving circuit includes a data buffer generator and an optical transmitter;

[0045] The data buffer generator is used to receive the PWM signal output by the control unit and modulate the received PWM signal;

[0046] The optical transmitter is used to output the modulated signal generated by the data buffer generator to the power semiconductor device to be tested.

[0047] In one example, the data buffer generator includes a multi-channel signal input pin and a multi-channel signal output pin, and the optical transmitter includes a multi-channel optical transmitter;

[0048] The multi-channel signal input pin is used to receive the multi-channel PWM signals output by the control unit;

[0049] The multi-channel signal output pins are connected to the multi-channel optical transmitters in a one-to-one correspondence to output the multi-channel modulated signals generated by the data buffer generator to the power semiconductor device to be tested.

[0050] In one example, the data buffer generator includes an enable pin;

[0051] The enable pin is configured to enable the output of the data buffer generator when receiving a first level signal, and to enable the output of the data buffer generator to be in a high impedance mode when receiving a second level signal.

[0052] In one example, a level signal generating circuit is also included;

[0053] The level signal generating circuit is configured to receive an enable signal to generate the first level signal or the second level signal.

[0054] In one example, the level signal generating circuit includes a switch circuit and a pull-up circuit;

[0055] The first electrode terminal of the switch circuit is connected to one end of the pull-up circuit and the enable pin, the second electrode terminal of the switch circuit is grounded, the control end of the switch circuit is used to receive an enable signal, and the other end of the pull-up circuit is connected to a power supply voltage.

[0056] by Figure 3For example, the driving circuit includes a data buffer generator U1 and a multi-channel optical transmitter (shown as FC1 to FC4 in the figure).

[0057] The data buffer generator U1 includes multiple signal input pins and multiple signal output pins. Specifically, pins 2, 4, 6 and 8 of the data buffer generator U1 are signal input pins, and pins 12, 14, 16 and 18 of the data buffer generator U1 are signal output pins.

[0058] Pin 2 of the data buffer generator U1 is connected to the first PWM input signal HRTIMI_CHA1 through a current limiting resistor R4 (i.e., receives the first PWM input signal HRTIMI_CHA1, and similarly below), pin 4 of the data buffer generator U1 is connected to the second PWM input signal HRTIMI_CHA2 through a current limiting resistor R5, pin 6 of the data buffer generator U1 is connected to the third PWM input signal HRTIMI_CHB1 through a current limiting resistor R6, and pin 8 of the data buffer generator U1 is connected to the fourth PWM input signal HRTIMI_CHB2 through a current limiting resistor R7.

[0059] Correspondingly, the pin 18 of the data buffer generator U1 is connected to the optical transmitter FC1 through the current limiting resistor R8, the pin 16 of the data buffer generator U1 is connected to the optical transmitter FC2 through the current limiting resistor R9, the pin 14 of the data buffer generator U1 is connected to the optical transmitter FC3 through the current limiting resistor R10, and the pin 12 of the data buffer generator U1 is connected to the optical transmitter FC4 through the current limiting resistor R11. The pins 1 of the four optical transmitters are all connected to the power supply.

[0060] The data buffer generator U1 also includes an enable pin 1 and an enable pin 19. The enable pin 1 and the enable pin 19 are connected to the first electrode terminal of the power semiconductor device Q1 (switch circuit), and the enable pin 1 and the enable pin 19 are also connected to the power supply through the pull-up resistor R3 (pull-up circuit). The second electrode terminal of the power semiconductor device Q1 is grounded, and the control terminal of the power semiconductor device Q1 is connected to the enable signal ENN through the current limiting resistor R1. In a further implementation, a pull-down resistor R2 is also connected between the control terminal of the power semiconductor device Q1 and the second electrode terminal of the power semiconductor device Q1, which is conducive to the conduction or disconnection of the power semiconductor device Q1.

[0061] The power semiconductor device Q1 includes but is not limited to a MOS tube and an IGBT. In the figure, a MOS tube is used, the drain of the MOS tube is the first electrode terminal, the source of the MOS tube is the second electrode terminal, and the gate of the MOS tube is the control terminal.

[0062] The data buffer generator U1 further includes a power pin 20 and a ground pin 10 , wherein the power pin 20 is connected to a power source and the ground pin 10 is grounded.

[0063] The working principle of the data buffer generator U1 is that when the enable signal ENN is at a high level, the power semiconductor device Q1 is turned on, and the 1 and 19 enable pins of the data buffer generator U1 are at a low level, thereby making the output of the data buffer generator U1 valid. Otherwise, 1 and 19 of the data buffer generator U1 are kept at a high level through the pull-up resistor R3, and the output is in high-impedance mode.

[0064] It should be noted that the preferred embodiments of the present application are given in the specification and drawings of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described in the specification. These embodiments are not used as additional limitations on the content of the present application. The purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. In addition, the above-mentioned technical features continue to be combined with each other to form various embodiments not listed above, which are all regarded as the scope of the description of the present application; further, for ordinary technicians in this field, they can be improved or transformed according to the above description, and all these improvements and transformations should belong to the scope of protection of the claims attached to the present application.

Claims

1. An adjustable pulse generator for power semiconductor drive testing, characterized in that: The adjustable pulse generator comprises an input unit, a control unit and a driving circuit; The input unit is used to receive a PWM signal parameter value input by a user; The control unit is used to output a PWM signal with a preset frequency and a preset duty cycle based on a PWM signal parameter value input by a user; The driving circuit is used to modulate the PWM signal output by the control unit to drive the power semiconductor device to be tested; The driving circuit is connected to the power semiconductor device to be tested by using an optical fiber; The driving circuit includes a data buffer generator and an optical transmitter; The data buffer generator is used to receive the PWM signal output by the control unit and modulate the received PWM signal; The optical transmitter is used to output the modulated signal generated by the data buffer generator to the power semiconductor device to be tested.

2. The adjustable pulse generator according to claim 1, characterized in that: The PWM signal parameters include a frequency division coefficient and a comparison value.

3. The adjustable pulse generator according to claim 1, characterized in that: The data buffer generator includes a multi-channel signal input pin and a multi-channel signal output pin, and the optical transmitter includes a multi-channel optical transmitter; The multi-channel signal input pin is used to receive the multi-channel PWM signals output by the control unit; The multi-channel signal output pins are connected to the multi-channel optical transmitters in a one-to-one correspondence to output the multi-channel modulated signals generated by the data buffer generator to the power semiconductor device to be tested.

4. The adjustable pulse generator according to claim 1, characterized in that: The data buffer generator includes an enable pin; The enable pin is configured to enable the output of the data buffer generator when receiving a first level signal, and to enable the output of the data buffer generator to be in a high impedance mode when receiving a second level signal.

5. The adjustable pulse generator according to claim 4, characterized in that: Also included is a level signal generating circuit; The level signal generating circuit is configured to receive an enable signal to generate the first level signal or the second level signal.

6. The adjustable pulse generator according to claim 5, characterized in that: The level signal generating circuit includes a switch circuit and a pull-up circuit; The first electrode terminal of the switch circuit is connected to one end of the pull-up circuit and the enable pin, the second electrode terminal of the switch circuit is grounded, the control end of the switch circuit is used to receive an enable signal, and the other end of the pull-up circuit is connected to a power supply voltage.

7. The adjustable pulse generator according to claim 1, characterized in that: It also includes a display unit connected to the control unit, and the display unit is used to display one of the following: a PWM signal parameter value, a PWM signal frequency, and a PWM signal duty cycle.

8. The adjustable pulse generator according to claim 1, characterized in that: It also includes a power supply circuit and a voltage regulating circuit; The power supply circuit is used to provide a power supply voltage; The voltage regulating circuit is used to regulate the power supply voltage provided by the power supply circuit, and output the regulated voltage to supply power to the control unit and the drive circuit.

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