Thyristor trigger circuit
By designing a thyristor trigger circuit including oscillation circuit, signal combination circuit and trigger pulse circuit, the problem of high volume and cost of pulse transformer caused by trigger pulses in the same grid frequency is solved, and efficient triggering without occupancy of processor resources is achieved, reducing losses and improving product reliability.
Patent Information
- Application Number
- CN202421231704.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Priority Date
- 2024-05-29
- Filing Date
- 2024-05-31
- Publication Date
- 2025-02-28
- Estimated Expiration
- 2034-05-31
AI Technical Summary
Using trigger pulses with the same grid frequency will lead to the pulse transformer volume, cost, large space, high loss, and occupy processor resources, affecting other processor operations.
A thyristor trigger circuit is designed, including an oscillation circuit, a signal combination circuit and a trigger pulse circuit. Through the signal combination circuit, the trigger pulses emitted by the processor and the modulation waves output by the oscillation circuit are received, and then modulated and output to the thyristor to avoid occupying processor resources.
It realizes thyristor triggering that does not occupy processor resources, reduces the volume and cost of pulse transformers, reduces losses, and improves product reliability and market competitiveness.
Smart Images
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Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of thyristor triggering, in particular to a thyristor triggering circuit. Background Art
[0002] Thyristor devices are widely used in voltage regulating and rectifying devices, which are widely used in motor start and stop, industrial electric furnaces, mechanical equipment, glass industry, crystal growth, automobile industry, chemical industry, metal corrosion protection, charging and other industries; the reliability, safety, energy efficiency index and volume of related products are particularly important. Many manufacturers who develop and produce such devices are using various methods to reduce the volume of their products, improve the energy efficiency index of their products, and ensure that the reliability and safety of their products can be further improved, making their products more competitive in the market.
[0003] The opening of the thyristor requires a trigger signal to be sent to its gate. Currently, a trigger pulse with the grid frequency is used, or a modulation pulse with dozens or hundreds of times the grid frequency is given by occupying processor resources.
[0004] Using a trigger pulse frequency that is the same as the grid frequency will cause the pulse transformer to be larger, more expensive, occupy a large space, and have high losses; occupying processor resources to provide modulated pulses for triggering will consume more processor resources, increase processor costs, and may also affect other work of the processor. Utility Model Content
[0005] The utility model provides a thyristor trigger circuit to effectively solve the problem that the use of trigger pulses with the same power grid frequency will cause the pulse transformer to be bulky, high in cost, large in space and high in loss. At the same time, it does not occupy processor resources, avoids affecting other work of the processor, and improves the reliability of the product.
[0006] The embodiment of this specification discloses a thyristor trigger circuit, including:
[0007] Oscillator circuit;
[0008] A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor;
[0009] A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor;
[0010] Wherein, the trigger pulse circuit includes a resistor R1, a transistor Q1, a resistor R2, a diode D1, a diode D2 and a transformer T1, one end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1 and then connected to the external voltage terminal VDD, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
[0011] The embodiment of this specification also discloses a thyristor trigger circuit, including:
[0012] Oscillator circuit;
[0013] A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor;
[0014] A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor;
[0015] The trigger pulse circuit includes a resistor R1, a limiting subcircuit, a resistor R2, a diode D1, a diode D2 and a transformer T1, one end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the input end of the limiting subcircuit, the output end of the limiting subcircuit is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
[0016] In some embodiments of the present specification, the limiting subcircuit includes a capacitor C4, a capacitor C5, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a variable resistor R26, a variable resistor R27, an operational amplifier IC5, a transistor VT5, a transistor VT1, a transistor VT2, a power supply V1, a power supply V3 and a voltage terminal V2, the other end of the resistor R1 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the in-phase terminal of the operational amplifier IC5, one end of the capacitor C4 and one end of the resistor R22, the other end of the capacitor C4 is connected to the other end of the resistor R22 and the positive electrode of the power supply V1, one end of the resistor R19 is connected to the negative electrode of the power supply V1, the other end of the resistor R19 is connected to one end of the capacitor C5, the resistor R21 One end of the capacitor C5 is connected to the inverting end of the operational amplifier IC5, the other end of the capacitor C5 is connected to the other end of the resistor R21, the output end of the operational amplifier IC5, the emitter of the transistor VT1, the emitter of the transistor VT2 and the base of the transistor VT5, the collector of the transistor VT1 is connected to one end of the variable resistor R26, one end of the variable resistor R27 and the positive electrode of the power supply V3, the base of the transistor VT1 is connected to the sliding end of the variable resistor R26, the other end of the variable resistor R26 is connected to the other end of the variable resistor R27, the collector of the transistor VT2, the negative electrode of the power supply V3 and one end of the resistor R24 and then grounded, the base of the transistor VT2 is connected to the sliding end of the variable resistor R27, the collector of the transistor VT5 is connected to one end of the resistor R23, and the resistor R23 The other end of is connected to the voltage end V2, the other end of the resistor R24 is connected to the emitter of the transistor VT5, and then connected together to one end of the resistor R2 and the anode of the diode D1.
[0017] In some embodiments of the present specification, the oscillation circuit includes an oscillator chip U2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a capacitor C3. Pin 7 of the oscillator chip U2 is connected to one end of the resistor R3 and one end of the resistor R4. The other end of the resistor R3 is connected to the grounded capacitor C1, pin 4 and pin 8 of the oscillator chip U2 and then connected to an external voltage terminal VCC. Pin 6 of the oscillator chip U2 is connected to pin 2 and then connected to the other end of the resistor R4 and one end of the capacitor C2. The other end of the capacitor C2 is connected to pin 1 of the oscillator chip U2 and one end of the capacitor C3 and then grounded. The other end of the capacitor C3 is connected to pin 5 of the oscillator chip U2. Pin 3 of the oscillator chip U2 is connected to the input end of the signal combination circuit.
[0018] In some embodiments of this specification, the signal combination circuit is an AND gate chip or a NAND gate chip.
[0019] In some embodiments of this specification, the oscillator chip U2 is a 555 chip.
[0020] The embodiments of this specification can at least achieve the following beneficial effects:
[0021] The trigger pulse sent by the processor and the modulated wave output by the oscillation circuit are received through the signal combination circuit, and then output to the thyristor through the trigger pulse circuit after modulation, which does not occupy processor resources and avoids affecting other work of the processor. At the same time, it occupies a small space and has a low cost, and effectively solves the problem that the use of trigger pulses with the same power grid frequency will cause the pulse transformer to be large in size, high in cost, large in space and high in loss. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 Schematic diagram of a trigger pulse circuit involved in some embodiments of the present invention.
[0024] Figure 2 Schematic diagram of an oscillating circuit involved in some embodiments of the present invention.
[0025] Figure 3 Schematic diagram of a limiting subcircuit involved in some embodiments of the present utility model.
[0026] Figure 4 A schematic diagram of a modulated trigger pulse output by a processor involved in some embodiments of the present invention.
[0027] Figure 5 This is a schematic diagram of a non-modulated trigger pulse output by a processor involved in some embodiments of the present invention.
[0028] Figure 6 It is a schematic diagram of a trigger pulse modulated by a modulated wave (implemented by U1) involved in some embodiments of the present utility model.
[0029] Figure 7 It is a schematic diagram of a modulation wave from an oscillation circuit involved in some embodiments of the present invention. DETAILED DESCRIPTION
[0030] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the embodiments of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.
[0031] In the description of the embodiments of the present invention, it should be understood that the terms "length", "vertical", "horizontal", "top", "bottom", etc. indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present invention.
[0032] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present utility model, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.
[0033] In the embodiments of the present utility model, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present utility model can be understood according to specific circumstances.
[0034] In the embodiments of the present utility model, unless otherwise clearly specified and limited, the first feature being "above" or "below" the second feature may include the first and second features being in direct contact, or may include the first and second features not being in direct contact but being in contact through another feature between them. Moreover, the first feature being "above", "above" and "above" the second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. The first feature being "below", "below" and "below" the second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.
[0035] The disclosure below provides many different embodiments or examples for realizing different structures of the embodiments of the present utility model. In order to simplify the disclosure of the embodiments of the present utility model, the components and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the embodiments of the present utility model. In addition, the embodiments of the present utility model can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.
[0036] The embodiments of the present utility model are described in detail below with reference to the accompanying drawings.
[0037] The embodiment of this specification discloses a thyristor trigger circuit, including:
[0038] Oscillator circuit;
[0039] A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor;
[0040] A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor;
[0041] Among them, Figure 1 As shown, the trigger pulse circuit includes a resistor R1, a transistor Q1, a resistor R2, a diode D1, a diode D2 and a transformer T1, one end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1 and then connected to the external voltage terminal VDD, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
[0042] In this embodiment, the trigger pulse sent by the processor and the modulated wave output by the oscillation circuit are received by the signal combination circuit, and then modulated and output to the transistor Q1. The transistor Q1 is turned on, and the voltage output by the voltage terminal VDD is output to the thyristor through the transformer T1, thereby controlling the thyristor. The modulated trigger pulse output by the processor is as follows: Figure 4 As shown, the non-modulated trigger pulse output by the processor is as follows Figure 5 As shown, the trigger pulse modulated by the modulated wave (implemented by U1) is as follows Figure 6As shown, the modulation wave from the oscillation circuit is as follows Figure 7 shown.
[0043] The embodiment of this specification also discloses a thyristor trigger circuit, including:
[0044] Oscillator circuit;
[0045] A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor;
[0046] A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor;
[0047] The trigger pulse circuit includes a resistor R1, a limiting subcircuit (replacing the triode Q1 of the previous embodiment), a resistor R2, a diode D1, a diode D2 and a transformer T1. One end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the input end of the limiting subcircuit, the output end of the limiting subcircuit is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
[0048] In this embodiment, the specific process is similar to that of the previous embodiment, with the only difference being that a limiting subcircuit is used to replace the transistor Q1 of the previous embodiment, and that the voltage output from the voltage terminal VDD is not used to drive the thyristor, but a limiting subcircuit is used to control the magnitude of the driving voltage output to the thyristor.
[0049] In some embodiments, Figure 3As shown, the limiting subcircuit includes a capacitor C4, a capacitor C5, a resistor R19, a resistor R20, a resistor R21, a resistor R22, a resistor R23, a resistor R24, a variable resistor R26, a variable resistor R27, an operational amplifier IC5, a transistor VT5, a transistor VT1, a transistor VT2, a power supply V1, a power supply V3 and a voltage terminal V2, the other end of the resistor R1 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the in-phase terminal of the operational amplifier IC5, one end of the capacitor C4 and one end of the resistor R22, the other end of the capacitor C4 is connected to the other end of the resistor R22 and the positive electrode of the power supply V1, one end of the resistor R19 is connected to the negative electrode of the power supply V1, the other end of the resistor R19 is connected to one end of the capacitor C5, one end of the resistor R21 and The inverting end of the operational amplifier IC5 is connected, the other end of the capacitor C5 is connected to the other end of the resistor R21, the output end of the operational amplifier IC5, the emitter of the transistor VT1, the emitter of the transistor VT2 and the base of the transistor VT5, the collector of the transistor VT1 is connected to one end of the variable resistor R26, one end of the variable resistor R27 and the positive electrode of the power supply V3, the base of the transistor VT1 is connected to the sliding end of the variable resistor R26, the other end of the variable resistor R26 is connected to the other end of the variable resistor R27, the collector of the transistor VT2, the negative electrode of the power supply V3 and one end of the resistor R24 and then grounded, the base of the transistor VT2 is connected to the sliding end of the variable resistor R27, the collector of the transistor VT5 is connected to one end of the resistor R23, and the resistor R23 The other end of is connected to the voltage end V2, the other end of the resistor R24 is connected to the emitter of the transistor VT5, and then connected together to one end of the resistor R2 and the anode of the diode D1.
[0050] In this embodiment, when the output voltage U o3 Greater than the upper limit voltage U H When VT2's emitter junction is forward biased and turned on, VT's emitter junction is reverse biased and turned off, so U o3 Restricted to U H Value; when U o3 Slightly less than the lower limit voltage U L When VT2 is turned on and VT1 is turned off, the current is limited to U L Value; so U o3 Restricted to U L ~U H range, that is, the driving voltage of the thyristor is also limited within the corresponding range, so the thyristor can be controlled more accurately, that is, the control accuracy of the thyristor is improved.
[0051] In some embodiments, Figure 2As shown, the oscillation circuit includes an oscillator chip U2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a capacitor C3. Pin 7 of the oscillator chip U2 is connected to one end of the resistor R3 and one end of the resistor R4. The other end of the resistor R3 is connected to the grounded capacitor C1, pin 4 and pin 8 of the oscillator chip U2 and then connected to an external voltage terminal VCC. Pin 6 of the oscillator chip U2 is connected to pin 2 and then connected to the other end of the resistor R4 and one end of the capacitor C2. The other end of the capacitor C2 is connected to pin 1 of the oscillator chip U2 and one end of the capacitor C3 and then grounded. The other end of the capacitor C3 is connected to pin 5 of the oscillator chip U2. Pin 3 of the oscillator chip U2 is connected to the input end of the signal combination circuit.
[0052] In some embodiments, the signal combination circuit is an AND gate chip ( Figure 1 U1 in the circuit) or NAND gate chip. That is, pin 1 of U1 can be connected to the processor to receive pulses; pin 2 of U1 can be connected to pin 3 of the oscillator chip U2 to receive the modulated wave; after being modulated by U1, it is output to resistor R1 through pin 3 of U1.
[0053] In some embodiments, the oscillator chip U2 is a 555 chip.
[0054] The above embodiments describe multiple specific implementations of the present invention, but those skilled in the art should understand that various changes or modifications can be made to these implementations without departing from the principles and essence of the present invention, but these changes and modifications are all within the scope of protection of the present invention.
Claims
1. A thyristor trigger circuit, characterized in that: include: Oscillator circuit; A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor; A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor; Wherein, the trigger pulse circuit includes a resistor R1, a transistor Q1, a resistor R2, a diode D1, a diode D2 and a transformer T1, one end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the base of the transistor Q1, the emitter of the transistor Q1 is grounded, the collector of the transistor Q1 is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1 and then connected to the external voltage terminal VDD, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
2. The thyristor trigger circuit according to claim 1, characterized in that: The signal combination circuit is an AND gate chip or a NAND gate chip.
3. The thyristor trigger circuit according to claim 1, characterized in that: The oscillation circuit includes an oscillator chip U2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a capacitor C3. Pin 7 of the oscillator chip U2 is connected to one end of the resistor R3 and one end of the resistor R4. The other end of the resistor R3 is connected to the grounded capacitor C1, pins 4 and 8 of the oscillator chip U2 and then connected to an external voltage terminal VCC. Pin 6 of the oscillator chip U2 is connected to pin 2 and then connected to the other end of the resistor R4 and one end of the capacitor C2. The other end of the capacitor C2 is connected to pin 1 of the oscillator chip U2 and one end of the capacitor C3 and then grounded. The other end of the capacitor C3 is connected to pin 5 of the oscillator chip U2. Pin 3 of the oscillator chip U2 is connected to the input end of the signal combination circuit.
4. The thyristor trigger circuit according to claim 3, characterized in that: The oscillator chip U2 is a 555 chip.
5. A thyristor trigger circuit, characterized in that: include: Oscillator circuit; A signal combination circuit is connected to the oscillation circuit and receives a trigger pulse sent by the processor; A trigger pulse circuit, whose input end is connected to the output end of the signal combination circuit, and whose output end is connected to the thyristor; The trigger pulse circuit includes a resistor R1, a limiting subcircuit, a resistor R2, a diode D1, a diode D2 and a transformer T1, one end of the resistor R1 is connected to the output end of the signal combination circuit, the other end of the resistor R1 is connected to the input end of the limiting subcircuit, the output end of the limiting subcircuit is connected to one end of the resistor R2 and the positive electrode of the diode D1, the negative electrode of the diode D1 is connected to the pin 5 of the transformer T1, the other end of the resistor R2 is connected to the pin 1 of the transformer T1, the pin 10 of the transformer T1 is connected to the positive electrode of the diode D2, the negative electrode of the diode D2 is connected to the G electrode of the thyristor, the pin 6 of the transformer T1 is connected to the K electrode of the thyristor, the pin 1 and the pin 5 of the transformer T1 are the primary side, and the pin 6 and the pin 10 of the transformer T1 are the secondary side.
6. The thyristor trigger circuit according to claim 5, characterized in that: The signal combination circuit is an AND gate chip or a NAND gate chip.
7. The thyristor trigger circuit according to claim 5, characterized in that: The amplitude limiting subcircuit includes capacitor C4, capacitor C5, resistor R19, resistor R20, resistor R21, resistor R22, resistor R23, resistor R24, variable resistor R26, variable resistor R27, operational amplifier IC5, transistor VT5, transistor VT1, transistor VT2, power supply V1, power supply V3 and voltage terminal V2, the other end of the resistor R1 is connected to one end of the resistor R20, the other end of the resistor R20 is connected to the in-phase terminal of the operational amplifier IC5, one end of the capacitor C4 and one end of the resistor R22, the other end of the capacitor C4 is connected to the other end of the resistor R22 and the positive electrode of the power supply V1, one end of the resistor R19 is connected to the negative electrode of the power supply V1, the other end of the resistor R19 is connected to one end of the capacitor C5, one end of the resistor R21 and the operational amplifier The inverting end of IC5 is connected, the other end of the capacitor C5 is connected to the other end of the resistor R21, the output end of the operational amplifier IC5, the emitter of the transistor VT1, the emitter of the transistor VT2 and the base of the transistor VT5, the collector of the transistor VT1 is connected to one end of the variable resistor R26, one end of the variable resistor R27 and the positive electrode of the power supply V3, the base of the transistor VT1 is connected to the sliding end of the variable resistor R26, the other end of the variable resistor R26 is connected to the other end of the variable resistor R27, the collector of the transistor VT2, the negative electrode of the power supply V3 and one end of the resistor R24 and then grounded, the base of the transistor VT2 is connected to the sliding end of the variable resistor R27, the collector of the transistor VT5 is connected to one end of the resistor R23, and the resistor R23 The other end of is connected to the voltage end V2, the other end of the resistor R24 is connected to the emitter of the transistor VT5, and then connected together to one end of the resistor R2 and the anode of the diode D1.
8. The thyristor trigger circuit according to claim 5, characterized in that: The oscillation circuit includes an oscillator chip U2, a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a capacitor C3. Pin 7 of the oscillator chip U2 is connected to one end of the resistor R3 and one end of the resistor R4. The other end of the resistor R3 is connected to the grounded capacitor C1, pins 4 and 8 of the oscillator chip U2 and then connected to an external voltage terminal VCC. Pin 6 of the oscillator chip U2 is connected to pin 2 and then connected to the other end of the resistor R4 and one end of the capacitor C2. The other end of the capacitor C2 is connected to pin 1 of the oscillator chip U2 and one end of the capacitor C3 and then grounded. The other end of the capacitor C3 is connected to pin 5 of the oscillator chip U2. Pin 3 of the oscillator chip U2 is connected to the input end of the signal combination circuit.
9. The thyristor trigger circuit according to claim 8, characterized in that: The oscillator chip U2 is a 555 chip.