Array substrate and display panel

Abstract

According to the array substrate and the display panel, in the direction perpendicular to the extending direction of a data line, an extending part extends to the position between two adjacent pixel electrodes, and the shortest distance between the extending part and a connecting line is larger than 0 micrometer; in the extending direction of the data line, the shortest distance between the extending part and the connecting line is larger than or equal to 0 micrometer. In other words, in the area between the two pixel electrodes, the connecting line is arranged on the periphery of the extending part, the connecting line and the end of the extending part are prevented from being overlapped, and then the risk that the connecting line is broken is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] At present, due to the use of data line sharing (DLS) design in multiple products of liquid crystal displays, pixel electrodes need to be connected through cross-pixel connection lines to achieve electrical signal transmission, so the flatness of the film layer under the pixel electrode is required to be higher. Since the terrain under the pixel electrode is composed of an organic insulating film layer, a color resist overlap, a first metal edge, and a second metal edge. Among them, the color resist overlap is located between two adjacent pixel electrodes, outside the edge of the second metal layer, and the terrain of the organic insulating layer is flat and the film thickness is relatively uniform; while the cross-pixel connection line overlaps the edge of the second metal layer, and there is a horn of color resist overlap above the edge of the second metal layer, which makes the terrain under the cross-pixel connection line higher, and the film layer of the organic insulating film at this location is thin, resulting in uneven cross-pixel connection lines at the thin position of the organic insulating film. After the high-temperature process, the cross-pixel connection line is easy to break at the edge of the second metal layer, and the signal cannot be transmitted, resulting in dark spots on the display. Utility Model Content

[0003] The embodiments of the present application provide an array substrate and a display panel, which can reduce the risk of cross-pixel connection lines being broken.

[0004] The present invention provides an array substrate, which includes

[0005] A first metal layer includes a common electrode and a gate line arranged at intervals;

[0006] a second metal layer, which is arranged in a different layer from the first metal layer, the second metal layer includes a data line, an output electrode of a thin film transistor and an extension portion, the output electrode of the thin film transistor is connected to the extension portion, the data line is connected to an input electrode of the thin film transistor, and in a top view of the array substrate, the extension portion is arranged to overlap with the common electrode;

[0007] a pixel electrode layer, which is arranged in a different layer from the second metal layer, the pixel electrode layer comprising connected pixel electrodes and connecting lines, the connecting lines being connected to the output electrode of the thin film transistor;

[0008] In the top view of the array substrate, in a direction perpendicular to the extension direction of the data line, the extension portion extends between two adjacent pixel electrodes, and the shortest distance between the extension portion and the connecting line is greater than 0 microns; in the extension direction along the data line, the shortest distance between the extension portion and the connecting line is greater than or equal to 0 microns.

[0009] Optionally, in some embodiments of the present application, the connecting line includes a via portion, a first portion, and a second portion connected in sequence, the via portion is overlapped and connected to the output electrode of the thin film transistor, the first portion is located on a side of the extension portion close to the gate line, the second portion is located on a side of the extension portion away from the output electrode of the thin film transistor, and the second portion is connected to the pixel electrode;

[0010] In the top view of the array substrate, in the extension direction along the data line, the shortest distance between the extension portion and the first portion is greater than or equal to 0 microns, and in the direction perpendicular to the extension direction of the data line, the shortest distance between the extension portion and the second portion is greater than 0 microns.

[0011] Optionally, in some embodiments of the present application, the second portion includes a first segment and a second segment connected to each other, the first segment is connected to the first portion, and the second segment is connected to the pixel electrode;

[0012] In a top view of the array substrate, an extension direction of the first portion intersects with an extension direction of the first segment and an extension direction of the second segment, respectively, and an extension direction of the first segment intersects with an extension direction of the second segment.

[0013] Optionally, in some embodiments of the present application, the extension direction of the first part is parallel to the extension direction of the extension part, the extension direction of the first segment is perpendicular to the extension direction of the first part, and the extension direction of the second segment is non-perpendicular to the extension direction of the first segment.

[0014] Optionally, in some embodiments of the present application, the second portion includes a first segment, a second segment and a third segment connected in sequence, the first segment is connected to the first portion, and the third segment is connected to the pixel electrode;

[0015] In the top view of the array substrate, the extension direction of the first portion intersects with the extension direction of the first segment and the extension direction of the third segment, and the extension direction of the first segment intersects with the extension direction of the second segment and the extension direction of the third segment.

[0016] Optionally, in some embodiments of the present application, the extension direction of the first portion and the extension direction of the second portion are both parallel to the extension direction of the extension portion, the extension direction of the first portion is perpendicular to the extension direction of the first portion, and the extension direction of the third portion is non-perpendicular to the extension direction of the second portion.

[0017] Optionally, in some embodiments of the present application, in a top view of the array substrate, an extension direction of the first portion is non-perpendicular to an extension direction of the second portion, and an extension direction of the first portion is parallel to an extension direction of the extension portion.

[0018] Optionally, in some embodiments of the present application, the array substrate further includes a substrate, a dielectric layer, a color resist layer and an organic insulating layer, the first metal layer is arranged on the substrate, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on a side of the dielectric layer away from the substrate, the color resist layer is arranged on a side of the second metal layer away from the substrate, the organic insulating layer covers the color resist layer, and the pixel electrode layer is arranged on a side of the organic insulating layer away from the color resist layer;

[0019] The color resist layer includes a plurality of color resist blocks, one of the color resist blocks is arranged corresponding to one of the pixel electrodes, and in a direction perpendicular to the surface of the substrate, edge portions of two adjacent color resist blocks are overlapped and both overlap with an end of the extension portion away from the output electrode of the thin film transistor.

[0020] Optionally, in some embodiments of the present application, in a top view of the array substrate, in the extension direction along the data line, the shortest distance between the extension portion and the first portion is greater than 0 microns, and in the direction perpendicular to the extension direction of the data line, the shortest distance between the extension portion and the second portion is greater than or equal to 1.5 microns.

[0021] Optionally, in some embodiments of the present application, in a top view of the array substrate, the first portion and the second portion are both arranged to overlap with a portion of the common electrode.

[0022] Optionally, in some embodiments of the present application, in a top view of the array substrate, a connection between the first portion and the second portion is chamfered.

[0023] Correspondingly, an embodiment of the present application further provides a display panel, which includes an opposing substrate and an array substrate as described in any one of the above embodiments, wherein the opposing substrate is arranged opposite to the array substrate.

[0024] In the array substrate of the embodiment of the present application, in the top view of the array substrate, in the direction perpendicular to the extension direction of the data line, the extension portion extends between two adjacent pixel electrodes, and the shortest distance between the extension portion and the connecting line is greater than 0 microns; in the extension direction along the data line, the shortest distance between the extension portion and the connecting line is greater than or equal to 0 microns. In other words, in the area between the two pixel electrodes, the connecting line is arranged at the periphery of the extension portion, so as to avoid the connection line and the end of the extension portion from overlapping, thereby reducing the risk of the connecting line breaking. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a schematic diagram of a top view of the structure of an array substrate provided in an embodiment of the present application;

[0026] Figure 2 yes Figure 1 A magnified view of part B;

[0027] Figure 3 yes Figure 1 Schematic diagram of the cross-sectional structure along line AA;

[0028] Figure 4 is another schematic diagram of a top view of the structure of the array substrate provided in an embodiment of the present application;

[0029] Figure 5 yes Figure 4 Enlarged view of part C;

[0030] Figure 6 is another schematic diagram of a top view of the array substrate provided in an embodiment of the present application;

[0031] Figure 7 yes Figure 6 A magnified view of part D in the middle;

[0032] Figure 8 It is a schematic diagram of the structure of the display panel provided in the embodiment of the present application. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application. In addition, it should be understood that the specific implementation methods described herein are only used to illustrate and explain the present application, and are not used to limit the present application. In the present application, unless otherwise stated, the directional words used, such as "upper" and "lower", generally refer to the upper and lower parts of the device in actual use or working state, specifically the drawing direction in the drawings; while "inside" and "outside" refer to the outline of the device; the terms "first", "second", "third", etc. are used only as markings, and no numerical requirements are imposed or order is established.

[0034] The embodiments of the present application provide an array substrate and a display panel, which are described in detail below. It should be noted that the description order of the following embodiments is not intended to limit the preferred order of the embodiments.

[0035] Please refer to Figure 1 and Figure 2 , an embodiment of the present application provides an array substrate 100, which includes a first metal layer m1, a second metal layer m2 and a pixel electrode layer pix.

[0036] The first metal layer m1 includes a common electrode m11 and a gate line m12 that are spaced apart.

[0037] The second metal layer m2 is arranged in a different layer from the first metal layer m1. The second metal layer m2 includes a data line m21, an output electrode m22 of the thin film transistor tft, and an extension m23. The output electrode m22 of the thin film transistor tft is connected to the extension m23. The data line m21 is connected to the input electrode of the thin film transistor tft. In the top view of the array substrate 100 ( Figure 1 ), the extension portion m23 is arranged to overlap with the common electrode m11.

[0038] The pixel electrode layer pix is ​​arranged in a different layer from the second metal layer m2. The pixel electrode layer pix includes a connected pixel electrode p1 and a connecting line p2, and the connecting line p2 is connected to an output electrode m22 of the thin film transistor tft.

[0039] In the top view of the array substrate 100, in the direction x perpendicular to the extension direction y of the data line m21, the extension portion m23 extends between two adjacent pixel electrodes p1, and the shortest distance d1 between the extension portion m23 and the connecting line p2 is greater than 0 microns; in the extension direction y along the data line m21, the shortest distance d2 between the extension portion m23 and the connecting line p2 is greater than or equal to 0 microns.

[0040] In the array substrate of the embodiment of the present application, in the area between the two pixel electrodes pix, the connecting line p2 is arranged on the periphery of the extending portion m23 to avoid overlapping of the ends of the connecting line p2 and the extending portion m23, thereby reducing the risk of breaking the connecting line p2.

[0041] Optionally, the gate of the thin film transistor tft is connected to the gate line m12. The thin film transistor tft may be a top gate type, a bottom gate type, or a double gate type. The embodiment of the present application is described by taking a bottom gate thin film transistor as an example, but is not limited thereto.

[0042] Optionally, two gate lines m12 are provided in two adjacent rows of pixel electrodes p1, one gate line m12 is used to connect part of the pixel electrodes p1 in one row, and the other gate line m12 is used to connect part of the pixel electrodes p1 in another row. The common electrode m11 is located at opposite sides of the two gate lines m12.

[0043] In two adjacent columns of pixel electrodes p1, the first thin film transistor is arranged in the area of ​​the first column of pixel electrodes p1, and the second thin film transistor is arranged in the area of ​​the second column of pixel electrodes p1. A first thin film transistor is connected to a pixel electrode p1 in the second column through a connecting line p2, and a second thin film transistor is connected to a pixel electrode p1 in the first column through another connecting line p2.

[0044] Optional, see Figure 3, the array substrate 100 further includes a substrate 11, a dielectric layer 12, a color resist layer 13 and an organic insulating layer 14. The first metal layer m1 is disposed on the substrate 11. The dielectric layer 12 covers the first metal layer m1 and the substrate 11. The second metal layer m2 is disposed on a side of the dielectric layer 12 away from the substrate 11. The color resist layer 13 is disposed on a side of the second metal layer m2 away from the substrate 11. The organic insulating layer 14 covers the color resist layer 13. The pixel electrode layer pix is ​​disposed on a side of the organic insulating layer 14 away from the color resist layer 13. The color resist layer 13 includes a plurality of color resist blocks 131, and one color resist block 131 is disposed corresponding to one pixel electrode p1. In the direction h perpendicular to the plate surface of the substrate 11, the edge portions of two adjacent color resist blocks 131 are overlapped and both overlap with an end of the extension portion m23 away from the output electrode m22 of the thin film transistor tft.

[0045] Optionally, the color resist block 131 includes a red color resist block, a green color resist block and a blue color resist block.

[0046] In some embodiments, the color resist layer 13 may also be disposed on the color filter substrate side.

[0047] In one embodiment of the present application, the connecting line p2 includes a via portion p21, a first portion p22, and a second portion p23 connected in sequence. The via portion p21 overlaps and is connected to the output electrode m22 of the thin film transistor TFT. The first portion p22 is located on a side of the extension portion m23 close to the gate line m12. The second portion p23 is located on a side of the extension portion m23 away from the output electrode m22 of the thin film transistor TFT. The second portion p23 is connected to the pixel electrode p1.

[0048] In the top view of the array substrate 100, in the extension direction y along the data line m21, the shortest distance d2 between the extension portion m23 and the first portion p22 is greater than or equal to 0 microns; in the direction x perpendicular to the extension direction y of the data line m21, the shortest distance d1 between the extension portion m23 and the second portion p23 is greater than 0 microns.

[0049] Among them, since the color-resist block 131 overlaps in the direction x perpendicular to the extension direction y of the data line m21, the flatness of the extension portion m23 in the extension direction y of the data line m21 is less affected, so the shortest distance d2 between the extension portion m23 and the first portion p22 is greater than or equal to 0 micrometers. The greater the shortest distance d1 between the extension portion m23 and the second portion p23, the lower the risk of the connection line p2 breaking.

[0050] Optionally, the shortest distance d2 between the extending portion m23 and the first portion p22 may be smaller than the shortest distance d1 between the extending portion m23 and the second portion p23.

[0051] In one embodiment of the present application, in a top view of the array substrate 100, in the extension direction y along the data line m21, the shortest distance d2 between the extension portion m23 and the first portion p22 is greater than 0 microns, and in the direction x perpendicular to the extension direction y of the data line m21, the shortest distance d1 between the extension portion m23 and the second portion p23 is greater than or equal to 1.5 microns.

[0052] Among them, the shortest distance d2 between the extension portion m23 and the first portion p22 is greater than 0 microns to ensure that the extension portion m23 and the first portion p22 do not overlap, reducing the risk of breakage of the first portion p22; the shortest distance d1 between the extension portion m23 and the second portion p23 is greater than or equal to 1.5 microns to further reduce the risk of breakage of the second portion p23.

[0053] Optionally, the shortest distance d2 between the extension portion m23 and the first portion p22 can be 0.1 microns, 0.2 microns, 0.3 microns, 0.4 microns, 0.5 microns, 0.6 microns, 0.7 microns, 0.8 microns, 0.9 microns, 1 micron, 1.1 microns, 1.2 microns, 1.3 microns, 1.4 microns, 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns or 2 microns, etc.

[0054] The shortest distance d1 between the extension portion m23 and the second portion p23 may be 1.5 microns, 1.6 microns, 1.7 microns, 1.8 microns, 1.9 microns, 2 microns, 2.1 microns, 2.2 microns, 2.3 microns, 2.4 microns, 2.5 microns, 2.6 microns, 2.7 microns, 2.8 microns, 2.9 microns or 3 microns, etc.

[0055] Optionally, the second portion p23 includes a first segment 231 and a second segment 232 which are connected to each other, the first segment 231 is connected to the first portion p22, and the second segment 232 is connected to the pixel electrode p1.

[0056] In the top view of the array substrate 100 , the extension direction of the first portion p22 intersects with the extension direction of the first section 231 and the extension direction of the second section 232 , and the extension direction of the first section 231 intersects with the extension direction of the second section 232 .

[0057] In the top view of the array substrate 100 , in the direction x perpendicular to the extending direction y of the data line m21 , the shortest distance d1 between the extending portion m23 and the first segment 231 is greater than or equal to 1.5 micrometers.

[0058] Optionally, the extension direction of the first portion p22 is parallel to the extension direction of the extension portion m23 , the extension direction of the first segment 231 is perpendicular to the extension direction of the first portion p22 , and the extension direction of the second segment 232 is non-perpendicular to the extension direction of the first segment 231 .

[0059] The extending direction of the first portion p22 is parallel to the extending direction of the extending portion m23 , so as to save the layout space of the first portion p22 and increase the overlapping area between the first portion p22 and the common electrode p11 .

[0060] Optionally, in the top view of the array substrate 100 , the first portion p22 and the second portion p23 are both partially overlapped with the common electrode m11 to form a storage capacitor.

[0061] Optionally, in the top view of the array substrate 100 , the connection between the first portion p22 and the second portion p23 is rounded to reduce the risk of corner discharge.

[0062] Optionally, in an embodiment of the present application, the pixel electrode layer pix further includes a first shielding electrode p3 and a second shielding electrode p4, the first shielding electrode p3 covers the data line m21, the second shielding electrode p4 is connected to two adjacent first shielding electrodes p3 and is arranged between two adjacent rows of pixel electrodes p1. The second shielding electrode p4 covers part of the gate line m12.

[0063] Please refer to Figure 4-5 Compared with the array substrate 100 of the above-mentioned embodiment, the difference of the array substrate 100 in one embodiment of the present application is that the second part p23 includes a first section 231, a second section 232 and a third section 233 connected in sequence, the first section 231 is connected to the first part p22, and the third section 233 is connected to the pixel electrode p1.

[0064] In the top view of the array substrate 100 ( Figure 4 ), the extension direction of the first portion p22 intersects with the extension direction of the first segment 231 and the extension direction of the third segment 233, respectively, and the extension direction of the first segment 231 intersects with the extension direction of the second segment 232 and the extension direction of the third segment 233, respectively.

[0065] Optionally, the extension direction of the first portion p22 and the extension direction of the second portion 232 are both parallel to the extension direction of the extension portion m23, the extension direction of the first portion 231 is perpendicular to the extension direction of the first portion p22, and the extension direction of the third portion 233 is non-perpendicular to the extension direction of the second portion 232.

[0066] In the top view of the array substrate 100, in the extension direction y along the data line m21, the shortest distance d2 between the extension portion m23 and the first portion p22 is greater than 0 microns, and in the direction x perpendicular to the extension direction y of the data line m21, the shortest distance d1 between the extension portion m23 and the first section 231 is greater than or equal to 1.5 microns.

[0067] The second portion p23 is of three-segment type, which increases the overlapping area between the second portion p23 and the common electrode m11 , that is, the second segment 232 and the third segment 233 are overlapped with the common electrode m11 to increase the storage capacitance.

[0068] Please refer to Figure 6-7 Compared with the array substrate 100 of the above-mentioned embodiment, the difference of the array substrate 100 of one embodiment of the present application is that in the top view ( Figure 6 ), the extension direction of the first portion p22 is not perpendicular to the extension direction of the second portion p23, and the extension direction of the first portion p22 is parallel to the extension direction of the extension portion m23.

[0069] That is, the second portion p23 extends along a single direction, and the second portion p23 adopts a one-stage structure, which simplifies the structure of the connecting line p2.

[0070] Please refer to Figure 8 Accordingly, an embodiment of the present application further provides a display panel 1000 , which includes an opposing substrate 200 and an array substrate 100 as described in any one of the above embodiments, and the opposing substrate 200 is arranged opposite to the array substrate 100 .

[0071] It should be noted that the structure of the array substrate 100 of the display panel 1000 of the embodiment of the present application is similar to or the same as the structure of the array substrate 100 of any of the above embodiments, and therefore will not be described in detail herein.

[0072] In the array substrate 100 of the display panel 1000 of the embodiment of the present application, in the top view of the array substrate 100, in the direction perpendicular to the extension direction of the data line m21, the extension part m23 extends between two adjacent pixel electrodes p1, and the shortest distance between the extension part m23 and the connecting line p2 is greater than 0 microns; in the extension direction along the data line m21, the shortest distance between the extension part m23 and the connecting line p2 is greater than or equal to 0 microns. In other words, in the area between the two pixel electrodes p1, the connecting line p2 is arranged at the periphery of the extension part m23, so as to avoid the connection line p2 and the end of the extension part m23 overlapping, thereby reducing the risk of the connecting line p2 breaking.

[0073] The above is a detailed introduction to an array substrate and a display panel provided in an embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An array substrate, characterized in that: include: A first metal layer includes a common electrode and a gate line arranged at intervals; a second metal layer, which is disposed in a different layer from the first metal layer, the second metal layer comprising a data line, an output electrode of a thin film transistor and an extension portion, the output electrode of the thin film transistor is connected to the extension portion, the data line is connected to an input electrode of the thin film transistor, and in a top view of the array substrate, the extension portion is overlapped with the common electrode; and a pixel electrode layer, which is arranged in a different layer from the second metal layer, the pixel electrode layer comprising connected pixel electrodes and connecting lines, the connecting lines being connected to the output electrode of the thin film transistor; In the top view of the array substrate, in a direction perpendicular to the extension direction of the data line, the extension portion extends between two adjacent pixel electrodes, and the shortest distance between the extension portion and the connecting line is greater than 0 microns; in the extension direction along the data line, the shortest distance between the extension portion and the connecting line is greater than or equal to 0 microns.

2. The array substrate according to claim 1, characterized in that: The connecting line comprises a via portion, a first portion, and a second portion which are connected in sequence, the via portion is overlapped and connected to the output electrode of the thin film transistor, the first portion is located on a side of the extension portion close to the gate line, the second portion is located on a side of the extension portion far from the output electrode of the thin film transistor, and the second portion is connected to the pixel electrode; In the top view of the array substrate, in the extension direction along the data line, the shortest distance between the extension portion and the first portion is greater than or equal to 0 microns, and in the direction perpendicular to the extension direction of the data line, the shortest distance between the extension portion and the second portion is greater than 0 microns.

3. The array substrate according to claim 2, characterized in that: The second portion includes a first segment and a second segment connected to each other, the first segment is connected to the first portion, and the second segment is connected to the pixel electrode; In a top view of the array substrate, an extension direction of the first portion intersects with an extension direction of the first segment and an extension direction of the second segment, respectively, and an extension direction of the first segment intersects with an extension direction of the second segment.

4. The array substrate according to claim 3, characterized in that: The extension direction of the first portion is parallel to the extension direction of the extension portion, the extension direction of the first section is perpendicular to the extension direction of the first portion, and the extension direction of the second section is non-perpendicular to the extension direction of the first section.

5. The array substrate according to claim 2, characterized in that: The second portion includes a first segment, a second segment and a third segment connected in sequence, the first segment is connected to the first portion, and the third segment is connected to the pixel electrode; In the top view of the array substrate, the extension direction of the first portion intersects with the extension direction of the first segment and the extension direction of the third segment, and the extension direction of the first segment intersects with the extension direction of the second segment and the extension direction of the third segment.

6. The array substrate according to claim 5, characterized in that: The extension direction of the first portion and the extension direction of the second segment are both parallel to the extension direction of the extension portion, the extension direction of the first segment is perpendicular to the extension direction of the first portion, and the extension direction of the third segment is non-perpendicular to the extension direction of the second segment.

7. The array substrate according to claim 2, characterized in that: In a top view of the array substrate, an extension direction of the first portion is non-perpendicular to an extension direction of the second portion, and the extension direction of the first portion is parallel to an extension direction of the extension portion.

8. The array substrate according to any one of claims 2 to 7, characterized in that: The array substrate further comprises a substrate, a dielectric layer, a color resist layer and an organic insulating layer, wherein the first metal layer is arranged on the substrate, the dielectric layer covers the first metal layer and the substrate, the second metal layer is arranged on a side of the dielectric layer away from the substrate, the color resist layer is arranged on a side of the second metal layer away from the substrate, the organic insulating layer covers the color resist layer, and the pixel electrode layer is arranged on a side of the organic insulating layer away from the color resist layer; The color resist layer includes a plurality of color resist blocks, one of the color resist blocks is arranged corresponding to one of the pixel electrodes, and in a direction perpendicular to the surface of the substrate, edge portions of two adjacent color resist blocks are overlapped and both overlap with an end of the extension portion away from the output electrode of the thin film transistor.

9. The array substrate according to claim 8, characterized in that: In the top view of the array substrate, in the extension direction along the data line, the shortest distance between the extension portion and the first portion is greater than 0 microns, and in the direction perpendicular to the extension direction of the data line, the shortest distance between the extension portion and the second portion is greater than or equal to 1.5 microns.

10. The array substrate according to any one of claims 2 to 7, characterized in that: In a top view of the array substrate, both the first portion and the second portion are partially overlapped with the common electrode.

11. The array substrate according to any one of claims 2 to 7, characterized in that: In a top view of the array substrate, a connection between the first portion and the second portion is provided with a rounded corner.

12. A display panel, characterized in that: It comprises an opposing substrate and an array substrate as claimed in any one of claims 1 to 11, wherein the opposing substrate is arranged opposite to the array substrate.

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