Unmanned aerial vehicle control system and unmanned aerial vehicle

Abstract

The embodiment of the utility model provides an unmanned aerial vehicle control system and an unmanned aerial vehicle. The unmanned aerial vehicle control system comprises a processor module, a watchdog module and an OR gate module, an update signal output end of the processor module is connected with a first control end of the OR gate module, a reset signal output end of the watchdog module is connected with a second control end of the OR gate module, and an output end of the OR gate module is connected with a reset signal input end of the processor module. The output of the OR gate module is controlled by the first control end and the second control end of the OR gate module, and more than one control end is used for controlling, so that the processor module can control the OR gate module not to send a reset signal to the processor module when the system is upgraded, and the upgrading abnormity can be reduced in the upgrading process of the unmanned aerial vehicle system.

Description

Technical Field

[0001] The utility model relates to the technical field of unmanned aerial vehicles, in particular to an unmanned aerial vehicle control system and an unmanned aerial vehicle. Background Art

[0002] In current drone systems, various functions are implemented through the processor. The processor may have abnormalities during use, and a watchdog is needed to ensure the reliable operation of the software system. That is, the processor will output a signal to the watchdog's feeding end at regular intervals to reset the watchdog. If the watchdog is not fed for more than the specified time, the watchdog will output a reset signal to the processor to reset the processor. During the upgrade of the drone system, the processor cannot effectively perform the feeding operation, and the watchdog will perform its function to reset the processor, resulting in abnormal upgrades. Utility Model Content

[0003] The purpose of the embodiment of the utility model is to provide a drone control system and a drone to reduce upgrade anomalies. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present utility model provides a drone control system, the system comprising:

[0005] Processor module, watchdog module and OR gate module;

[0006] The update signal output terminal of the processor module is connected to the first control terminal of the OR gate module, the reset signal output terminal of the watchdog module is connected to the second control terminal of the OR gate module, and the output terminal of the OR gate module is connected to the reset signal input terminal of the processor module.

[0007] In a possible implementation manner, the OR gate module includes an OR gate submodule and a first capacitor;

[0008] The first control end of the OR gate submodule is connected to the first control end of the OR gate module, the second control end of the OR gate submodule is connected to the second control end of the OR gate module, the ground end of the OR gate submodule is grounded, the power supply voltage end of the OR gate submodule is respectively connected to the power supply end and the first end of the first capacitor, and the output end of the OR gate submodule is connected to the output end of the OR gate module;

[0009] The second terminal of the first capacitor is grounded.

[0010] In a possible implementation, the watchdog module includes a watchdog timer and a second capacitor;

[0011] The reset signal output terminal of the watchdog timer is connected to the reset signal output terminal of the watchdog module, the ground terminal of the watchdog timer is grounded, and the power supply voltage terminal of the watchdog timer is respectively connected to the power supply terminal and the second end of the second capacitor;

[0012] A first terminal of the second capacitor is grounded.

[0013] In a possible implementation, the processor module includes a processor and a pull-up submodule;

[0014] The update signal output terminal of the processor is connected to the update signal output terminal of the processor module;

[0015] The pull-up submodule is connected to the reset signal input terminal of the processor module and the reset signal input terminal of the processor respectively.

[0016] In a possible implementation manner, the pull-up submodule includes a first resistor;

[0017] The first end of the first resistor is connected to the power supply end, and the second end of the first resistor is respectively connected to the reset signal input end of the processor and the output end of the OR gate submodule.

[0018] In a possible implementation manner, the pull-up submodule further includes a third capacitor;

[0019] The first end of the third capacitor is respectively connected to the second end of the first resistor, the reset signal input end of the processor, and the output end of the OR gate module, and the second end of the third capacitor is grounded.

[0020] In a possible implementation manner, the watchdog module further includes a second resistor;

[0021] A first end of the second resistor is connected to a dog feeding output end of the processor module, and a second end of the second resistor is connected to a dog feeding input end of the watchdog timer;

[0022] The dog feeding output terminal of the processor is connected to the dog feeding output terminal of the processor module.

[0023] In a possible implementation, the working positive voltage terminal of the processor is connected to the power supply terminal, the analog positive voltage terminal of the processor is connected to the power supply terminal, and the battery voltage terminal of the processor is connected to the power supply terminal.

[0024] In a possible implementation manner, the OR gate module further includes a third resistor;

[0025] A first end of the third resistor is connected to a reset signal output end of the watchdog timer, and a second end of the third resistor is connected to a second control end of the OR gate submodule.

[0026] In a second aspect, an embodiment of the present invention provides a drone, comprising the drone control system described in any one of the first aspects above.

[0027] The utility model provides a drone control system and a drone, comprising: a processor module, a watchdog module and an OR gate module; the update signal output terminal of the processor module is connected to the first control terminal of the OR gate module, the reset signal output terminal of the watchdog module is connected to the second control terminal of the OR gate module, and the output terminal of the OR gate module is connected to the reset signal input terminal of the processor module. Since the output of the OR gate module is controlled by the first control terminal and the second control terminal of the OR gate module, more than one control terminal is controlled, so that the processor module can control the OR gate module not to send a reset signal to the processor module when the system is upgraded, which can reduce upgrade anomalies during the upgrade of the drone system.

[0028] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0030] Figure 1 A schematic diagram of the first structure of a UAV control system provided by an embodiment of the utility model;

[0031] Figure 2 A second structural schematic diagram of a drone control system provided by an embodiment of the utility model;

[0032] Figure 3 A waveform diagram of a processor reset in the related art;

[0033] Figure 4 A waveform diagram of a watchdog timer resetting a processor in the related art;

[0034] Figure 5 A schematic structural diagram of a drone provided in an embodiment of the utility model. DETAILED DESCRIPTION

[0035] The following will be combined with the drawings in the embodiments of the utility model to clearly and completely describe the technical solutions in the embodiments of the utility model. Obviously, the described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments in the utility model, all other embodiments obtained by ordinary technicians in this field based on this application belong to the scope of protection of the utility model.

[0036] First, the professional terms that may be used in the embodiments of the present invention are explained:

[0037] Watchdog (WatchDog Timer): It is a timer circuit, which generally has an input end, called the dog feeding end, and an output end connected to the reset end RST (RESET) of the processor. When the processor is working normally, it outputs a signal to the watchdog's feeding end at regular intervals to clear the watchdog. If the dog is not fed within the specified time, the watchdog timing is exceeded, and a reset signal will be output to the processor to reset the processor to prevent the processor from crashing.

[0038] UAV: The full name is unmanned aircraft, which is an unmanned aircraft controlled by radio remote control equipment and self-contained program control device, or operated completely or intermittently autonomously by an on-board computer.

[0039] Level inversion: refers to the process of converting a circuit or signal from one level to another.

[0040] PDR (Power Down Reset): The function of PDR is to generate a reset inside the processor after the VDD voltage (the processor's operating positive voltage) drops from high to low and crosses the specified threshold.

[0041] OR gate: Also known as OR circuit, if one of several conditions is met, an event will occur. This relationship is called an "OR" logic relationship, and the circuit with an "OR" logic relationship is called an OR gate. The OR gate has multiple input terminals and one output terminal. As long as one of the inputs is high (logic "1"), the output is high (logic "1"); only when all the inputs are low (logic "0"), the output is low (logic "0").

[0042] In the current UAV system, there are multiple units working together, and each unit implements its functions through its own processor. The processor may be abnormal during use, and a watchdog is needed to ensure the reliable operation of the software system. That is, the processor will output a signal to the watchdog's feeding end at regular intervals to reset the watchdog. If the watchdog is not fed for more than the specified time, the watchdog will output a reset signal to the processor to reset the processor. During the unit upgrade process of the UAV system, due to the need to erase the memory, and the memory erasing time is generally long, the processor cannot effectively perform the feeding operation, and the watchdog will perform its function to reset the processor, resulting in an abnormal upgrade.

[0043] In order to solve the above problems, an embodiment of the utility model provides a drone control system and a drone, which are described in detail below.

[0044] See also Figure 1 , Figure 1 The first structural diagram of the UAV control system provided by the embodiment of the utility model, the system 1 comprises:

[0045] Processor module 11, watchdog module 12 and OR gate module 13;

[0046] The update signal output end of the processor module 11 is connected to the first control end of the OR gate module 13, the reset signal output end of the watchdog module 12 is connected to the second control end of the OR gate module 13, and the output end of the OR gate module 13 is connected to the reset signal input end of the processor module 11.

[0047] The processor module 11 is used to output a high level signal / low level signal to the first control terminal of the OR gate module 13 through its own update signal output terminal;

[0048] The watchdog module 12 is used to output a reset signal (low level signal) to the second control terminal of the OR gate module 13 through its own reset signal output terminal;

[0049] The OR gate module 13 is used to receive a high level signal / low level signal through its own first control end, receive a reset signal through its own second control end, and based on its own logical relationship, output a high level signal / low level signal to the reset signal input end of the processor module 11 through its own output end.

[0050] In the embodiment of the utility model, since the output of the OR gate module 13 is controlled by the first control end and the second control end of the OR gate module 13, more than one control end is controlled, so that the processor module 11 can control the OR gate module 13 not to send a reset signal to the processor module 11 when the system is upgraded. Based on the logical relationship of the OR gate module 13, when the first control end input is a high-level signal, the second control end input is a high-level signal or a low-level signal, and the output end of the OR gate module 13 outputs a high-level signal. Therefore, by controlling the output of the update signal output end of the processor module 11, the output of the reset signal output end of the watchdog module 12 cannot affect the output of the output end of the OR gate module 13, that is, it cannot affect the input of the reset signal input end of the processor module 11, which can reduce upgrade abnormalities during the upgrade of the drone system.

[0051] In one possible implementation, see Figure 2 , the OR gate module 13 includes an OR gate submodule 131 and a first capacitor C1;

[0052] The first control terminal A of the OR gate submodule 131 is connected to the first control terminal of the OR gate module 13, the second control terminal B of the OR gate submodule 131 is connected to the second control terminal of the OR gate module 13, the ground terminal GND1 of the OR gate submodule 131 is grounded GND, the power supply voltage terminal VCC1 of the OR gate submodule 131 is respectively connected to the power supply terminal VCC' and the first end of the first capacitor C1, and the output terminal Y of the OR gate submodule 131 is connected to the output terminal of the OR gate module 13;

[0053] A second end of the first capacitor C1 is connected to the ground GND.

[0054] The voltage value of the power supply terminal VCC' can be set according to the actual situation of the circuit. In an example, the voltage value of the power supply terminal VCC' can be 3.3V.

[0055] It is understandable that the chip model and manufacturer of the OR gate submodule 131 can be selected according to the actual situation of the circuit, and the embodiment of the utility model does not specifically limit this. In one example, the chip model of the OR gate submodule 131 can be SN74AHC1G32DBVR.

[0056] The first capacitor C1 is a filter capacitor, which is mainly used to filter out some noise. The capacitance value of the first capacitor C1 can be adjusted according to actual conditions. In an example, the capacitance value of the first capacitor C1 can be 0.1uf / 16V (16V means the maximum withstand voltage is 16V).

[0057] In one possible implementation, see Figure 2, the watchdog module 12 includes a watchdog timer 121 and a second capacitor C2;

[0058] The reset signal output terminal of the watchdog timer 121 connected to the reset signal output terminal of the watchdog module 12, the ground terminal GND2 of the watchdog timer 121 is grounded GND, and the power supply voltage terminal VCC2 of the watchdog timer 121 is connected to the power supply terminal VCC' and the second end of the second capacitor C2 respectively;

[0059] A first terminal of the second capacitor C2 is grounded GND.

[0060] It is understandable that there are many manufacturers and models of watchdog timer 121, and the embodiment of the utility model does not specifically limit this. In an example, the model of watchdog timer 121 can be MAX823REUK.

[0061] The second capacitor C2 is a filter capacitor, which is mainly used to filter out some noise. The capacitance value of the second capacitor C2 can be adjusted according to actual conditions. In an example, the capacitance value of the second capacitor C2 can be 0.1uf / 16V (16V means the maximum withstand voltage is 16V).

[0062] In one possible implementation, see Figure 2 , the processor module 11 includes a processor 111 and a pull-up submodule 112;

[0063] The update signal output terminal DIS_WDG of the processor 111 is connected to the update signal output terminal of the processor module 11;

[0064] The pull-up submodule 112 is connected to the reset signal input terminal of the processor module 11 and the reset signal input terminal NRST of the processor 111 respectively.

[0065] It is understandable that there are many manufacturers and models of processor 111 to choose from, and the embodiment of the utility model does not specifically limit this. In an example, the model of processor 111 can be STM32F405RGT6.

[0066] The pull-up submodule 112 is used to provide an initial level to the reset signal input terminal NRST of the processor 111, so as to stabilize the initial level of the reset signal input terminal NRST and prevent false triggering that may be caused by being in a suspended state.

[0067] In one possible implementation, see Figure 2 , the pull-up submodule 112 includes a first resistor R1;

[0068] The first end of the first resistor R1 is connected to the power supply terminal VCC′, and the second end of the first resistor R1 is connected to the reset signal input terminal NRST of the processor 111 and the output terminal Y of the OR gate submodule 131 respectively.

[0069] The first resistor R1 is a pull-up resistor. The main function of the first resistor R1 is to serve as a protection resistor to limit the current between the power supply terminal VCC' and the signal terminal (the reset signal input terminal NRST of the processor 111, the output terminal Y of the OR gate module 131). The resistance value of the first resistor R1 can be adjusted according to actual conditions. In an example, the resistance value of the first resistor R1 can be 4.75 kΩ.

[0070] In one possible implementation, see Figure 2 , the pull-up submodule 112 further includes a third capacitor C3;

[0071] The first end of the third capacitor C3 is respectively connected to the second end of the first resistor R1, the reset signal input terminal NRST of the processor 111, and the output terminal Y of the OR gate submodule 131, and the second end of the third capacitor C3 is grounded GND.

[0072] The third capacitor C3 is a filter capacitor, which is mainly used to filter out some noise. The capacitance value of the third capacitor C3 can be adjusted according to actual conditions. In an example, the capacitance value of the third capacitor C3 can be 0.1uf / 16V (16V means the maximum withstand voltage is 16V).

[0073] In one possible implementation, see Figure 2 , the watchdog module 12 also includes a second resistor R2;

[0074] A first end of the second resistor R2 is connected to a dog feeding output end of the processor module 11, and a second end of the second resistor R2 is connected to a dog feeding input end WDI1 of the watchdog timer 121;

[0075] The dog feeding output terminal WDI2 of the processor 111 is connected to the dog feeding output terminal of the processor module 11 .

[0076] The second resistor R2 is used as a current limiting resistor. The resistance value of the second resistor R2 can be adjusted according to actual conditions. In one example, the resistance value of the second resistor R2 can be 33Ω.

[0077] In one possible implementation, see Figure 2The working positive voltage terminal VDD of the processor 111 is connected to the power supply terminal VCC', the analog positive voltage terminal VDDA of the processor 111 is connected to the power supply terminal VCC', and the battery voltage terminal VBAT of the processor 111 is connected to the power supply terminal VCC'.

[0078] In one possible implementation, see Figure 2 , the working negative voltage terminal VSS of the processor 111 is grounded GND, and the analog negative voltage terminal VSSA of the processor 111 is grounded GND.

[0079] In one possible implementation, see Figure 2 , the OR gate module 13 also includes a third resistor R3;

[0080] The first end of the third resistor R3 is connected to the reset signal output end of the watchdog timer 121. The second end of the third resistor R3 is connected to the second control end B of the OR gate submodule 131 .

[0081] The third resistor R3 is a debugging resistor, which is convenient for measurement and debugging during experiments. In an example, the resistance value of the third resistor R3 can be 0R.

[0082] It can be understood that the ground GND in the above utility model embodiment is the same ground, and the power supply terminal VCC′ in the above utility model embodiment is the same power supply terminal.

[0083] It can be understood that the "1" and "2" in VCC1 and VCC2, GND1 and GND2, WDI1 and WDI2 in the above utility model embodiments are only used to distinguish the same pins between different chips.

[0084] See also Figure 2 The processor 111 has a reset function. During the power-on process, the processor 111 will reset the system through its own NRST terminal. During the operation of the processor 111, pulling down its own NRST terminal will also reset the system. For details, see Figure 3 , the processor 111 can enable / disable the internal power monitor by controlling the level of the PDR_ON terminal. When the PDR_ON terminal level is low, the internal power monitor is turned off (disabled). When the PDR_ON terminal level is high, the internal power monitor is enabled. The functions affected by the internal power monitor include PDR power down reset (Power Down Reset). The function of PDR is to reset the power supply to V DD When the voltage drops from high to low and crosses the specified threshold (PDR=1.7V), a reset is generated inside the processor. Figure 3 The time in represents time.

[0085] See also Figure 2 In the case where the unit in the drone system is not upgraded, or the watchdog timer 121 is required to perform its function, during the power-on operation of the watchdog timer 121, the dog feeding output terminal WDI2 of the processor 111 performs a level flip (commonly known as dog feeding) on ​​the dog feeding input terminal WDI1 of the watchdog timer 121. If the level of the dog feeding input terminal WDI1 of the watchdog timer 121 does not flip, after t RP The reset signal output terminal of the watchdog timer 121 A low level pulse signal appears, and the processor 111 can be reset by this low level pulse signal (the low level pulse signal is input to the reset signal input terminal NRST of the processor 111). The above process can be referred to Figure 4 , the reliability of each unit in the UAV system is improved through the watchdog timer 121, thereby improving the reliability of the UAV system. Figure 4 In, t RP (Reset timeout Period) is the reset timeout period, t WD (WatchDog timeout Period) is the watchdog timeout period, t RST (RESET) is the reset signal rise time.

[0086] See also Figure 2 The update signal output terminal DIS_WDG of the processor 111 is connected to the first control terminal A of the OR gate submodule 131, and the reset signal output terminal of the watchdog timer 121 is connected to the reset signal output terminal DIS_WDG of the processor 111. The output terminal A of the OR submodule 131 is connected to the second control terminal B of the OR submodule 131, and the output terminal A of the OR submodule 131 is connected to the reset signal input terminal NRST of the processor 111. The logic table of the OR submodule 131 is shown in Table 1 below (high level is represented by H, low level is represented by L, and high level / low level is represented by X):

[0087] Table 1

[0088] A B Y H X H X H H L L L

[0089] When the update signal output terminal DIS_WDG of the processor 111 is at a high level, the first control terminal A of the gate submodule 131 is at a high level, and the reset signal output terminal of the watchdog timer 121 is at a high level. (The second control terminal B of the OR gate submodule 131) Regardless of high level / low level, the output terminal Y of the OR gate submodule 131 is high level, and the processor 111 cannot be reset, so the function of the watchdog timer can be disabled, that is, when the unit in the drone system is upgraded, the watchdog timer is shielded to reduce upgrade abnormalities, and the reliability of each unit can be improved through the upgrade.

[0090] Only when the first control terminal A and the second control terminal B of the OR gate submodule 131 are both at a low level, the output terminal Y of the OR gate submodule 131 will output a low level. The output terminal Y of the OR gate submodule 131 is connected to the reset signal input terminal NRST of the processor 111, so the OR gate submodule 131 will output a low level to reset the processor 111 at this time.

[0091] That is, when the update signal output terminal DIS_WDG of the processor 111 is at a low level, the first control terminal A of the gate submodule 131 is at a low level, and the reset signal output terminal of the watchdog timer 121 is at a low level. (the second control terminal B of the OR gate module 131) will affect the level of the output terminal Y of the OR gate module 131, and the reset signal output terminal of the watchdog timer 121 Only when there is a low level pulse will the output terminal Y of the OR gate submodule 131 be pulled low, thereby resetting the processor 111.

[0092] The utility model embodiment also provides a drone 2, see Figure 5 The drone 2 includes the drone control system 1 described in any one of the above-mentioned utility model embodiments.

[0093] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims

1. A drone control system, characterized in that: The system comprises: Processor module, watchdog module and OR gate module; The update signal output terminal of the processor module is connected to the first control terminal of the OR gate module, the reset signal output terminal of the watchdog module is connected to the second control terminal of the OR gate module, and the output terminal of the OR gate module is connected to the reset signal input terminal of the processor module.

2. The system according to claim 1, characterized in that The OR gate module includes an OR gate submodule and a first capacitor; The first control end of the OR gate submodule is connected to the first control end of the OR gate module, the second control end of the OR gate submodule is connected to the second control end of the OR gate module, the ground end of the OR gate submodule is grounded, the power supply voltage end of the OR gate submodule is respectively connected to the power supply end and the first end of the first capacitor, and the output end of the OR gate submodule is connected to the output end of the OR gate module; The second terminal of the first capacitor is grounded.

3. The system according to claim 2, characterized in that The watchdog module includes a watchdog timer and a second capacitor; The reset signal output terminal of the watchdog timer is connected to the reset signal output terminal of the watchdog module, the ground terminal of the watchdog timer is grounded, and the power supply voltage terminal of the watchdog timer is respectively connected to the power supply terminal and the second end of the second capacitor; A first terminal of the second capacitor is grounded.

4. The system according to claim 3, characterized in that The processor module includes a processor and a pull-up submodule; The update signal output terminal of the processor is connected to the update signal output terminal of the processor module; The pull-up submodule is connected to the reset signal input terminal of the processor module and the reset signal input terminal of the processor respectively.

5. The system according to claim 4, characterized in that The pull-up submodule includes a first resistor; The first end of the first resistor is connected to the power supply end, and the second end of the first resistor is respectively connected to the reset signal input end of the processor and the output end of the OR gate submodule.

6. The system according to claim 5, characterized in that The pull-up submodule further includes a third capacitor; The first end of the third capacitor is respectively connected to the second end of the first resistor, the reset signal input end of the processor, and the output end of the OR gate module, and the second end of the third capacitor is grounded.

7. The system according to claim 4, characterized in that The watchdog module also includes a second resistor; A first end of the second resistor is connected to a dog feeding output end of the processor module, and a second end of the second resistor is connected to a dog feeding input end of the watchdog timer; The dog feeding output terminal of the processor is connected to the dog feeding output terminal of the processor module.

8. The system according to claim 4, characterized in that The working positive voltage terminal of the processor is connected to the power supply terminal, the analog positive voltage terminal of the processor is connected to the power supply terminal, and the battery voltage terminal of the processor is connected to the power supply terminal.

9. The system according to claim 3, characterized in that The OR gate module also includes a third resistor; A first end of the third resistor is connected to a reset signal output end of the watchdog timer, and a second end of the third resistor is connected to a second control end of the OR gate submodule.

10. A drone, characterized in that: The drone comprises the drone control system described in any one of claims 1 to 9 above.

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