PLC master-slave station star topology structure based on EtherCat interface

Abstract

The utility model relates to the technical field of PLCs, in particular to a PLC master-slave station star topological structure based on an EtherCat interface, which comprises a board A and a board B which are mutually independent, a first MCU chip is arranged on the board A, and a second MCU chip is arranged on the board B; the first MCU chip and the second MCU chip are respectively provided with an output pin unit, the output pin units are connected with an output PHY chip, and the output PHY chip is connected with an EtherCat output network port; the first MCU chip is also provided with an input pin unit, the input pin unit is connected with an input PHY chip, and the input PHY chip is connected with an EtherCat input network port; and the A board and the B board are connected through LVDS (Low Voltage Differential Signaling).

Description

Technical Field

[0001] The utility model relates to the technical field of PLC, in particular to a PLC master-slave station star topology structure based on an EtherCat interface. Background Art

[0002] Fieldbus has become an integrated component of automation technology. Through a large number of practical experiments and tests, it has been widely used today. It is precisely because of the popularity of fieldbus technology that PC-based control systems have been widely used. However, although the performance of controller CPUs (especially IPC performance) has developed rapidly, traditional fieldbus systems are becoming a "bottleneck" in the development of control system performance. Another factor that urgently needs technological innovation is that traditional solutions are not very ideal.

[0003] Traditionally, the layered control system usually consists of several auxiliary systems (cycle systems): the actual control task, the fieldbus system, the local expansion bus in the I / O system or a simple local firmware cycle of the peripherals. Normally, the system response time is 3-5 times the controller cycle time. In the layer above the fieldbus system (i.e. the network controller), Ethernet often represents the level of technological development to a certain extent. The newer technologies in this area are applications at the drive or I / O level, i.e. these areas where fieldbus systems were widely used in the past. These types of applications require the system to have good real-time capabilities, adapt to small data volume communication, and be economical. EtherCAT meets these requirements and can also implement Internet technology at the I / O level.

[0004] EtherCAT (Ethernet for Control Automation Technology) is a real-time industrial fieldbus communication protocol based on the Ethernet development framework. It was introduced to the market in 2003, became an international standard in 2007, and became a Chinese national standard in 2014. The emergence of EtherCAT has set new standards for the real-time performance and topology flexibility of the system.

[0005] 1) EtherCAT is one of the fastest industrial Ethernet technologies and it provides nanosecond-accurate synchronization. Compared with other bus systems with the same cycle time, EtherCAT system architecture can usually reduce CPU load by 25%-30%.

[0006] 2) EtherCAT has no restrictions on network topology. A maximum of 65,535 nodes can form a linear, bus, tree, star or any combination of topologies.

[0007] 3) Compared with traditional fieldbus systems, EtherCAT node addresses can be set automatically, without the need for network debugging, and integrated diagnostic information can accurately locate errors. At the same time, there is no need to configure switches or deal with complex MAC or IP addresses.

[0008] 4) EtherCAT master devices do not require special cards, and slave devices use highly integrated, low-cost chips that can be provided by multiple suppliers.

[0009] 5) EtherCAT provides an effective synchronization solution using accurate calibration of distributed clocks. In EtherCAT, data exchange is based entirely on pure hardware devices. Since the communication utilizes a logical ring network structure and full-duplex Fast Ethernet with an actual ring network structure, the "master clock" can simply and accurately determine the running compensation for each "slave clock", and vice versa. The distributed clock is adjusted based on this value, which means that it can provide a very accurate clock with very small signal jitter within the network.

[0010] In general, EtherCAT has the characteristics of high performance, flexible topology, easy application, low cost, high-precision device synchronization, optional cable redundancy and functional safety protocol, and hot plugging.

[0011] Currently, the EtherCat communication protocol on the market still uses a single linear topology when cascading slave devices and master devices. However, for industries such as logistics, lithium battery formation, light inspection machines, and semiconductors, the simple linear topology cannot fully meet customer needs.

[0012] For linear, bus, and tree topologies, if a multi-level topology is currently implemented, it can only be achieved through cascade communication between multiple PLCs. This is not as simple and efficient as a star structure in terms of cost and wiring complexity.

[0013] Therefore, a new technical solution is urgently needed to solve the above technical problems. Utility Model Content

[0014] The purpose of the utility model is to overcome the above-mentioned problems of the prior art and provide a PLC master-slave station star topology structure based on the EtherCat interface to solve the technical problems that the multi-level topology can only be realized through cascade communication of multiple PLCs in the prior art, and the cost and the complexity of wiring are not as simple and efficient as the star structure.

[0015] The above objectives are achieved through the following technical solutions:

[0016] A PLC master-slave station star topology structure based on an EtherCat interface, comprising a mutually independent A board and a B board, wherein the A board is provided with a first MCU chip, and the B board is provided with a second MCU chip;

[0017] The first MCU chip and the second MCU chip are both provided with an output pin unit, the output pin unit is connected to an output PHY chip, and the output PHY chip is connected to an EtherCat output network port;

[0018] The first MCU chip is also provided with an input pin unit, the input pin unit is connected to the input PHY chip, and the input PHY chip is connected to an EtherCat input network port;

[0019] The A board and the B board are connected via LVDS.

[0020] Furthermore, the input pin unit and the input PHY chip are provided with corresponding input first pin, input second pin, input third pin, input fourth pin, input fifth pin, input sixth pin, input seventh pin, input eighth pin, input ninth pin, input tenth pin, input eleventh pin, input twelfth pin and input thirteenth pin.

[0021] Furthermore, the input PHY chip is also provided with an input pin 25, an input pin 25, an input pin 25 and an input pin 25; the input pin 25, the input pin 25, the input pin 25 and the input pin 25 are used to connect to the EtherCat input network port.

[0022] Further, the output pin unit and the output PHY chip are provided with a first output pin, a second output pin, a third output pin, a fourth output pin, a fifth output pin, a sixth output pin, a seventh output pin, an eighth output pin, a ninth output pin, a tenth output pin, an eleventh output pin, a twelfth output pin and a thirteenth output pin which correspond to each other.

[0023] Furthermore, the output PHY chip is also provided with an output pin 25, an output pin 25, an output pin 25 and an output pin 25; the output pin 25, the output pin 25, the output pin 25 and the output pin 25 are used to connect to the EtherCat output network port.

[0024] Furthermore, the first MCU chip, the second MCU chip, the input PHY chip and the output PHY chip are also respectively provided with a twenty-second pin, a twenty-third pin and a twenty-fourth pin corresponding to each other.

[0025] Furthermore, one of the first MCU chips, one of the input PHY chips, and two of the output PHY chips are arranged on the A board;

[0026] One of the second MCU chips and three of the output PHY chips are arranged on the B board.

[0027] Furthermore, the first MCU chip and the second MCU chip are respectively provided with an eighteenth pin, a nineteenth pin, a twentieth pin and a twenty-first pin for realizing LVDS connection.

[0028] Furthermore, the first MCU chip and the second MCU chip are respectively connected with SPI FLASH for storing data generated during work.

[0029] Furthermore, the model of the SPI FLASHU5 is W25Q64JVSSIQ.

[0030] The utility model provides a PLC master-slave star topology structure based on the EtherCat interface. Only one PLC is needed as the master station to realize the star topology structure. While saving resources, because the communication protocol is EtherCat, the highest efficiency is achieved in terms of speed, complexity, synchronization performance, etc. This design scheme is based on the EtherCAT communication protocol, innovates on a single linear topology structure, changes the existing simple linear topology structure, realizes a multi-level topology for complex on-site processes, achieves a one-input-multiple-output effect, reduces costs, and effectively improves the use efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a framework diagram of a star topology structure of a PLC master-slave station based on an EtherCat interface described in the utility model;

[0032] Figure 2 A circuit diagram of a star topology structure of a PLC master-slave station based on an EtherCat interface described in the utility model;

[0033] Figure 3 This is a circuit structure diagram on board A in a star topology structure of a PLC master-slave station based on an EtherCat interface described in the utility model;

[0034] Figure 4This is a circuit structure diagram on board B in a star topology structure of a PLC master-slave station based on an EtherCat interface described in the utility model. DETAILED DESCRIPTION

[0035] The utility model is further described in detail below based on the accompanying drawings and embodiments. The described embodiments are only part of the embodiments of the utility model, not all of the embodiments. Based on the embodiments of the utility model, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the utility model.

[0036] like Figure 1 and 2 As shown, this solution provides a PLC master-slave station star topology structure based on the EtherCat interface, which is suitable for multi-axis complex equipment and production line networking, and the network topology is arranged in a star manner. It includes an independent A board and a B board, the A board is provided with a first MCU chip U1, and the B board is provided with a second MCU chip U2;

[0037] The first MCU chip U1 and the second MCU chip U2 are both provided with an output pin unit, and the output pin unit is connected to the output PHY chip U4, and the output PHY chip is connected to an EtherCat output network port;

[0038] The first MCU chip U1 is also provided with an input pin unit, and the input pin unit is connected to the input PHY chip U3, and the input PHY chip is connected to an EtherCat input network port;

[0039] The A board and the B board are connected via LVDS to achieve data exchange;

[0040] Specifically, the A board and the B board in this embodiment are both PCB boards, which serve as carriers of each chip.

[0041] The EtherCat input network port and the multiple EtherCat output network ports are connected to the external functional device through the EtherCat bus. By adopting this solution, only two PCB boards are set in the PLC to realize the functions of one input and five outputs, that is, to realize the function of one PLC to five.

[0042] It should be noted that the output PHY chip U4 and the input PHY chip U3 in this embodiment are of the same model, both adopting YT8522. For the convenience of explanation only, the pins of the output PHY chip U4 and the input PHY chip U3 are described differently in the embodiment.

[0043] On the other hand, in this embodiment, the first MCU chip U1 and the second MCU chip U2 have the same specifications, both of which are GT100;

[0044] The EtherCat input network port and the EtherCat output network port have the same specifications.

[0045] In addition, this embodiment is powered by a 3.3V power supply.

[0046] like Figure 3 As shown, the input pin unit and the input PHY chip U3 are provided with corresponding input first pin RX_CLK0, input second pin RX_DV0, input third pin RX_ERR0, input fourth pin RX_D0-3, input fifth pin RX_D0-2, input sixth pin RX_D0-1, input seventh pin RX_D0-0, input eighth pin TX_ENA0, input ninth pin TX_D0-3, input tenth pin TX_D0-2, input eleventh pin TX_D0-1, input twelfth pin TX_D0-0 and input thirteenth pin LINK_MII0; the same pins on the input pin unit and the input PHY chip U3 are connected to each other.

[0047] like Figure 3 As shown, the input PHY chip U3 is also provided with input pin 25 TX+0, input pin 25 TX-0, input pin 25 RX+0 and input pin 25 RX-0; the input pin 25 TX+0, the input pin 25 TX-0, the input pin 25 RX+0 and the input pin 25 RX-0 are used to connect to the EtherCat input network port.

[0048] like Figure 3 and 4 As shown, the output pin unit and the output PHY chip U4 are provided with corresponding first output pin RX_CLK, second output pin RX_DV, third output pin RX_ERR, fourth output pin RX_D3, fifth output pin RX_D2, sixth output pin RX_D1, seventh output pin RX_D0, eighth output pin TX_ENA, ninth output pin TX_D3, tenth output pin TX_D2, eleventh output pin TX_D1, twelfth output pin TX_D0 and thirteenth output pin LINK_MII; the same pins on the output pin unit and the output PHY chip U4 are connected to each other.

[0049] In this embodiment, the output PHY chip U4 is also provided with an output pin 25 TX+, an output pin 25 TX-, an output pin 25 RX+ and an output pin 25 RX-; the output pin 25 TX+, the output pin 25 TX-, the output pin 25 RX+ and the output pin 25 RX- are used to connect to the EtherCat output network port.

[0050] In addition, the first MCU chip U1, the second MCU chip U2, the input PHY chip U3 and the output PHY chip U4 are also respectively provided with a twenty-second pin LINKPOL, a twenty-third pin MI_DATA and a twenty-fourth pin RESET which correspond to each other.

[0051] Specifically, on the A board, the 22nd pin LINKPOL, the 23rd pin MI_DATA and the 24th pin RESET on the input PHY chip U3 and the output PHY chip U4 are used to be connected to the 22nd pin LINKPOL, the 23rd pin MI_DATA and the 24th pin RESET on the first MCU chip U1 accordingly;

[0052] On the B board, the 22nd pin LINKPOL, the 23rd pin MI_DATA and the 24th pin RESET on the output PHY chip U4 are used to be correspondingly connected to the 22nd pin LINKPOL, the 23rd pin MI_DATA and the 24th pin RESET on the second MCU chip U2.

[0053] like Figure 1 As shown, as a specific embodiment of the present solution, one of the first MCU chips U1, one of the input PHY chips U3 and two of the output PHY chips U4 are arranged on the A board;

[0054] One of the second MCU chips U2 and three of the output PHY chips U4 are arranged on the B board;

[0055] In this embodiment, this structure can realize a structure of 1 input and 5 outputs on the PLC. Compared with the traditional technology that can only perform cascade communication through multiple PLCs, not only is the structure simpler and the connection more convenient, but the cost is also significantly reduced.

[0056] The first MCU chip U1 and the second MCU chip U2 are also respectively provided with an eighteenth pin LVDS_TX-, a nineteenth pin LVDS_TX+, a twentieth pin LVDS_RX- and a twenty-first pin LVDS_RX+ for realizing LVDS connection;

[0057] Specifically, LVDS low-voltage differential signaling is a differential signal technology with low power consumption, low bit error rate, low crosstalk and low radiation. This transmission technology can reach more than 155Mbps. The core of LVDS technology is the use of extremely low voltage swing high-speed differential transmission data, which can achieve point-to-point or point-to-multipoint connection. Its transmission medium can be copper PCB connection or balanced cable.

[0058] In this embodiment, the first MCU chip U1 and the second MCU chip U2 exchange data via LVDS, and the specific connection method is as follows:

[0059] The eighteenth pin LVDS_TX- on the first MCU chip U1 is connected to the twentieth pin LVDS_RX- on the second MCU chip U2;

[0060] The nineteenth pin LVDS_TX+ on the first MCU chip U1 is connected to the twenty-first pin LVDS_RX+ on the second MCU chip U2;

[0061] The 20th pin LVDS_RX- on the first MCU chip U1 is connected to the 18th pin LVDS_TX- on the second MCU chip U2;

[0062] The 21st pin LVDS_RX+ on the first MCU chip U1 is connected to the 19th pin LVDS_TX+ on the second MCU chip U2;

[0063] In addition, the first MCU chip U1 and the second MCU chip U2 are respectively connected with SPI FLASHU5 for storing data generated during work; wherein, the model of the SPI FLASHU5 is W25Q64JVSSIQ.

[0064] The above description is only for illustrating the implementation mode of the present invention and is not intended to limit the present invention. For those skilled in the art, any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A PLC master-slave station star topology structure based on EtherCat interface, characterized in that: It comprises a mutually independent A board and a B board, wherein the A board is provided with a first MCU chip (U1), and the B board is provided with a second MCU chip (U2); The first MCU chip (U1) and the second MCU chip (U2) are both provided with an output pin unit, the output pin unit is connected to an output PHY chip (U4), and the output PHY chip is connected to an EtherCat output network port; The first MCU chip (U1) is also provided with an input pin unit, the input pin unit is connected to an input PHY chip (U3), and the input PHY chip is connected to an EtherCat input network port; The A board and the B board are connected via LVDS.

2. The PLC master-slave station star topology structure based on the EtherCat interface according to claim 1 is characterized in that: The input pin unit and the input PHY chip (U3) are provided with a first input pin (RX_CLK0), a second input pin (RX_DV0), a third input pin (RX_ERR0), a fourth input pin (RX_D0-3), a fifth input pin (RX_D0-2), a sixth input pin (RX_D0-1), a seventh input pin (RX_D0-0), an eighth input pin (TX_ENA0), a ninth input pin (TX_D0-3), a tenth input pin (TX_D0-2), an eleventh input pin (TX_D0-1), a twelfth input pin (TX_D0-0) and a thirteenth input pin (LINK_MII0) which correspond to each other.

3. The PLC master-slave station star topology structure based on EtherCat interface according to claim 2 is characterized in that: The input PHY chip (U3) is also provided with an input pin 25 (TX+0), an input pin 25 (TX-0), an input pin 25 (RX+0) and an input pin 25 (RX-0); the input pin 25 (TX+0), the input pin 25 (TX-0), the input pin 25 (RX+0) and the input pin 25 (RX-0) are used to connect to the EtherCat input network port.

4. The PLC master-slave station star topology structure based on the EtherCat interface according to claim 1 is characterized in that: The output pin unit and the output PHY chip (U4) are both provided with a first output pin (RX_CLK), a second output pin (RX_DV), a third output pin (RX_ERR), a fourth output pin (RX_D3), a fifth output pin (RX_D2), a sixth output pin (RX_D1), a seventh output pin (RX_D0), an eighth output pin (TX_ENA), a ninth output pin (TX_D3), a tenth output pin (TX_D2), an eleventh output pin (TX_D1), a twelfth output pin (TX_D0) and a thirteenth output pin (LINK_MII) which correspond to each other.

5. The PLC master-slave station star topology structure based on EtherCat interface according to claim 4 is characterized in that: The output PHY chip (U4) is also provided with an output pin 25 (TX+), an output pin 25 (TX-), an output pin 25 (RX+) and an output pin 25 (RX-); the output pin 25 (TX+), the output pin 25 (TX-), the output pin 25 (RX+) and the output pin 25 (RX-) are used to connect to the EtherCat output network port.

6. The PLC master-slave station star topology structure based on EtherCat interface according to claim 1 is characterized in that: The first MCU chip (U1), the second MCU chip (U2), the input PHY chip (U3) and the output PHY chip (U4) are also respectively provided with a twenty-second pin (LINKPOL), a twenty-third pin (MI_DATA) and a twenty-fourth pin (RESET) which correspond to each other.

7. The PLC master-slave station star topology structure based on EtherCat interface according to claim 1 is characterized in that: The A board is provided with one of the first MCU chips (U1), one of the input PHY chips (U3) and two of the output PHY chips (U4); One of the second MCU chips (U2) and three of the output PHY chips (U4) are arranged on the B board.

8. The PLC master-slave station star topology structure based on EtherCat interface according to claim 1 is characterized in that: The first MCU chip (U1) and the second MCU chip (U2) are also respectively provided with an eighteenth pin (LVDS_TX-), a nineteenth pin (LVDS_TX+), a twentieth pin (LVDS_RX-) and a twenty-first pin (LVDS_RX+) for realizing LVDS connection.

9. The PLC master-slave station star topology structure based on EtherCat interface according to claim 1 is characterized in that: The first MCU chip (U1) and the second MCU chip (U2) are also respectively connected to a SPIFLASH (U5) for storing data generated during work.

10. The PLC master-slave station star topology structure based on EtherCat interface according to claim 9, characterized in that: The model of the SPIFLASH (U5) is W25Q64JVSSIQ.

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