PCIe-based test master control system

Abstract

The utility model discloses a PCIe-based test master control system, which is applied to a PXI case, the PXI case comprises a PCIe panel and an IO panel, the IO panel comprises a GPIB interface and is used for being in communication connection with equipment to be tested, the PCIe panel comprises a PCIe interface and is used for data transmission, and the test master control system comprises a bottom plate module comprising an FPGA circuit, a data transmission module and a data transmission module, the FPGA circuit is connected with an interface on the PCIe panel or the IO panel through an interface circuit preset on the bottom plate module; wherein the FPGA circuit is connected with the GPIB interface through a GPIB control bus; the pinch plate module comprises a processing chip, and the processing chip is connected to the interface circuit through a chip system circuit on the pinch plate module so as to be connected with an interface on the PCIe panel or the IO panel; and the processing chip is connected with the FPGA circuit so as to control the test master control system. The test master control system provided by the utility model can meet the test requirements of high operation and high real-time performance of products in various fields.

Description

Technical Field

[0001] The utility model relates to the field of test systems, and in particular to a test main control system based on PCIe. Background Art

[0002] In the trend of industrial and technological development, the demand for product testing is increasing, which is not only reflected in the number of testing needs, but also in the requirements for the diversification, intelligence and batch production of testing platform performance.

[0003] However, due to the limitations of design concepts, structures and technologies, traditional product testing platforms have gradually exposed their shortcomings in handling complex testing tasks. For example, in the field of smart cars, with the rapid development of autonomous driving technology, the testing requirements for key components such as sensors and control systems are becoming increasingly high, which not only requires the test platform to provide accurate and fast test results, but also requires it to be able to adapt to the testing needs of different types of components. Therefore, existing test platforms face major challenges and cannot fully meet the high standards for test performance in the development and production of new generation products in these fields. Utility Model Content

[0004] The utility model aims to solve at least one of the technical problems existing in the prior art. To this end, the utility model proposes a test main control system based on PCIe, which can meet the high computing and high real-time testing requirements for products in various fields.

[0005] According to a PCIe-based test control system of an embodiment of the utility model, the test control system is applied to a PXI chassis, the PCIE chassis includes a PCIe panel and an IO panel, the IO panel includes a GPIB interface for communicating with a device under test, the PCIe panel includes a PCIe interface for data transmission, and the test control system includes:

[0006] A baseboard module, comprising an FPGA circuit, wherein the FPGA circuit is connected to an interface on the PCIe panel or the IO panel via an interface circuit preset on the baseboard module; wherein the FPGA circuit is connected to the GPIB interface via a GPIB control bus;

[0007] The pinch board module includes a processing chip, which is connected to the interface circuit through the chip system circuit on the pinch board module, and then connected to the interface on the PCIe panel or the IO panel; the processing chip is connected to the FPGA circuit to realize control of the test main control system.

[0008] A PCIe-based test control system according to an embodiment of the utility model has at least the following beneficial effects:

[0009] Applied to a PXI chassis, the PXI chassis includes a PCIe panel and an IO panel, the IO panel includes a GPIB interface for communication connection with the device to be tested, the PCIe panel includes a PCIe interface for data transmission, and the test main control system includes: a baseboard module, including an FPGA circuit, the FPGA circuit is connected to the interface on the PCIe panel or the IO panel through an interface circuit preset on the baseboard module; wherein the FPGA circuit is connected to the GPIB interface through a GPIB control bus; a gusset module, including a processing chip, the processing chip is connected to the interface circuit through a chip system circuit on the gusset module, and then connected to the interface on the PCIe panel or the IO panel; the processing chip is connected to the FPGA circuit to realize control of the test main control system. The utility model adopts a PCIe bus for data transmission, which can meet the needs of high-computing and high-real-time testing of products, and can provide more powerful computing power through the joint calculation of the processing chip and the FPGA circuit, supporting high-computing testing of products.

[0010] According to some embodiments of the present invention, the processing chip is connected to the PCIe interface on the PCIe panel via a PCIe bus in an interface circuit; wherein a PCIe switching chip is also provided on the PCIe bus, and the PCIe switching chip is used to expand a single-channel PCIe interface into a multi-channel PCIe interface.

[0011] According to some embodiments of the utility model, the baseboard module also includes a clock buffer chip, which is respectively connected to the processing chip and the PCIe switching chip through the interface circuit. The clock buffer chip is also connected to each channel of the multi-channel PCIe interface, and the clock buffer chip is used to provide a clock signal for the processing chip and the PCIe switching chip.

[0012] According to some embodiments of the utility model, the processing chip includes an embedded neural network processing unit and an image processing unit. The neural network processing unit is used to intelligently analyze and process parameter data of the device under test, and the image processing unit is used to analyze and process image data of the device under test.

[0013] According to some embodiments of the utility model, the IO panel also includes an external indicator light interface, the external indicator light is connected to the FPGA circuit through the interface circuit, and the external indicator light includes a power indicator light, a storage status indicator light, a programmable indicator light and an alarm indicator light.

[0014] According to some embodiments of the present utility model, a first control circuit, a second control circuit and a third control circuit are included between the processing chip and the FPGA circuit;

[0015] The first control circuit is used to respond to a reset button on the IO panel, the reset button is connected to the FPGA circuit, and is used to reset the processing chip;

[0016] The second control circuit is based on a synchronous serial communication protocol and is used for data exchange and configuration control between the processing chip and the FPGA circuit;

[0017] The third control circuit is based on a bidirectional serial communication bus protocol and is used by the processing chip to monitor the working status of the FPGA circuit.

[0018] According to some embodiments of the present invention, the processing chip is connected to the memory module via a memory bus in the interface circuit, and the processing chip is also connected to an onboard storage hard disk via a SATA 3.0 interface.

[0019] According to some embodiments of the utility model, the processing chip is connected to the DP display interface, HDMI display interface, network interface, USB interface and communication interface of the IO panel through the interface circuit; wherein, the USB interface includes a USB2.0 interface and a USB3.0 interface, and the interface circuit between the USB2.0 interface and the processing chip is also provided with a USB expansion chip.

[0020] According to some embodiments of the present utility model, the pinch plate module and the base plate module are connected using a first board-to-board connector, the IO panel is arranged on an interface board, and the interface board and the base plate module are connected via a second board-to-board connector.

[0021] According to some embodiments of the present invention, an SSD solid state drive slot is provided on the surface opposite to the connection surface of the base plate module and the pinch plate module. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the specific implementation of the utility model or the technical solution in the prior art, the following is a brief introduction to the drawings required for the specific implementation or the prior art description. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, each element or part is not necessarily drawn according to the actual scale.

[0023] Figure 1 A module block diagram of a PCIe-based test control system provided by an embodiment of the utility model;

[0024] Figure 2 Another module block diagram of a PCIe-based test control system provided by an embodiment of the utility model;

[0025] Figure 3 A schematic diagram of an IO panel provided in an embodiment of the utility model;

[0026] Figure 4 A schematic diagram of the structure of a PCIe-based test control system provided by an embodiment of the utility model;

[0027] Figure 5 Another structural schematic diagram of a PCIe-based test main control system provided by an embodiment of the utility model. DETAILED DESCRIPTION

[0028] The following embodiments of the technical solution of the utility model are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the utility model, and are therefore only used as examples, and cannot be used to limit the protection scope of the utility model.

[0029] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by technicians in the field to which the utility model belongs.

[0030] PXI (PCI eXtensions for Instrumentation) chassis is a standardized chassis system designed specifically for instruments and test equipment. It uses the PCI bus as the communication bus and can embed various PCI bus-based modules.

[0031] like Figure 1 As shown, a PCIe-based test control system 100 is applied to a PXI chassis, the PXI chassis includes a PCIe panel 140 and an IO panel 130, the IO panel 130 includes a GPIB interface for communicating with a device under test, the PCIe panel 140 includes a PCIe interface for data transmission, and the test control system 100 includes:

[0032] The baseboard module 120 includes an FPGA circuit 121, and the FPGA circuit 121 is connected to an interface on the PCIe panel 140 or the IO panel 130 through an interface circuit preset on the baseboard module 120; wherein the FPGA circuit 121 is connected to the GPIB interface through a GPIB control bus;

[0033] The pinch board module 110 includes a processing chip 111, which is connected to the interface circuit through the chip system circuit on the pinch board module 110, and then connected to the interface on the PCIe panel 140 or the IO panel 130; the processing chip 111 is connected to the FPGA circuit 121 to realize the control of the test main control system 100.

[0034] During operation, the processing chip 111 is connected to external devices through various interfaces of the PCIe panel 140 and the IO panel 130 of the PXI chassis to control the test system and the device under test. Specifically, the processing chip 111 can send control instructions to the FPGA circuit 121, and the FPGA circuit 121 controls the GPIB interface on the IO panel 130 through the GPIB control bus to interact with the device under test. At the same time, the processing chip 111 can also transmit data with the test system through the PCIe panel 140.

[0035] In some embodiments, the processing chip 111 may specifically be RK3588. As a high-performance ARM processor, the RK3588 processor has powerful computing capabilities and rich interface resources, and can be applied to various control requirements of the test main control system 100 of the present utility model.

[0036] Among them, the test main control system 100 adopts a separate design of the baseboard module 120 and the gusset module 110, separating the bottom FPGA circuit 121 and the upper processing chip 111, thereby improving the modularity and scalability of the system. The baseboard module 120 and the gusset module 110 can be independently designed and upgraded, thereby improving the flexibility and scalability of the entire system. At the same time, the modular design makes it easier to maintain and replace each component, thereby improving the maintainability of the system.

[0037] The test main control system 100 uses the PCIe bus architecture to provide a high-bandwidth data transmission channel through the PCIe panel 140, and the IO panel 130 provides a GPIB interface for communicating with the device under test. The FPGA circuit 121 of the baseboard module 120 connects the various interfaces to realize the reception and transmission and processing of signals; the processing chip 111 of the gusset module 110 is responsible for unified control of the entire test system to meet the needs of high-computing and high-real-time testing of products. The IO panel 130 also provides a variety of interfaces such as the GPIB interface, which can be connected to the device under test in different forms of communication to meet various product testing requirements. The FPGA circuit 121 and the processing chip 111 work closely together through the connection lines, giving full play to their respective advantages and improving the computing performance and real-time control capabilities of the entire system.

[0038] In summary, the PCIe-based test control system 100, through its modular design, high-speed data transmission, flexible interface support, and hardware collaborative computing, can very well meet the needs of high-performance testing of products in various fields.

[0039] like Figure 2As shown, in some embodiments, the processing chip 111 is connected to the PCIe interface on the PCIe panel 140 via a PCIe bus in the interface circuit; wherein a PCIe switching chip is also provided on the PCIe bus, and the PCIe switching chip is used to expand a single-channel PCIe interface into a multi-channel PCIe interface.

[0040] Among them, the PCIe switching chip (PCIeSwitch) can expand the original single PCIe interface into multiple PCIe channels, increase the bus bandwidth, and meet the needs of high-speed data transmission.

[0041] In some embodiments, in 4-links mode, the processing chip 111 outputs a PCIe 3.0x4 interface, which is expanded by a PCIe Switch chip and divided into four independent PCIe 3.0x4 interfaces, which are respectively connected to the PCIe panel 140. Through the expansion of PCIe Switch, the bandwidth of a single PCIe 3.0x4 interface is expanded to the total bandwidth of four groups of PCIe 3.0x4 interfaces, which greatly improves the bus bandwidth. In 2-links mode, a PCIe Switch chip is integrated on the PCIe panel 140. This design is suitable for application scenarios with multiple slots in a large chassis. Through PCIe Switch, a single PCIe interface can be expanded to multiple channels to improve resource utilization efficiency.

[0042] In some embodiments, the baseboard module may also include a clock buffer chip (ClockBuffer), which is connected to the processing chip 111 and the PCIe switching chip through an interface circuit. The clock buffer chip is also connected to each channel of the multi-channel PCIe interface to provide a unified clock signal for the processing chip 111 and the PCIe switching chip, and the frequency may be 100MHz. By adopting a unified clock source, the clock synchronization between the modules inside the system can be ensured, and data transmission problems caused by timing errors can be avoided. At the same time, the clock buffer chip isolates the clock signals of the processing chip 111 and the PCIe switching chip to avoid mutual interference between the two. This design can provide high-quality clock signals and ensure the stability and reliability of the entire test system. In short, the introduction of the clock buffer chip not only ensures the timing consistency between the multi-channel PCIe interfaces, but also isolates the clocks of the processing chip and the PCIe switching chip, effectively improving the overall time characteristics and anti-interference ability of the system, and further improving the overall performance of the test main control system.

[0043] In some embodiments, the processing chip 111 includes an embedded neural network processing unit and an image processing unit. The neural network processing unit can intelligently analyze and process parameter data of the device under test, and the image processing unit can analyze and process image data of the device under test.

[0044] Among them, the neural network processing unit can be used to intelligently analyze and process the parameter data of the device under test. For example, the various performance parameters collected are analyzed through machine learning algorithms to identify abnormal conditions and predict possible failures. The image processing unit can be used to analyze and process the image data of the device under test. For example, the appearance of the device can be inspected to identify surface defects; or the dynamic image of the device under working status can be monitored and analyzed in real time.

[0045] It is understandable that in the testing of electronic consumer products such as smart phones, computers, and home appliances, this processing chip can achieve efficient testing. The neural network processing unit can intelligently analyze the various parameter data of electronic products and quickly identify product failures and abnormalities; the image processing unit can perform comprehensive scanning and image recognition of product appearance, structure, etc. to assist in detecting product quality problems. Through the multi-modal fusion of parameter analysis and image detection, more intelligent and accurate automated testing of electronic products can be achieved.

[0046] In some embodiments, the neural network processing unit and the image processing unit in the processing chip 111 may work together in the following manner:

[0047] The neural network processing unit can receive various parameter data from the device under test, such as voltage, current, temperature, etc., while the image processing unit can process image data from the device under test, such as appearance, internal structure, etc.; the neural network processing unit can use its powerful learning and reasoning capabilities to intelligently analyze the parameter data and extract key information, and the image processing unit can analyze and identify the image data, such as defect detection, size measurement, etc. The analysis results obtained by the neural network processing unit and the image processing unit can be fused to form a more comprehensive and accurate test result. For example, combining the results of parameter data analysis and image analysis can better diagnose the working status of the device under test. In short, the neural network processing unit and the image processing unit integrated in the processing chip 111 can fully cooperate to greatly enhance the intelligent analysis capability of the test main control system 100 and meet the needs of complex test scenarios.

[0048] In some embodiments, the IO panel 130 also includes an external indicator light interface. The external indicator light is connected to the FPGA circuit 121 through an interface circuit. The external indicator light includes a power indicator light, a storage status indicator light, a programmable indicator light, and an alarm indicator light.

[0049] Among them, the power indicator light is used to display the power status of the test main control system 100; the storage status indicator light is used to display the working status of the system's internal storage devices (such as hard disks, SSDs, etc.); the programmable indicator light can be programmed and controlled by the FPGA circuit 121 to display information such as the system's operating status or test progress; the alarm indicator light is used to display alarm information when an abnormal situation occurs in the system. This design of integrating multiple indicator lights on the IO panel can intuitively feedback the system's working status and operating conditions to the user. As the system control hub, the FPGA circuit 121 can flexibly drive and control these indicator lights to provide users with intuitive system status feedback, which is helpful for equipment debugging and fault diagnosis.

[0050] In some embodiments, the external indicator light interface is connected and controlled through an FPGA circuit. As a programmable logic device, the FPGA can flexibly program and control the indicator lights. Combined with the neural network and image processing functions inside the processing chip, the FPGA can intelligently drive and switch these indicator lights. For example, according to the analysis results of the neural network on the parameter data, the corresponding status indicator light can be lit, or, according to the image processing detection results of the product appearance, the alarm indicator light can be triggered to prompt an abnormality. These external indicator lights can intuitively reflect the operating status and test results of the test system. The operator can observe these indicator lights in real time and grasp the progress of the test process. When a fault or abnormality occurs, the alarm indicator light can also prompt in time, which helps to quickly locate the problem. The visualization and process feedback of the entire test process are conducive to improving the operability and reliability of the test system.

[0051] In some embodiments, a first control circuit, a second control circuit, and a third control circuit are included between the processing chip and the FPGA circuit;

[0052] The first control circuit is used to respond to the reset button on the IO panel 130, which is connected to the FPGA circuit 121. When the user presses the reset button, the circuit sends a reset instruction to the FPGA circuit 121. After receiving the reset instruction, the FPGA circuit 121 transmits the reset signal to the processing chip 111 through the first control circuit, thereby implementing the reset operation of the processing chip 111. This hardware reset mechanism based on the reset button provides a simple and direct reset method for testing the main control system 100. The user only needs to press the reset button on the IO panel 130 to quickly reset the entire system without complicated operations through software or other methods.

[0053] The second control line is based on a synchronous serial communication protocol (SPI), and is used for data exchange and configuration control between the processing chip 111 and the FPGA circuit 121. The SPI bus usually consists of four lines:

[0054] SCLK-serial clock signal;

[0055] MOSI - master device output, slave device input;

[0056] MISO-master input, slave output;

[0057] CS-chip select signal;

[0058] Through these four lines, the processing chip 111, as a master device, can send various configuration instructions and control signals to the FPGA circuit 121 (as a slave device). At the same time, the FPGA circuit 121 can also feed back operating data and status information to the processing chip 111. This SPI-based two-way data interaction mechanism enables the processing chip 111 to flexibly configure and control the FPGA circuit 121. For example, the processing chip 111 can download the FPGA configuration file of the FPGA circuit 121 through the SPI bus, or adjust the working parameters of the FPGA circuit 121 in real time. At the same time, the FPGA circuit 121 can also use the SPI bus to report test data, operating status and other information to the processing chip 111. The SPI communication mechanism of the second control line provides an efficient and reliable interface for data exchange and configuration control between the processing chip 111 and the FPGA circuit 121. This close collaboration at the hardware level is conducive to improving the overall performance of the test main control system 100.

[0059] The third control line is based on a bidirectional serial communication bus protocol (SMBus) and is used for the processing chip 111 to monitor the working status of the FPGA circuit 121 .

[0060] SMBus is a simple, low-power two-wire bus protocol, which is usually used to transmit status information and control instructions between master devices and slave devices. As the master device, the processing chip 111 regularly reads the operating parameters of the FPGA circuit 121, such as temperature, power consumption, etc., through the SMBus. These status information can help the processing chip 111 to timely understand the working status of the FPGA circuit 121, and provide a basis for system monitoring and fault diagnosis. In addition, the FPGA circuit 121 also establishes a connection with the PCIe panel 140 through the SMBus. This enables the FPGA circuit 121 to upload the various test data it collects to the PCIe panel 140 through the SMBus and send it to the subsequent analysis equipment for further analysis.

[0061] In some embodiments, the processing chip 111 is connected to the memory module via a memory bus in the interface circuit, and the processing chip 111 is also connected to the onboard storage hard disk via a SATA 3.0 interface.

[0062] Among them, the memory bus is a high-speed, parallel bus protocol used to process data exchange between the chip and the memory module. Through the memory bus, the processing chip can quickly read or write various data in the memory module (such as LPDDR4, eMMC), providing sufficient temporary storage space for the system. This connection method based on the memory bus can maximize the performance of the processing chip and the memory module and improve the operating efficiency of the entire system. SATA3.0 is a high-speed serial ATA interface standard, which is widely used in the connection of computer hard disk drives. The SATA3.0 interface can achieve high-speed data transmission between the processing chip and the onboard storage hard disk, providing a large-capacity permanent storage space for the test main control system 100, which can be used to save various test data, configuration parameters and other important information. At the same time, the processing chip can also quickly read or write data in the hard disk through the SATA3.0 interface to meet the high-performance storage requirements of the system.

[0063] like Figure 3 As shown, in some embodiments, the IO panel 130 provided by the embodiment of the utility model also includes a display interface DP, a display interface HDMI, a network interface GE1, a network interface GE2, and a communication interface COM. The above interfaces are connected to the processing chip 111 through an interface circuit. Among them, the communication interface COM can support RS-232, RS-422 and RS-485 interface communications through software configuration.

[0064] In some embodiments, the USB interface includes a USB2.0 interface and a USB3.0 interface. A USB expansion chip is also provided on the interface circuit between the USB2.0 interface and the processing chip 111. USB3.0 supports firmware upgrade download. Through this interface, the firmware of the processing chip 111 can be conveniently upgraded and updated, thereby ensuring functional stability, maintainability and security.

[0065] These interfaces provide devices with multiple connection and display output functions, and can perform data transmission and control with the processing chip. The design of the USB interface adopts the coexistence of USB2.0 and USB3.0 to meet the connection requirements of different devices. By integrating a variety of external interfaces, the entire system is provided with good scalability and compatibility.

[0066] like Figure 2As shown, the IO panel also includes a trigger signal interface (TRIG). The TRIG interface can be used to receive trigger signal inputs from external devices. These trigger signals can be used to synchronize the actions or data acquisition of the test system. As a trigger signal input interface, the TRIG interface inputs the trigger signal of the external device into the synchronization control module inside the FPGA. This synchronization control module is responsible for coordinating the actions and data acquisition of the entire test system, and is connected and synchronized with the PCIe panel 140 through the trigger bus. This design can achieve synchronous operation between the test system and external devices, improve the coordination of the test process and the accuracy of data acquisition. The TRIG interface plays an important role in the synchronization control of the entire test system.

[0067] In some embodiments, the trigger signal interface uses a front SMB connector, which can make the interface more compact and reliable, and more convenient to connect with various devices.

[0068] like Figure 4 As shown, Figure 4 This is a structural diagram of the test main control system provided in the embodiment of the present application. In some embodiments, the gusset module 110 and the baseboard module 120 can be connected using a first board-to-board connector 150 with a height of 5 mm, the IO panel 130 is set on the interface board 131, and the interface board 131 and the baseboard module 120 can be connected through a second board-to-board connector 160 with a height of 2.5 cm. Among them, the number of the first board-to-board connector 150 and the second board-to-board connector 160 is not limited in the embodiment of the present application.

[0069] like Figure 5 As shown, in some embodiments, an SSD solid state drive slot 170 is provided on the surface opposite to the connection surface of the base plate module 120 and the gusset plate module 110. By providing the SSD slot 170 on the base plate module 120, the SSD solid state drive can be easily installed and replaced, providing a high-speed data storage function for the entire test system. The SSD hard drive is integrated on the base plate module 120, which is conducive to shortening the distance of data transmission within the system and improving the efficiency of data access.

[0070] By using the solution of the utility model patent, it is possible to make up for the problem of insufficient high-computing and high-real-time testing needs of products in various fields; its low power consumption and low cost effectively reduce the application scenario requirements and costs of the overall automated testing equipment.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the utility model, rather than to limit it. Although the utility model has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. These modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the utility model, and they should all be included in the scope of the claims and specification of the utility model.

Claims

1. A test control system based on PCIe, characterized in that: The test main control system is applied to a PXI chassis, the PXI chassis includes a PCIe panel and an IO panel, the IO panel includes a GPIB interface for communicating with a device under test, the PCIe panel includes a PCIe interface for data transmission, and the test main control system includes: A baseboard module, comprising an FPGA circuit, wherein the FPGA circuit is connected to an interface on the PCIe panel or the IO panel via an interface circuit preset on the baseboard module; wherein the FPGA circuit is connected to the GPIB interface via a GPIB control bus; The pinch board module includes a processing chip, which is connected to the interface circuit through the chip system circuit on the pinch board module, and then connected to the interface on the PCIe panel or the IO panel; the processing chip is connected to the FPGA circuit to realize control of the test main control system.

2. The test main control system according to claim 1, characterized in that: The processing chip is connected to the PCIe interface on the PCIe panel via a PCIe bus in an interface circuit; wherein a PCIe switching chip is also provided on the PCIe bus, and the PCIe switching chip is used to expand a single-channel PCIe interface into a multi-channel PCIe interface.

3. The test main control system according to claim 2, characterized in that: The baseboard module also includes a clock buffer chip, which is respectively connected to the processing chip and the PCIe switching chip through the interface circuit. The clock buffer chip is also connected to each channel of the multi-channel PCIe interface. The clock buffer chip is used to provide a clock signal for the processing chip and the PCIe switching chip.

4. The test main control system according to claim 1, characterized in that: The processing chip includes an embedded neural network processing unit and an image processing unit. The neural network processing unit is used to intelligently analyze and process parameter data of the device under test, and the image processing unit is used to analyze and process image data of the device under test.

5. The test main control system according to claim 1, characterized in that: The IO panel also includes an external indicator light interface, and the external indicator light is connected to the FPGA circuit through the interface circuit. The external indicator light includes a power indicator light, a storage status indicator light, a programmable indicator light, and an alarm indicator light.

6. The test main control system according to claim 1, characterized in that: The processing chip and the FPGA circuit include a first control circuit, a second control circuit and a third control circuit; The first control circuit is used to respond to a reset button on the IO panel, the reset button is connected to the FPGA circuit, and is used to reset the processing chip; The second control circuit is based on a synchronous serial communication protocol and is used for data exchange and configuration control between the processing chip and the FPGA circuit; The third control circuit is based on a bidirectional serial communication bus protocol and is used by the processing chip to monitor the working status of the FPGA circuit.

7. The test main control system according to claim 1, characterized in that: The processing chip is connected to the memory module via the memory bus in the interface circuit, and the processing chip is also connected to the onboard storage hard disk via the SATA 3.0 interface.

8. The test main control system according to claim 1, characterized in that: The processing chip is connected to the DP display interface, HDMI display interface, network interface, USB interface and communication interface of the IO panel through the interface circuit; wherein, the USB interface includes a USB2.0 interface and a USB3.0 interface, and the interface circuit between the USB2.0 interface and the processing chip is also provided with a USB expansion chip.

9. The test main control system according to claim 1, characterized in that: The gusset plate module is connected to the base plate module by using a first board-to-board connector, the IO panel is arranged on an interface board, and the interface board is connected to the base plate module by using a second board-to-board connector.

10. The test main control system according to claim 7, characterized in that: An SSD solid state hard disk slot is provided on the surface opposite to the connection surface of the base plate module and the gusset plate module.

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