Multi-path staggered parallel Helic inverter current sharing control system

Abstract

The utility model discloses a multi-path interleaved parallel Helic inverter current sharing control system, which comprises a plurality of paths of interleaved parallel Helic inverters, and a DC bus input end is provided with a DC bus total voltage sampling unit and a DC bus total filter capacitor in parallel; the alternating current output end is connected in parallel with an inversion output total capacitor, and the inversion output total capacitor is connected in parallel with an inversion voltage sampling unit; the structures of the inverter circuits of the Herac inverters are the same; all the Heric inverters share an outer loop control driving signal; and the carrier phases of the inner ring driving signals of all paths of the Heric inverters are different from one another. The large-power grid-connected and off-grid charging and discharging function can be achieved, due to the fact that the Herac inverter of the Herac topological circuit structure is adopted, common-mode current is smaller during grid connection, and use of a user is safer.

Description

Technical Field

[0001] The utility model belongs to the technical field of grid-connected and off-grid inverter control in energy storage equipment, and specifically relates to a multi-path staggered parallel Heric inverter current sharing control system. Background Art

[0002] As a supporting system for household microgrids, energy storage systems need to meet the requirements of smoothing power fluctuations and improving the quality of grid power. The single-phase grid-connected and off-grid converter in the energy storage system is the interface between the energy storage system and the household microgrid. The quality of its control performance is directly related to the safety performance, stability performance and efficient operation of the household microgrid. Traditional isolated inverters are generally electrically isolated by their own transformers, which reduces the system control efficiency and makes the hardware equipment large and bulky. With the development of science and technology, social progress and the improvement of production and living standards, after optimization and improvement of the design, the new transformerless photovoltaic grid-connected inverter in the existing technology has improved efficiency, reduced size and reduced weight to a certain extent, but it is easy to generate common-mode leakage current, which is potentially harmful to personal safety.

[0003] Conventional single-phase grid-connected and off-grid inverters in the prior art generally adopt a single full-bridge solution. Although it has the characteristics of small size and easy to implement in the direction of software control, its power is also limited by the volume of components and cannot meet the requirements of high-power use. Multiple inverters are directly connected in parallel on the inverter by parallel connection, and merged into one through the bridge arm inductance. The switch tubes at the corresponding position of each inverter are driven by the same waveform signal, that is, a simple functional parallel connection is realized. Although the control is simple, the ripple current of the total bridge arm will increase, and the harmonics will also increase; and when a single inverter bears the same power, the more the number of inverters, the more its ripple and harmonics increase. Directly adopting a multi-inverter parallel connection method, since each inverter has hardware differences, although all bridge arms input the same drive signal, there will be current differences, and long-term use may easily cause a certain device to be damaged prematurely; even if a coupling inductor is added to the parallel bridge arm for hardware current sharing, the hardware current sharing belongs to passive current sharing, and the current sharing effect is poor, and the equipment cost and volume are also increased. Utility Model Content

[0004] In order to solve the above-mentioned problems existing in the prior art, the purpose of the utility model is to provide a multi-path staggered parallel Heric inverter current sharing control system, which controls the current sharing of each inverter bridge arm through a software control algorithm without adding a coupled inductor, thereby reducing the ripple current output, reducing the inductor volume, realizing the grid-connected and off-grid functions and effectively resisting the grid-connected common-mode current, improving the safety factor while meeting the stable performance requirements. The overall equipment and components are stable and reliable, and have a long service life.

[0005] The technical solution adopted by the utility model is:

[0006] The first technical solution provides a multi-path staggered parallel Heric inverter current sharing control system, comprising a plurality of paths of Heric inverters staggered in parallel between a DC bus input terminal and an AC output terminal, wherein a DC bus total voltage sampling unit and a DC bus total filter capacitor are arranged in parallel at the DC bus input terminal;

[0007] The AC output terminal is provided with an inverter output total capacitor in parallel, and an inverter voltage sampling unit is provided in parallel on the inverter output total capacitor;

[0008] The inverter circuit structure of each Heric inverter is the same; all Heric inverters share an outer loop control drive signal;

[0009] The carrier phases of the inner loop driving signals of each Heric inverter are different from each other.

[0010] Furthermore, it includes N Heric inverters that are staggered and connected in parallel, and the inner loop carrier phases of the driving signals of each Heric inverter differ by 360° / N in sequence; N≥2.

[0011] Furthermore, each of the Heric inverters includes an inverter bridge arm, one end of all the inverter bridge arms are connected in parallel and then connected to the DC bus input end via a DC bus total voltage sampling unit, and the other end of all the inverter bridge arms are connected in parallel and then connected to the AC output end via an inverter output total capacitor.

[0012] Furthermore, the upper and lower bridge arms of each Heric inverter are respectively connected to bridge arm inductors, and device parameters of all switch tubes and bridge arm inductors of each Heric inverter are the same.

[0013] Furthermore, each of the Heric inverters is provided with six switch tubes; the first inverter switch tube, the second inverter switch tube, the third inverter switch tube and the fourth inverter switch tube of each of the Heric inverters form a full-bridge circuit, and the fifth inverter switch tube and the sixth switch are respectively connected in series between the upper bridge arm and the lower bridge arm of each of the Heric inverter full-bridge circuits;

[0014] The upper bridge arm and the lower bridge arm of each Heric inverter are connected in series with the bridge arm inductor respectively, and then connected to the two ends of the inverter output total capacitor.

[0015] Furthermore, the upper bridge arm inductor of each Heric inverter is respectively connected in series with an inverter inductor current sampling unit.

[0016] Furthermore, the driving waveforms of the first inverter switch tube and the fourth inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the first inverter switch tube is complementary to the driving waveform of the fifth inverter switch tube, and are respectively provided with a neutral zone;

[0017] The driving waveforms of the second inverter switch tube and the third inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the second inverter switch tube is complementary to the driving waveform of the sixth inverter switch tube, and are respectively provided with a neutral zone;

[0018] The carrier timing of all the switch tubes of each Heric inverter is the same;

[0019] The wave generation logic of all the switch tubes of each Heric inverter is the same.

[0020] Furthermore, the two ends of the inverter output total capacitor are connected in series with the inverter relays respectively, and then connected in parallel to the grid end and the load end;

[0021] The grid end is provided with a grid relay; the load end is provided with a load relay.

[0022] Finally, the AC output end is also provided with a grid voltage sampling unit and a load current sampling unit in parallel.

[0023] The beneficial effects of the utility model are:

[0024] A multi-channel staggered parallel Heric inverter current sharing control system includes several Heric inverters staggered in parallel between the DC bus input and AC output, the DC bus input is connected in parallel with a DC bus total voltage sampling unit and a DC bus total filter capacitor; the AC output is connected in parallel with an inverter output total capacitor, and an inverter voltage sampling unit is connected in parallel on the inverter output total capacitor; the inverter circuit structure of each Heric inverter is the same; all Heric inverters share an outer loop control drive signal; the carrier phase of the inner loop drive signal of each Heric inverter is different. It can realize high-power on-grid and off-grid charging and discharging functions. Due to the Heric inverter with a Heric topology circuit structure, the common mode current is smaller when connected to the grid, and it is safer for users to use. Due to the use of multi-inverter staggered parallel mode, the carrier phase of each inverter is evenly phase-shifted by 360° / N, and the inductor current ripple is reduced by N times compared with the ordinary parallel mode. The inductor can be made smaller, and the software-controlled active current sharing method can reduce N coupled inductors, so the volume can be made smaller. At the same time, the current imbalance caused by the difference in hardware parameters of each inverter is eliminated, the heat is more uniform, the service life is longer, and the operation is more reliable; because the loop adopts PR+ repeated control, the off-grid voltage THD is smaller, which is more friendly to off-grid electrical appliances, the grid-connected current harmonics are also smaller, and the grid-connected PF power factor is higher, so the quality of the grid-connected current is better, which can reduce the pollution to the power grid. Through the software control algorithm, the current sharing control of each inverter bridge arm without adding coupled inductors can reduce the ripple current output, reduce the inductor volume, realize the off-grid function and effectively resist the grid-connected common mode current, improve the safety factor and meet the stable performance requirements, and the overall equipment and components are stable and reliable with a long service life. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0026] Figure 1 This is a schematic diagram of the circuit structure principle of the multi-path staggered parallel Heric inverter current sharing control system of the utility model;

[0027] Figure 2 This is a schematic diagram of the circuit structure principle of a multi-path staggered parallel Heric inverter current sharing control system of the first embodiment of the utility model;

[0028] Figure 3This is a schematic diagram of a control loop flow of a multi-path staggered parallel Heric inverter current sharing control system in an off-grid state according to a first embodiment of the utility model;

[0029] Figure 4 This is a schematic diagram of a control loop flow of a multi-path staggered parallel Heric inverter current sharing control system in a grid-connected state according to a first embodiment of the utility model;

[0030] Figure 5 It is a driving timing diagram of a multi-path staggered parallel Heric inverter current sharing control system of the first embodiment of the utility model. DETAILED DESCRIPTION

[0031] The utility model is further described in detail below in conjunction with the accompanying drawings.

[0032] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0033] like Figures 1 to 5 As shown, in order to provide a multi-path staggered parallel Heric inverter current sharing control system, the overall planning scheme is: In order to comply with the development trend of cutting-edge new technologies and new products in the industry, the research found that the existing technology has the following defects:

[0034] 1. As the support of household microgrids, energy storage systems play a role in smoothing power fluctuations and improving the power quality of the grid. Among them, the single-phase grid-connected and off-grid converter serves as the interface between the energy storage system and the household microgrid. The quality of its control strategy is related to the safe, stable and efficient operation of the household microgrid. However, traditional isolated inverters generally have their own transformers for electrical isolation, which reduces system efficiency and increases volume and weight. The new transformerless photovoltaic grid-connected inverter with higher efficiency, smaller volume and weight also has disadvantages, that is, the common-mode leakage current it has poses a potential threat to personal safety. Therefore, the Heric single-phase inverter that can effectively suppress common-mode current is proposed as a research object.

[0035] 2. Ordinary single-phase grid-connected and off-grid inverters generally adopt a single full-bridge solution. Although software control is easy to implement, the power cannot be increased due to limitations such as device size. However, if multiple inverters are connected in parallel, power amplification can be achieved and multiple devices can share the harsh conditions.

[0036] 3. The commonly used parallel connection method is to connect multiple inverters in parallel to the original inverter, and merge them into one through the bridge arm inductance. The corresponding position tubes of each inverter have the same driving waveform, that is, to achieve simple functional parallel connection. Although this method is simple to control, it will increase the total bridge arm ripple current and harmonics. Moreover, when a single inverter bears the same power, the current ripple harmonics will be further increased according to the increase in the number of inverters.

[0037] 4. Conventionally, multiple inverters are connected in parallel, but in fact, each inverter has hardware differences. Even if all bridge arms send the same drive, there will always be current differences. Long-term use may cause premature damage to a certain device. Generally, coupled inductors are added to the parallel bridge arms to perform hardware current balancing. However, this current balancing is passive, with poor current balancing effect, and will also increase cost and volume.

[0038] The utility model specifically plans to develop a multi-path staggered parallel Heric inverter current sharing control system. The first technical solution provides a multi-path staggered parallel Heric inverter current sharing control system. The first technical solution provides a multi-path staggered parallel Heric inverter current sharing control method.

[0039] The first technical solution provides a multi-path staggered parallel Heric inverter current sharing control system, which is provided with a plurality of staggered parallel Heric inverters (hereinafter referred to as inverters, or inverter circuits), and the plurality of Heric inverters are connected in parallel between the DC bus input terminal and the AC output terminal; a DC bus total voltage sampling unit and a DC bus total filter capacitor are arranged in parallel at the DC bus input terminal; an inverter output total capacitor is arranged in parallel at the AC output terminal, and an inverter voltage sampling unit is arranged in parallel on the inverter output total capacitor.

[0040] The inverter circuit structure of each Heric inverter is the same; the Heric inverters share an outer loop control drive signal, that is, all inverters share one outer loop, and their inner loops are different; the carrier phase of the inner loop drive signal of each Heric inverter is different.

[0041] The number of Heric inverters arranged in parallel and staggered is defined as N, and the inner loop carrier phases of the driving signals of each Heric inverter differ by 360° / N in sequence; N≥2.

[0042] Furthermore, each Heric inverter is provided with an inverter bridge arm, one end of all the inverter bridge arms are connected in parallel and then connected to the DC bus input end via a DC bus total voltage sampling unit, and the other end of all the inverter bridge arms are connected in parallel and then connected to the AC output end via an inverter output total capacitor.

[0043] The upper and lower bridge arms of each Heric inverter are respectively connected with bridge arm inductors, and the device parameters of all switch tubes and bridge arm inductors of each Heric inverter are the same.

[0044] Specifically, each Heric inverter is provided with six switch tubes; the first inverter switch tube, the second inverter switch tube, the third inverter switch tube and the fourth inverter switch tube of each Heric inverter form a full-bridge circuit, and the fifth inverter switch tube and the sixth switch are connected in series between the upper bridge arm and the lower bridge arm of each Heric inverter full-bridge circuit; the upper bridge arm and the lower bridge arm of each Heric inverter are connected in series with the bridge arm inductor, and then connected to the two ends of the inverter output total capacitor. The inverter inductor current sampling unit is connected in series with the upper bridge arm inductor of each Heric inverter.

[0045] Furthermore, the driving waveforms of the first inverter switch tube and the fourth inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the first inverter switch tube is complementary to the driving waveform of the fifth inverter switch tube, and are respectively provided with a neutral zone, i.e., a dead zone; thereby, the upper and lower switch tubes of the same bridge arm are respectively provided with a dead zone to prevent short circuit conduction and ensure the safety factor.

[0046] The driving waveforms of the second inverter switch tube and the third inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the second inverter switch tube and the driving waveform of the sixth inverter switch tube are complementary, and neutral zones, i.e., dead zones, are respectively set.

[0047] The carrier timing of all the switching tubes of each Heric inverter is the same, which is a triangular wave of a certain frequency. The carrier frequency can be set according to the frequency of the switching tube.

[0048] The wave generation logic of all the switch tubes of each Heric inverter is different; Figure 5 As shown, in the positive half cycle of the sine wave, the second inverter switch tube A2 and the third inverter switch tube A3 emit a low level, and the sixth inverter switch tube A6 emits a high level. When the modulation wave is greater than the carrier, the first inverter switch tube A1 and the fourth inverter switch tube A4 emit a high level, and the fifth inverter switch tube A5 emits a low level. In the negative half cycle of the sine wave, the first inverter switch tube A1 and the fourth inverter switch tube A4 emit a low level, and the fifth inverter switch tube A5 emits a high level. When the modulated wave is greater than the carrier wave, the second inverter switch tube A2 and the third inverter switch tube A3 send a high level, and the sixth inverter switch tube A6 sends a low level; the first inverter switch tube A1 and the fourth inverter switch tube A4 send the same signal, and form a complementary signal with the fifth inverter switch tube A5, and have a dead zone; the second inverter switch tube A2 and the third inverter switch tube A3 send the same signal, and form a complementary signal with the sixth inverter switch tube A6, and have a dead zone.

[0049] Finally, the two ends of the inverter output total capacitor are connected in series with the inverter relays, and then connected in parallel to the grid end and the load end; two grid relays are set at the grid end; two load relays are set at the load end. A grid voltage sampling unit and a load current sampling unit are also set in parallel at the AC output end.

[0050] Specifically, a multi-channel staggered parallel Heric inverter current sharing control system of the first technical solution is provided with a DC bus input DC, a DC bus total voltage sampling, a DC bus total filter capacitor C_in, N-channel staggered parallel Heric inverters A inverter ~ N inverters, an inverter output total capacitor C_out, an inverter relay, a load relay, and a grid relay;

[0051] N Heric inverters connected in parallel are defined as the first Heric inverter A, the second Heric inverter B, and the Nth Heric inverter N. Each Heric inverter is provided with six switch tubes; that is:

[0052] The first Heric inverter A is provided with a first inverter switch tube A1, a second inverter switch tube A2, a third inverter switch tube A3, a fourth inverter switch tube A4, a fifth inverter switch tube A5 and a sixth inverter switch tube A6, a total of six switch tubes; the upper bridge arm of the first Heric inverter A is connected to the first upper bridge arm inductor L_A1, the lower bridge arm is connected to the first lower bridge arm inductor L_A2, and the first inverter inductor current sampling unit is connected in series to the first upper bridge arm inductor L_A1;

[0053] The second Heric inverter B is provided with a first inverter switch tube B1, a second inverter switch tube B2, a third inverter switch tube B3, a fourth inverter switch tube B4, a fifth inverter switch tube B5 and a sixth inverter switch tube B6, a total of six switch tubes; the upper bridge arm of the second Heric inverter B is connected to the second upper bridge arm inductor L_B1, the lower bridge arm is connected to the second lower bridge arm inductor L_B2, and the second inverter inductor current sampling unit is connected in series to the second upper bridge arm inductor L_B1;

[0054] …

[0055] The Nth Heric inverter N is provided with a first inverter switch tube N1, a second inverter switch tube N2, a third inverter switch tube N3, a fourth inverter switch tube N4, a fifth inverter switch tube N5 and a sixth inverter switch tube N6, a total of six switch tubes; the upper bridge arm of the Nth Heric inverter N is connected to the Nth upper bridge arm inductor L_N1, the lower bridge arm is connected to the Nth lower bridge arm inductor L_N2, and the Nth inverter inductor current sampling unit is connected in series to the Nth upper bridge arm inductor L_N1.

[0056] The input ends of all inverter AN circuits are connected in parallel to both ends of the DC bus capacitor; the inverters AN all use the same Heric inverter connection method; the upper bridge arm inductance output of all AN inverters is connected in parallel to the upper end of the total inverter filter capacitor, and the lower bridge arm inductance output is connected in parallel to the lower end of the total inverter filter capacitor. Each inverter has its own bridge arm inductance, and no additional devices are required. The AN inverter circuit structure is the same, and the carrier phase difference of each bridge arm drive signal is 360° / N, and N is greater than or equal to 2;

[0057] Among them, the AN inverter structure and device parameters such as switch tubes and inverter inductors are the same, which makes it easier and more convenient to design and build the platform. At the same time, each inverter can maintain the same current size during operation, which makes it easier to achieve current sharing.

[0058] Further, the driving waveform of the first inverter switch tube A1 of inverter A is consistent with that of the fourth inverter switch tube A4, and is complementary to that of the fifth inverter switch tube A5 with a dead zone; the driving waveform of the second inverter switch tube A2 is consistent with that of the third inverter switch tube A3, and is complementary to that of the sixth inverter switch tube A6 with a dead zone; the subcarrier timing of all tubes of the same inverter is the same. When the sine is in the positive half cycle, A1\A4\A5 is high-frequency, A2\A3 is low, and A6 is high; when the sine is in the negative half cycle, A2\A3\A6 is high-frequency, A1\A4 is low, and A5 is high.

[0059] Furthermore, the wave generation logic of the six switch tubes of each inverter of AN is the same, except that the carrier of each inverter differs by 360° / N;

[0060] Furthermore, if all inverters share a software control loop, the current of each inverter will be unbalanced due to hardware parameter errors, so the utility model adopts the method of outer loop sharing and inner loop independent control to achieve software active current sharing;

[0061] Furthermore, when the system is working in an off-grid state, the outermost loop is the inverter voltage effective value loop, which is used to stabilize the voltage effective value and belongs to the slow loop. Then the inverter voltage instantaneous loop uses PR+ repetitive control to track the sine wave. Finally, the inverter current loop of each branch is used to control the current and also has the function of current balancing, which can realize the high-power off-grid load function.

[0062] Furthermore, when the inverter is running in the grid-connected state, the outer loop is the bus voltage loop used to stabilize the bus voltage and control the charging and discharging functions, and the inner loop is the branch current loop of each inverter. Using PR+ repeated control, the functions of current sharing and grid voltage tracking can be achieved;

[0063] Furthermore, the inverter realizes the active current sharing function of staggered parallel connection of multiple inverters for high-power on-grid and off-grid charging and discharging.

[0064] The second technical solution of the utility model provides a current sharing control method for multi-path staggered parallel inverters, which is specifically performed according to the following operation steps:

[0065] When the system is working in an off-grid state, the control system uses the inverter voltage effective value loop as the outer loop control drive signal to output a stable voltage effective value; the inverter voltage instantaneous loop repeatedly controls the drive signal according to PR+ to track the sine wave; each Heric inverter implements current sharing control according to the corresponding inverter current loop drive signal;

[0066] When the system is working in the grid-connected state, the control system uses the DC bus voltage signal as the outer loop control drive signal to output a stable bus voltage, thereby realizing stable charging and discharging functions; using the branch current loop of each Heric inverter as the inner loop control drive signal, using the PR+ repetitive controller, it can realize current sharing control and track the grid voltage.

[0067] The utility model discloses a multi-channel staggered parallel Heric inverter current sharing control system and control method, comprising a plurality of Heric inverters staggered in parallel between the DC bus input and the AC output, wherein the DC bus input is provided with a DC bus total voltage sampling unit and a DC bus total filter capacitor in parallel; the AC output is provided with an inverter output total capacitor in parallel, and an inverter voltage sampling unit is provided in parallel on the inverter output total capacitor; the inverter circuit structure of each Heric inverter is the same; all Heric inverters share an outer loop control drive signal; the carrier phase of the inner loop drive signal of each Heric inverter is different from each other. It can realize high-power on-grid and off-grid charging and discharging functions, and because the Heric inverter adopts the Heric topology circuit structure, the common mode current is smaller when connected to the grid, and it is safer for users to use. Due to the use of multi-inverter staggered parallel mode, the carrier phase of each inverter is evenly phase-shifted by 360° / N, and the inductor current ripple is reduced by N times compared with the ordinary parallel mode. The inductor can be made smaller, and the software-controlled active current sharing method can reduce N coupled inductors, so the volume can be made smaller. At the same time, the current imbalance caused by the difference in hardware parameters of each inverter is eliminated, the heat is more uniform, the service life is longer, and the operation is more reliable; because the loop adopts PR+ repeated control, the off-grid voltage THD is smaller, which is more friendly to off-grid electrical appliances, the grid-connected current harmonics are also smaller, and the grid-connected PF power factor is higher, so the quality of the grid-connected current is better, which can reduce the pollution to the power grid. Through the software control algorithm, the current sharing control of each inverter bridge arm without adding coupled inductors can reduce the ripple current output, reduce the inductor volume, realize the off-grid function and effectively resist the grid-connected common mode current, improve the safety factor and meet the stable performance requirements, and the overall equipment and components are stable and reliable with a long service life.

[0068] Embodiment 1 According to the first technical solution of the utility model, a multi-path staggered parallel Heric inverter current sharing control system is first provided.

[0069] The specific technical solution of embodiment 1 is as follows:

[0070] The multi-channel staggered parallel Heric inverter current sharing control system of the first embodiment is staggered in parallel to set two Heric inverters: inverter A and inverter B, and each Heric inverter is respectively provided with six switch tubes; the first inverter switch tube, the second inverter switch tube, the third inverter switch tube and the fourth inverter switch tube of each Heric inverter constitute a full-bridge circuit, and the fifth inverter switch tube and the sixth switch are respectively connected in series between the upper bridge arm and the lower bridge arm of each Heric inverter full-bridge circuit; the upper bridge arm and the lower bridge arm of each Heric inverter are respectively connected in series with the bridge arm inductor, and then connected to the two ends of the inverter output total capacitor. The inverter inductor current sampling unit is respectively connected in series with the upper bridge arm inductor of each Heric inverter.

[0071] The actual settings include DC bus input DC, DC bus total voltage sampling, DC bus total filter capacitor C_in, two staggered parallel Heric inverters A inverter and B inverter, inverter output total capacitor C_out, inverter relay, load relay and grid relay.

[0072] The two Heric inverters connected in parallel are defined as the first Heric inverter A and the second Heric inverter B; each Heric inverter is provided with six switch tubes; that is:

[0073] The first Heric inverter A is provided with a first inverter switch tube A1, a second inverter switch tube A2, a third inverter switch tube A3, a fourth inverter switch tube A4, a fifth inverter switch tube A5 and a sixth inverter switch tube A6, a total of six switch tubes; the upper bridge arm of the first Heric inverter A is connected to the first upper bridge arm inductor L_A1, the lower bridge arm is connected to the first lower bridge arm inductor L_A2, and the first inverter inductor current sampling unit is connected in series to the first upper bridge arm inductor L_A1;

[0074] The second Heric inverter B is provided with a first inverter switch tube B1, a second inverter switch tube B2, a third inverter switch tube B3, a fourth inverter switch tube B4, a fifth inverter switch tube B5 and a sixth inverter switch tube B6, a total of six switch tubes; the upper bridge arm of the second Heric inverter B is connected to the second upper bridge arm inductor L_B1, the lower bridge arm is connected to the second lower bridge arm inductor L_B2, and the second inverter inductor current sampling unit is connected in series to the second upper bridge arm inductor L_B1;

[0075] The input ends of all inverter circuits are connected in parallel to both ends of the DC bus capacitor; inverter A and inverter B are both connected in the same Heric inverter method; the upper bridge arm inductor outputs of all inverters are connected in parallel to the upper end of the total inverter filter capacitor, and the lower bridge arm inductor outputs are connected in parallel to the lower end of the total inverter filter capacitor. Each inverter has its own bridge arm inductor and does not require additional devices. A has the same structure as the inverter circuit, and the carrier phase of each bridge arm drive signal differs by 360° / 2, that is, 180°.

[0076] The specific operation process of the first embodiment is as follows:

[0077] When the system is working in an off-grid state, a DC voltage value greater than or equal to the peak-to-peak value of the inverter output sine wave is applied to the DC bus input end, the input inverter voltage effective value is given, and the inverter voltage effective value sampling data is calculated (that is, the instantaneous inverter voltage value is sampled in real time, thereby calculating the inverter voltage effective value of one power frequency cycle, and the inverter voltage effective value adjustment interval is one power frequency cycle). The system controls the inverter voltage effective value (the frequency is adjusted once for one power frequency cycle), and the inverter voltage effective value loop output value is multiplied by the Sin (a unit sine value input manually, whose angle steps in real time between 0 and 360 degrees according to the switching frequency, and the amplitude is one) input data as the given of the inverter voltage instantaneous value loop, and is subtracted from the real-time feedback inverter voltage sampling data. The result is controlled by the outer loop (that is, the inverter voltage instantaneous value loop) PR+ repetitive controller for limiting adjustment, so that the phase difference of the drive signal carrier of each bridge arm is 360° / 2, that is, 180°.

[0078] The first inverter inductor current sampling unit connected in series with the first upper bridge arm inductor L_A1 of the first Heric inverter A collects the real-time current value of the first Heric inverter A and feeds it back to the first PI controller of the first Heric inverter A; and 1 / 2 of the real-time load current value collected by the load current sampling unit is also fed back to the first PI controller of the first Heric inverter A; PI control and limit adjustment are performed through the first PI controller of the first Heric inverter A.

[0079] Combined with the inverter power sampling value (that is, the maximum count value of the controller switching cycle, the write value of 100% duty cycle inside the relevant controller chip) and the DC bus voltage sampling data information (the sampling information value of the device DC bus capacitor), a feedforward modulation operation is performed; finally, the first bridge arm modulation signal of the first Heric inverter A is formed, thereby adjusting the drive control signals of the first inverter switch tube A1, the second inverter switch tube A2, the third inverter switch tube A3, the fourth inverter switch tube A4, the fifth inverter switch tube A5 and the sixth inverter switch tube A6 of the first Heric inverter A.

[0080] The second inverter inductor current sampling unit connected in series with the second upper bridge arm inductor L_B1 of the second Heric inverter B collects the real-time current value of the second Heric inverter B and feeds it back to the second PI controller of the second Heric inverter B; and 1 / 2 of the real-time load current value collected by the load current sampling unit is also fed back to the second PI controller of the second Heric inverter B; PI control and limit adjustment are performed through the second PI controller of the second Heric inverter B.

[0081] Combined with the inverter power sampling (the maximum count value of the controller switching cycle, that is, the write value of 100% duty cycle inside the relevant controller chip) and the DC bus voltage sampling (the sampling information value of the device DC bus capacitor) data information, a feedforward modulation operation is performed; finally, the second bridge arm modulation signal of the second Heric inverter B is formed, thereby adjusting the drive control signals of the second inverter switch tube B1, the second inverter switch tube B2, the third inverter switch tube B3, the fourth inverter switch tube B4, the fifth inverter switch tube B5 and the sixth inverter switch tube B6 of the second Heric inverter B.

[0082] Thus, the control system uses the inverter voltage effective value loop as the outer loop control driving signal to output a stable voltage effective value; the inverter voltage instantaneous loop repeatedly controls the driving signal according to PR+ to track the sine wave; each Heric inverter implements current sharing control according to the corresponding inverter current loop driving signal.

[0083] When the system works in the grid-connected state, the DC bus voltage set value and the feedback DC bus voltage sampling data information are input to the DC bus input terminal, and the DC bus outer loop PI controller is used to perform PI control operation processing for limiting, and according to the feedback grid Sin and Cos (grid angle information, obtained by phase locking) input data information, and Iq (grid current reactive value, calculated) data information, DQ-Alfha / Beta logic operation processing is performed through Park transformation and Clark transformation; 1 / 2 of the operation result data information is input to the first Heric inverter A and the second Heric inverter B respectively;

[0084] The first PR+ repetitive controller of the first Heric inverter A performs PR+ repetitive control operation and limit adjustment;

[0085] Combined with the switching cycle T data information (the maximum count value of the controller switching cycle, i.e., the write value of 100% duty cycle inside the relevant controller chip) and the DC bus sampling data information (the sampling information value of the device DC bus capacitor), a pre-amplitude modulation operation is performed; finally, the first bridge arm modulation signal of the first Heric inverter A is formed, thereby adjusting the drive control signals of the first inverter switch tube A1, the second inverter switch tube A2, the third inverter switch tube A3, the fourth inverter switch tube A4, the fifth inverter switch tube A5 and the sixth inverter switch tube A6 of the first Heric inverter A.

[0086] The second PR+ repetitive controller of the second Heric inverter B performs PR+ repetitive control operation and limit adjustment;

[0087] Combined with the switching cycle T data information (the maximum count value of the controller switching cycle, i.e., the write value of 100% duty cycle inside the relevant controller chip) and the DC bus sampling data information (the sampling information value of the device DC bus capacitor), a pre-amplitude modulation operation is performed; finally, the second bridge arm modulation signal of the second Heric inverter B is formed, thereby adjusting the drive control signals of the first inverter switch tube B1, the second inverter switch tube B2, the third inverter switch tube B3, the fourth inverter switch tube B4, the fifth inverter switch tube B5 and the sixth inverter switch tube B6 of the second Heric inverter A.

[0088] The control system uses the DC bus voltage signal as the outer loop control drive signal to output a stable bus voltage, thereby achieving stable charging and discharging functions; the branch current loop of each Heric inverter is used as the inner loop control drive signal, and the PR+ repetitive controller is used to achieve current sharing control and track the grid voltage.

[0089] The control system uses the DC bus voltage signal as the outer loop control drive signal to output a stable bus voltage, thereby achieving stable charging and discharging functions; the branch current loop of each Heric inverter is used as the inner loop control drive signal, and the PR+ repetitive controller is used to achieve current sharing control and track the grid voltage.

[0090] The above content is only used to illustrate the technical solution of the utility model rather than to limit it. The utility model is not limited to the above optional implementation modes. Other modifications or equivalent substitutions made to the technical solution of the utility model by ordinary technicians in this field, regardless of any changes in its shape or structure, should be included in the scope of the claims of the utility model as long as they do not depart from the spirit and scope of the technical solution of the utility model.

Claims

1. A multi-path staggered parallel Heric inverter current sharing control system, characterized in that: It comprises a plurality of Heric inverters which are staggered and connected in parallel between a DC bus input terminal and an AC output terminal, wherein a DC bus total voltage sampling unit and a DC bus total filter capacitor are connected in parallel to the DC bus input terminal; The AC output terminal is provided with an inverter output total capacitor in parallel, and an inverter voltage sampling unit is provided in parallel on the inverter output total capacitor; The inverter circuit structure of each Heric inverter is the same; all Heric inverters share an outer loop control drive signal; The carrier phases of the inner loop driving signals of each Heric inverter are different from each other.

2. According to the multi-path staggered parallel Heric inverter current sharing control system of claim 1, it is characterized in that: It comprises N Heric inverters which are staggered and connected in parallel, and the inner loop carrier phases of the driving signals of each Heric inverter differ by 360° / N in sequence; N≥2.

3. According to the multi-path staggered parallel Heric inverter current sharing control system of claim 1, it is characterized in that: Each of the Heric inverters includes an inverter bridge arm. After one end of all the inverter bridge arms are connected in parallel, they are connected to the DC bus input end via a DC bus total voltage sampling unit. After the other ends of all the inverter bridge arms are connected in parallel, they are connected to the AC output end via an inverter output total capacitor.

4. The Heric inverter current sharing control system with multiple staggered parallel connections according to claim 1 is characterized in that: The upper and lower bridge arms of each Heric inverter are respectively connected to bridge arm inductors, and the device parameters of all switch tubes and bridge arm inductors of each Heric inverter are the same.

5. The Heric inverter current sharing control system with multiple staggered parallel connections according to any one of claims 1 to 4, characterized in that: Each of the Heric inverters is provided with six switch tubes; the first inverter switch tube, the second inverter switch tube, the third inverter switch tube and the fourth inverter switch tube of each of the Heric inverters form a full-bridge circuit, and the fifth inverter switch tube and the sixth switch are respectively connected in series between the upper bridge arm and the lower bridge arm of each of the Heric inverter full-bridge circuits; The upper bridge arm and the lower bridge arm of each Heric inverter are connected in series with the bridge arm inductor respectively, and then connected to the two ends of the inverter output total capacitor.

6. The Heric inverter current sharing control system with multiple staggered parallel connections according to claim 5 is characterized in that: The upper bridge arm inductor of each Heric inverter is respectively connected in series with an inverter inductor current sampling unit.

7. The Heric inverter current sharing control system with multiple staggered parallel connections according to claim 5 is characterized in that: The driving waveforms of the first inverter switch tube and the fourth inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the first inverter switch tube is complementary to the driving waveform of the fifth inverter switch tube, and are respectively provided with a neutral zone; The driving waveforms of the second inverter switch tube and the third inverter switch tube of each Heric inverter are consistent with each other, the driving waveform of the second inverter switch tube is complementary to the driving waveform of the sixth inverter switch tube, and are respectively provided with a neutral zone; The carrier timing of all the switch tubes of each Heric inverter is the same; The wave generation logic of all the switch tubes of each Heric inverter is the same.

8. The Heric inverter current sharing control system with multiple staggered parallel connections according to claim 1 is characterized in that: The two ends of the inverter output total capacitor are connected in series with the inverter relay respectively, and then connected in parallel to the grid end and the load end; The grid end is provided with a grid relay; the load end is provided with a load relay.

9. The Heric inverter current sharing control system with multiple staggered parallel connections according to claim 8, characterized in that: The AC output end is also provided with a grid voltage sampling unit and a load current sampling unit in parallel.

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