Integrated circuit structure

Abstract

An integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is arranged above the substrate and comprises a first channel layer, a first gate structure and a plurality of first source / drain epitaxial structures. The first gate structure surrounds the first channel layer. The first source / drain epitaxial structures are arranged on two opposite sides of the first channel layer. The top nanostructure transistor is over the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and a second source / drain epitaxial structure. The second channel layer is over the first channel layer. The second gate structure surrounds the second channel layer. The bottom surface of the second gate structure is coplanar with the bottom surface of the first gate structure. The second source / drain epitaxial structure is disposed on two opposite sides of the second channel layer.

Description

Technical Field

[0001] The present application relates to an integrated circuit structure. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced many generations of ICs, each with smaller and more complex circuits than the previous generation. During the course of IC evolution, functional density (i.e., the number of interconnected elements per wafer area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a process) has decreased. This scaling down process can increase production efficiency and reduce associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances. Utility Model Content

[0003] The integrated circuit structure of the present application solves the technical problems faced by the increase in functional density and the reduction in geometric size of ICs. The integrated circuit structure of the present application is a separate gate structure, which allows independent gate control. In addition, the layout area of ​​the gate structure is substantially the same as that of the shared gate structure, so that the design flexibility of the circuit is increased without increasing the layout area. In addition, the fork-sheet gate structure provides gate control as good as the nanosheet gate structure.

[0004] The present application provides an integrated circuit structure. The integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is above the substrate, wherein the bottom nanostructure transistor includes a first channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first channel layer. The first source / drain epitaxial structure is on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor, wherein the top nanostructure transistor includes a second channel layer, a second gate structure, and a second source / drain epitaxial structure. The second channel layer is above the first channel layer. The second gate structure surrounds the second channel layer, wherein the bottom surface of the second gate structure is coplanar with the bottom surface of the first gate structure. The second source / drain epitaxial structure is on opposite sides of the second channel layer.

[0005] The present application provides an integrated circuit structure. The integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is above the substrate, wherein the bottom nanostructure transistor includes a first channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first channel layer. The first source / drain epitaxial structure is on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor, wherein the top nanostructure transistor includes a second channel layer, a second gate structure, and a second source / drain epitaxial structure. The second channel layer is above the first channel layer. The second gate structure surrounds the second channel layer, wherein the bottom surface of the second gate structure is coplanar with the bottom surface of the first gate structure, and the top surface of the first gate structure is higher than the top surface of the second channel layer. The second source / drain epitaxial structure is on opposite sides of the second channel layer.

[0006] The present application provides an integrated circuit structure. An integrated circuit structure substrate, an isolation structure, a bottom nanostructure transistor and a top nanostructure transistor. The isolation structure is embedded in the substrate. The bottom nanostructure transistor is above the substrate, wherein the bottom nanostructure transistor includes a first gate structure, a first channel layer and a first source / drain epitaxial structure. The first gate structure has a first fork shape. The first channel layer is surrounded by the first gate structure. The first source / drain epitaxial structure is on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor, wherein the top nanostructure transistor includes a second gate structure, a second channel layer and a second source / drain epitaxial structure. The second gate structure has a second fork shape, wherein the first gate structure and the second gate structure both contact the isolation structure, and the first gate structure electrically isolates the second gate structure. The second channel layer is surrounded by the second gate structure. The second source / drain epitaxial structure is on opposite sides of the second channel layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The various aspects of the present application can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be understood that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the sizes of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B and Fig. 21C A perspective view and a cross-sectional view showing intermediate stages of forming an integrated circuit structure (or a semiconductor device) according to some embodiments of the present application;

[0009] Fig. 22 is a schematic cross-sectional view of an integrated circuit structure (or semiconductor device) according to some embodiments of the present application;

[0010] Fig.23 is a circuit diagram of a tri-state buffer logic circuit according to some embodiments of the present application;

[0011] Fig.24 A top view of a tri-state buffer logic circuit according to some embodiments of the present application is shown;

[0012] FIG. 25A to FIG. 25D Draw the diagrams along Fig.24 Schematic cross-sectional view of lines AA, BB, CC and DD;

[0013] Fig.26A and Fig.26B According to some embodiments of the present application, the Fig.24 Schematic cross-sectional view of lines AA and DD.

[0014]

Explanation of symbols

[0015] 10: Three-state buffer logic circuit

[0016] 100a, 100b: semiconductor device / integrated circuit structure

[0017] 102: Groove

[0018] 110: Base material

[0019] 112: Protruding part

[0020] 120: Epitaxial stacking

[0021] 121: Fin structure

[0022] 122,124,126,128: Epitaxial layer / channel layer

[0023] 129: Top surface

[0024] 130: Hard Mask (HM) layer

[0025] 132: Oxide layer

[0026] 134: Nitride layer

[0027] 140: Isolation Structure

[0028] 145: Dummy gate dielectric layer

[0029] 150: Dummy gate structure

[0030] 154: Virtual gate electrode layer

[0031] 156: Oxide layer

[0032] 158: Nitride layer

[0033] 170: Gate spacer

[0034] 170': Dielectric film

[0035] 180: Internal spacer

[0036] 210: Source / drain epitaxial structure

[0037] 215: Source / drain epitaxial structure

[0038] 220: Isolation layer

[0039] 225: Spacer layer

[0040] 230: Contact stop layer (CESL)

[0041] 235: Interlayer dielectric (ILD) layer

[0042] 240: Protective Materials

[0043] 250: Dielectric barrier layer

[0044] 255: Dielectric barrier

[0045] 260: Gate structure

[0046] 261: Bottom surface

[0047] 262: Interface layer

[0048] 264: High-k gate dielectric layer

[0049] 266: Work function metal layer

[0050] 268: Filler Metal

[0051] 269: Top surface

[0052] 270: Gate structure

[0053] 271: Bottom surface

[0054] 272: Interface layer

[0055] 274: High-k gate dielectric layer

[0056] 276: Work function metal layer

[0057] 278: Filler Metal

[0058] 280: Interlayer dielectric (ILD) layer

[0059] 291: Source / Drain Contact

[0060] 293: Source / Drain Contact

[0061] 295: Source / Drain Contact

[0062] 297: Grid hole

[0063] 299: Grid hole

[0064] S / D: Source / Drain region

[0065] GT1: Gate Trench

[0066] O1, O2, O3, O4: Open

[0067] R1, R3, R4: Concave

[0068] Tn: Bottom transistor

[0069] Tp: Top transistor

[0070] Tn1, Tn2, Tn3, Tn4, Tp1, Tp2, Tp3, Tn4: Transistor

[0071] H1, H2: Height

[0072] T1, T2, T3, T4: vertical thickness

[0073] S D ,SD1,S en ,S enb ,SQ : Input signal

[0074] Gp1, Gn1, Gp2, Gn2, Gp3, Gn3, Gp4, Gn4: Gate

[0075] G1, G4: common gate DETAILED DESCRIPTION

[0076] The following disclosure provides many different embodiments or examples for implementing different features of the present application. The following describes specific embodiments of components and arrangements to simplify the present application. These are of course only embodiments and are not intended to be limiting. For example, in the subsequent description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which another feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present application may repeat numbers and / or text in different instances. The purpose of repetition is to simplify and clarify the description, rather than to define the relationship between the different embodiments and / or configurations discussed.

[0077] In addition, spatially relative terms such as "below," "below," "below," "above," "over" and other similar terms are used herein for convenience in describing the relationship of one element or feature to another element or feature in the figures. Spatially relative terms encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented in other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein should be interpreted accordingly.

[0078] As used herein, "approximately," "about," "essentially," or "substantially" shall generally mean within 20%, or within 10%, or within 5% of a given value or range. The values ​​given herein are approximate, meaning that if not explicitly stated, the terms "approximately," "about," "essentially," or "substantially" can be inferred. It will be understood by those of ordinary skill in the art that dimensions may vary depending on different technology nodes. It will be recognized by those of ordinary skill in the art that dimensions depend on the specific device type, technology generation, minimum feature size, etc. Therefore, it is intended that the term be interpreted based on the technology being evaluated.

[0079] As used herein, the term "etch selectivity" refers to the ratio of the etching rates of two different materials under the same etching conditions. As used herein, the term "high k" refers to a high dielectric constant. In the field of semiconductor device structures and production processes, high k refers to a dielectric constant greater than the dielectric constant of SiO2 (e.g., greater than 3.9). As used herein, the term "low k" refers to a low dielectric constant. In the field of semiconductor device structures and production processes, low k refers to a dielectric constant less than the dielectric constant of SiO2 (e.g., less than 3.9). As used herein, the term "p-type" defines a structure, layer and / or region as being doped with a p-type dopant, such as boron. As used herein, the term "n-type" defines a structure, layer and / or region as being doped with an n-type dopant, such as phosphorus. As used herein, the term "conductive" refers to a conductive structure, layer and / or region. As used herein, a source / drain region may refer to a source or a drain individually or collectively, depending on the context.

[0080] Nanostructure transistors (e.g., gate allaround (GAA) transistor structures) can be patterned by any suitable method. For example, the structure is patterned using one or more photolithography processes (including double patterning or multiple patterning processes). In general, the double patterning or multiple patterning process combines photolithography and self-alignment processes to allow the formation of patterns having a pitch that is, for example, smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, after which the remaining spacers can be used to pattern the GAA structure.

[0081] The present application relates to integrated circuit structures and methods of forming the same. More specifically, some embodiments of the present application relate to complementary FET (CFET) devices that include separate fork-sheet gate structures surrounded by identical gate spacers.

[0082] Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B and Fig. 21C A perspective view and a cross-sectional view of an intermediate stage of an integrated circuit structure (or semiconductor device) 100a according to some embodiments of the present application are depicted. In some embodiments, FIG. 21A to FIG. 21C The semiconductor device in the embodiment is a CFET device. In addition to the integrated circuit structure, Figures 1 to 7A The X-axis, Y-axis, and Z-axis directions are also depicted. According to some exemplary embodiments, the formed device includes a p-type transistor (such as a p-type GAA FET) and an n-type transistor (such as an n-type GAA FET). In the various views and illustrative embodiments, the same reference numbers are used to indicate the same elements. It should be understood that additional embodiments of the method can be provided in Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B and Fig. 21C Additional operations are provided before, during, and after the processes shown, and some of the operations described below may be replaced or eliminated. The order of operations / processes may be interchangeable.

[0083] Figures 1 to 7A is a perspective view of some embodiments of a semiconductor device 100 a at an intermediate stage during fabrication. Figure 7B , Fig. 8A , Fig. 9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A , Fig.17A , Fig.18A , Fig.19A , Fig. 20A as well as Fig.21A The semiconductor device 100a is formed along a first tangent line (eg, Fig. 7A Schematic cross-sectional view of some embodiments of the cut line II). Figure 7C , Figure 8B , Fig. 9B , Fig. 10B , Fig. 11B , Fig. 12B , Fig. 13B , Fig. 14B , Fig. 15B , Fig. 16B , Fig. 17B , Fig.18B , Fig.19B , Fig. 20B as well as Fig. 21B The semiconductor device 100a is formed along a second tangent line (eg, Fig. 7A Schematic cross-sectional view of some embodiments of the cut line II-II). Fig. 21C The semiconductor device 100a is formed along a third tangent line (eg, Fig. 7A Schematic cross-sectional view of some embodiments of the cut line III-III).

[0084] refer to Figure 1, the epitaxial stack 120 is formed over the substrate 110. In some embodiments, the substrate 110 may include silicon (Si). Alternatively, the substrate 110 may include germanium (Ge), silicon germanium (SiGe), a III-V group material (e.g., GaAs, GaP, GaAsP, AlInAs, AlGaAs, GaInAs, InAs, GaInP, InP, InSb and / or GaInAsP; or a combination thereof), or other suitable semiconductor materials. In some embodiments, the substrate 110 may include a semiconductor-on-insulator (SOI) structure such as a buried dielectric layer. Alternatively, the substrate 110 may include a buried dielectric layer such as a buried oxide (BOX) layer, wherein the buried oxide layer is formed, for example, by separation by implantation of oxygen (SIMOX) technology, wafer bonding, selective epitaxial growth (SEG), or other suitable methods.

[0085] Epitaxial stack 120 includes a plurality of epitaxial layers 122, 124, 126, and 128. A plurality of epitaxial layers 122 having a first composition are disposed between a plurality of epitaxial layers 124 having a second composition, and a plurality of epitaxial layers 126 having a third composition are disposed between a plurality of epitaxial layers 128 having a fourth composition. The first, second, third, and fourth compositions are different. In some embodiments, epitaxial layers 122, 126, and 128 are germanium-rich layers, and epitaxial layer 124 is a silicon-rich layer. However, other embodiments are possible, including those providing first and second compositions with different etch selectivities.

[0086] For example, epitaxial growth of multiple layers of epitaxial stack 120 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes. In some embodiments, epitaxial layers 122, 124, 126, and 128 include a material different from substrate 110. As described above, in at least some embodiments, epitaxial layers 122, 124, and 126 include epitaxially grown silicon germanium (SiGe) layers having different compositions, and epitaxial layer 128 includes an epitaxially grown GeSn layer. Alternatively, in some embodiments, any of epitaxial layers 122, 124, 126, and 128 may include other materials such as germanium, tin; compound semiconductors such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; or materials such as Si1- x Ge x ,Ge 1-y Sn y 、Si 1-x-y Ge x Sn y , Ga 1-x-y As x P y 、Al 1-x-y In x As y 、Al 1-x-y Ga x As y 、In 1-x-y Ga x As y , Ga 1-x- y In x P y and / or Ga 1-x-y-z In x As y P z or a combination thereof. As discussed, the materials of the epitaxial layers 122, 124, 126, and 128 may be selected based on providing different etch selectivity characteristics.

[0087] For example, the epitaxial layer 122 is Si x1 Ge y1 , epitaxial layer 124 is Si x2 Ge y2 , epitaxial layer 126 is Si x3 Ge y3 The epitaxial layer 128 is Ge y4 Sn z1 The silicon atom concentration of the epitaxial layer 124 is higher than the silicon atom concentration of the epitaxial layers 122 and 126. On the contrary, the silicon atom concentration of the epitaxial layer 128 is lower than the silicon atom concentration of the epitaxial layers 122 and 126. For example, x2 is greater than x1 and x3. In addition, the silicon atom concentration of the epitaxial layer 128 is 0 or less than 1%. The germanium atom concentrations of the epitaxial layers 122, 124, 126 and 128 are different. For example, y4>y1>y3>y2, but not limited thereto.

[0088] In some embodiments, x1 is in the range of about 0.15 to about 0.25, y1 is in the range of about 0.75 to about 0.85, x2 is in the range of about 0.55 to about 0.65, y2 is in the range of about 0.35 to about 0.45, x3 is in the range of about 0.35 to about 0.45, y3 is in the range of about 0.55 to about 0.65, y4 is in the range of about 0.85 to about 0.95, and z1 is in the range of about 0.05 to about 0.15.

[0089] Epitaxial layers 124 and 128 or portions thereof may form a nanostructure channel of a nanostructure transistor. As used herein, the term "nanostructure" is used to denote any material portion having nanometer-scale or even micrometer-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term denotes elongated material portions of circular and substantially circular cross-sections, as well as beam or bar-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. For example, depending on its geometry, a nanostructure is a nanosheet, a nanowire, a nanoslab, or a nanoring. The use of epitaxial layers 124 and 128 to define one or more channels of a device is discussed further below.

[0090] exist Figure 1 In the embodiment, epitaxial layers 126 and 128 are disposed above epitaxial layers 122 and 124. It should be noted that the two epitaxial layers 124 and the two epitaxial layers 128 are Figure 1 The configuration shown is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers may be formed in the epitaxial stack 120; the number of layers depends on the number of channel regions required for the transistor. In some embodiments, the number of layers of each of the epitaxial layers 124 and 128 is between 1 and 100, such as between 2 and 10.

[0091] In some embodiments, each of the epitaxial layers 122, 124, 126, and 128 has a thickness in a range of about 0.1 nm to about 100 nm. In addition, the plurality of epitaxial layers 122 may have different thicknesses, the plurality of epitaxial layers 124 may have different thicknesses, the plurality of epitaxial layers 126 may have different thicknesses, and / or the plurality of epitaxial layers 128 may have different thicknesses.

[0092] As described in more detail below, epitaxial layers 124 and 128 can be used as channel regions of a subsequently formed semiconductor device, and the thickness is selected based on device performance considerations. Epitaxial layers 122 and 126 in the channel region can eventually be removed, which are used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness is selected based on device performance considerations. Therefore, epitaxial layers 122 and 126 can also be referred to as sacrificial layers, and epitaxial layers 124 and 128 can also be referred to as channel layers.

[0093] refer to Figure 2 , forming at least one fin structure 121 extending from the substrate 110. In various embodiments, the fin structure 121 is formed above the protrusion 112, wherein the protrusion 112 is formed from the substrate 110 and includes a portion of each epitaxial layer 122, 124, 126 and 128 of the epitaxial stack 120. The fin structure 121 can be manufactured using a suitable process including a double patterning or multiple patterning process. In general, the double patterning or multiple patterning process combines photolithography and self-alignment processes to allow the formation of patterns, which have a pitch that is, for example, less than that obtainable using a single direct photolithography process. For example, in some embodiments, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 121 by etching the epitaxial stack 120. The etching process may include dry etching, wet etching, reactive ion etching (RIE) and / or other suitable processes.

[0094] exist Figure 1 and Figure 2In the illustrated embodiment, a hard mask (HM) layer 130 is formed over the epitaxial stack 120 before patterning the fin structure 121. In some embodiments, the HM layer 130 includes an oxide layer 132 (e.g., a pad oxide layer that may include SiO2) and a nitride layer 134 (e.g., a pad nitride layer that may include Si3N4) formed over the oxide layer 132. The oxide layer 132 may serve as an adhesion layer between the epitaxial stack 120 and the nitride layer 134, and may serve as an etch stop layer for etching the nitride layer 134. In some embodiments, the oxide layer 132 includes a thermally grown oxide, an oxide deposited by chemical vapor deposition (CVD), and / or an oxide deposited by atomic layer deposition (ALD). In some embodiments, the nitride layer 134 is deposited on the oxide layer 132 by CVD and / or other suitable techniques.

[0095] The fin structure 121 may then be fabricated using a suitable process including photolithography and etching processes. The photolithography process may include forming a photoresist layer (not shown) over the HM layer 130, exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a patterned mask including a resist. In some embodiments, patterning the resist to form a patterned mask element may be performed using an electron beam (e-beam) lithography process or an extreme ultraviolet (EUV) lithography process using light in the EUV region (having a wavelength of, for example, about 1-200 nm). The patterned mask may then be used to protect areas of the substrate 110 (and layers formed on the substrate 110) while an etching process forms trenches 102 through the HM layer 130, through the epitaxial stack 120, and into the substrate 110 in the unprotected areas, leaving the fin structure 121. The trenches 102 may be etched using dry etching (e.g., reactive ion etching), wet etching, and / or combinations thereof. Many other implementations of the method of forming fins on a substrate may also be used, including, for example, defining fin regions (eg, by masking or isolation regions) and epitaxially growing the epitaxial stack 120 in the form of the fin structure 121 .

[0096] Then, if Figure 3As shown in FIG. 1 , an isolation structure 140 is formed to surround the fin structure 121. The isolation structure 140 may include a pad oxide (not shown). The pad oxide may be formed by a thermal oxide formed by thermal oxidation of a surface layer of the substrate 110. The pad oxide may also be a silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The isolation structure 140 may also include a dielectric material above the pad oxide, and this dielectric material may be formed using flowable chemical vapor deposition (FCVD) or spin coating, etc.

[0097] Then, the isolation structure 140 is planarized until the top surface of the fin structure 121 is exposed. That is, the hard mask layer 130 (refer to Figure 2 ). Subsequently, the isolation structure 140 is recessed so that the top of the fin structure 121 protrudes above the top surface of the isolation structure 140. The etching may be performed using a dry etching process, wherein NH3 and NF3 are used as etching gases. According to an alternative embodiment of the present application, the recessing of the isolation structure 140 is performed using a wet etching process. The etching chemicals may include, for example, diluted HF.

[0098] refer to Figure 4 The dummy gate dielectric layer 145 is conformally formed on Figure 3 Subsequently, at least one dummy gate structure 150 is formed on the dummy gate dielectric layer 145 and partially disposed on the fin structure 121. The portion of the fin structure 121 underlying the dummy gate structure 150 may be referred to as a channel region. The dummy gate structure 150 may also define a source / drain region S / D (indicated by Figure 7B ), for example, an area of ​​the fin structure 121 adjacent to the channel region and on opposite sides of the channel region.

[0099] In some embodiments, the dummy gate dielectric layer 145 is made of silicon dioxide, silicon nitride, a high-k dielectric material, or other suitable material. The formation operation of the dummy gate is to form a dummy gate electrode layer, and a hard mask of multiple layers (e.g., an oxide layer and a nitride layer) may be included above the dummy gate electrode layer. Then, the hard mask is patterned, and then the dummy gate electrode layer is patterned by using the patterned hard mask as an etching mask. The etching process may include wet etching, dry etching, and / or a combination of the above. In this way, a dummy gate structure 150 including a dummy gate electrode layer 154 and a hard mask (e.g., an oxide layer 156 and a nitride layer 158) is formed.

[0100] refer to Figure 5 After the formation of the dummy gate structure 150 is completed, the gate spacer 170 (refer to Figure 6 ) is formed on the sidewall of the dummy gate structure 150. In detail, Figure 5 As shown, dielectric film 170' is deposited on Figure 4 The dielectric film 170' may be silicon nitride (SiN), silicon oxycarbide (SiCO), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), etc. The dielectric film 170' is conformally formed on the substrate 110, the dummy gate structure 150, the dummy gate dielectric layer 145, and the fin structure 121. In some embodiments, the dielectric film 170' may be a single layer or multiple layers.

[0101] refer to Figure 6 Then, the deposited dielectric film 170' (refer to Figure 5 ) and the dummy gate dielectric layer 145 are subjected to an anisotropic etching process to expose a portion of the fin structure 121 (see Figure 3 ). The dielectric material portion directly above the pseudo dummy gate structure 150 may be completely removed by this anisotropic etching process. A portion of the dielectric material on the sidewall of the dummy gate structure 150 may be retained to form a gate sidewall spacer, which is represented as a gate spacer 170 for simplicity.

[0102] The anisotropic etching process further etches the exposed portion of the fin structure 121, and the anisotropic etching process extends laterally beyond the gate spacer 170 (for example, in the source / drain region of the fin structure 121), resulting in a recess R1 into the fin structure 121 and on opposite sides of the dummy gate structure 150. After the anisotropic etching, the end surfaces of the epitaxial layers 122, 124, 126, and 128 are substantially aligned with the corresponding outermost sidewalls of the gate spacer 170 due to the anisotropic etching.

[0103] In some embodiments, anisotropic etching can be performed by dry chemical etching with a plasma source and a reactive gas. The plasma source can be an inductively coupled plasma (ICP) source, a transformer coupled plasma (TCP) source, an electron cyclotron resonance (ECR) source, etc., and the reactive gas can be (for example) a fluorine-based gas (such as SF6, CH2F2, CH3F, CHF3, etc.), a chlorine-based gas (for example, Cl2), hydrogen bromide gas (HBr), oxygen (O2), etc., or a combination thereof.

[0104] refer to 7A to 7C . Epitaxial layers 122 and 126 are laterally or horizontally recessed using a suitable etching technique, thereby creating a lateral recess vertically between the corresponding epitaxial layers 124 and 128. This operation is performed using a selective wet etching process. By way of example and not limitation, epitaxial layers 122, 124, 126, and 128 are made of different materials that allow for selective etching of epitaxial layers 122 and 126. In some embodiments, the selective wet etching includes an APM etch (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture), which etches SiGe (e.g., epitaxial layers 122 and 124) at a faster etching rate than etching Si (e.g., epitaxial layer 126). The selective wet etching may also include a fluorine etchant (e.g., NF3 or other suitable etchant) to etch Ge (e.g., epitaxial layers 122 and 124) at a faster etching rate than etching GeSn (e.g., epitaxial layer 128). In detail, the fluorine-containing etchant reacts with Sn to form SnF x , which protects GeSn from being further etched. Therefore, the epitaxial layers 124 and 128 extend laterally beyond the opposite end surfaces of the epitaxial layers 122 and 124 .

[0105] An inner spacer 180 is then formed in the recess. For example, an inner spacer material layer is formed to fill the recess left by the lateral etching of the epitaxial layers 122 and 126. The inner spacer material layer can be a low-k dielectric material (such as SiO2, silicon nitride (SiN), silicon oxycarbide (SiCO), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN)). The inner spacer material layer can be formed using CVD (including low-pressure CVD (LPCVD) and plasma enhanced CVD (PECVD)), PVD, ALD or other suitable processes. After depositing the inner spacer material layer, an anisotropic etching process is performed to trim the deposited inner spacer material layer so that a portion of the deposited inner spacer material layer that fills the recess left by the lateral etching of the epitaxial layers 122 and 126 is left. After the trimming process, for simplicity, the remaining portion of the deposited inner spacer material is represented as the inner spacer 180. The inner spacer 180 is used to isolate the metal gate and source / drain epitaxial structures formed in subsequent processing. Figure 7B In the embodiment of FIG. 1 , the sidewalls of the inner spacer 180 are substantially aligned with the sidewalls of the epitaxial layers (channel layers) 124 and 128 .

[0106] refer to Fig. 8A and Figure 8B . The source / drain epitaxial structure 210 is formed at the source / drain region S / D of the fin structure 121. The source / drain epitaxial structure 210 is connected to the epitaxial layer 124. The source / drain epitaxial structure 210 is formed by performing an epitaxial growth process, wherein the epitaxial growth process provides an epitaxial material connected to the fin structure 121. During the epitaxial growth process, the dummy gate structure 150 and the gate spacer 170 confine the source / drain epitaxial structure 210 in the source / drain region S / D. In some embodiments, the lattice constant of the source / drain epitaxial structure 210 is different from the lattice constant of the epitaxial layer 124, so that the epitaxial layer 124 can generate strain or stress through the source / drain epitaxial structure 210, thereby improving the carrier mobility of the semiconductor device and improving the device performance. The epitaxy process includes CVD deposition techniques (e.g., PECVD, vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy and / or other suitable processes. The epitaxy process may use gaseous and / or liquid precursors that interact with the components of the epitaxial layer 124.

[0107] In some embodiments, the source / drain epitaxial structure 210 is a silicon-rich material and may include Si, SiP, or other suitable materials. The source / drain epitaxial structure 210 may be doped in-situ by introducing dopants during the epitaxy process, the dopants including: n-type dopants (such as phosphorus or arsenic); and / or other suitable dopants including combinations of the above. If the source / drain epitaxial structure 210 is not doped in-situ, an implantation process (i.e., a junction implant process) is performed to dope the source / drain epitaxial structure 210. In an exemplary embodiment, the source / drain epitaxial structure 210 in the n-type includes Si:P.

[0108] As described above, the source / drain epitaxial structure 210 is a silicon-rich material, so that the source / drain epitaxial structure 210 is easy to grow on the silicon-rich material (for example, the epitaxial layer 124 in this embodiment). Therefore, the growth rate of the source / drain epitaxial structure 210 on the epitaxial layer 124 is greater than the growth rate on the epitaxial layer 128. Even if some epitaxial material grows on the epitaxial layer 128 during the growth of the source / drain epitaxial structure 210, the quality of the epitaxial material is not as good as that of the source / drain epitaxial structure 210, and the epitaxial material may be peeled off from the epitaxial layer 128.

[0109] Then, an isolation layer 220 is formed to cover one of the plurality of source / drain epitaxial structures 210. Specifically, a dielectric layer is formed over the source / drain epitaxial structure 210, and one or more etching processes are performed to pattern the dielectric layer and form the isolation layer 220. Therefore, the isolation layer 220 covers one of the plurality of source / drain epitaxial structures 210 and is spaced apart from another source / drain epitaxial structure 210. In some embodiments, the isolation layer 220 is composed of silicon oxide, silicon nitride, SiOCN, etc., or a combination thereof.

[0110] refer to Fig. 9A and Fig. 9B. The source / drain epitaxial structure 215 is formed at the source / drain region S / D of the fin structure 121. The source / drain epitaxial structure 215 is connected to the epitaxial layer 128. The source / drain epitaxial structure 215 can be formed by performing an epitaxial growth process, wherein the epitaxial growth process provides an epitaxial material connected to the fin structure 121. During the epitaxial growth process, the dummy gate structure 150 and the gate spacer 170 limit the source / drain epitaxial structure 215 to the source / drain region S / D. In some embodiments, the lattice constant of the source / drain epitaxial structure 215 is different from the lattice constant of the epitaxial layer 128, so that the epitaxial layer 128 can generate strain or stress through the source / drain epitaxial structure 215 to improve the carrier mobility of the semiconductor device and enhance the performance of the device. The epitaxial process includes CVD deposition technology (e.g., PECVD, vapor phase epitaxy and / or ultra-vacuum CVD), molecular beam epitaxy and / or other suitable processes. The epitaxial process may use gaseous and / or liquid precursors that interact with the composition of the epitaxial layer 128 .

[0111] In some embodiments, the source / drain epitaxial structure 215 is a germanium-rich material and may include Ge, GaAs, AlGaAs, SiGe, or other suitable materials. The source / drain epitaxial structure 215 may be in-situ doped during the epitaxial process by introducing a dopant material, the dopant material including: a p-type dopant (such as boron or BF2); and / or other suitable dopants in combination with the above. If the source / drain epitaxial structure 215 is not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structure 215. In an exemplary embodiment, the source / drain epitaxial structure 215 in the n-type includes SiGe:B.

[0112] As described above, the source / drain epitaxial structure 215 is a germanium-rich material, so that the source / drain epitaxial structure 215 is easy to grow on the germanium-rich material (for example, the epitaxial layer 128 in this embodiment). Therefore, the growth rate of the source / drain epitaxial structure 215 on the epitaxial layer 128 is greater than the growth rate of the source / drain epitaxial structure 210.

[0113] refer to Fig. 10A and Fig. 10B. A contact etch stop layer (CESL) 230 is conformally formed over the substrate 110. In some embodiments, the CESL 230 may be one or more stress layers. In some embodiments, the CESL 230 has a tensile stress and is formed of SiN, SiCN, or a combination thereof. In some other embodiments, the CESL 230 includes a material such as oxynitride. In yet other embodiments, the CESL 230 may have a composite structure including multiple layers, such as a silicon nitride layer covering a silicon oxide layer. The CESL 230 may be formed using PECVD, however, other suitable methods such as LPCVD or ALD may also be used.

[0114] Then, an interlayer dielectric (ILD) layer 235 is formed on the CESL 230. The ILD layer 235 may be formed by CVD, high-density plasma CVD, spin coating, sputtering, or other suitable methods. In some embodiments, the ILD layer 235 includes silicon oxide. In some other embodiments, the ILD layer 235 may include silicon oxynitride, silicon nitride, SiOCN, a compound including Si, O, C, and / or H (e.g., silicon oxide, SiCOH, and SiOC), a low-k material, or an organic material (e.g., a polymer). After forming the ILD layer 235, a planarization operation (such as CMP) is performed to remove the oxide layer (patterned hard mask) 156 and the nitride layer 158 (see FIG. 1 ). Fig. 9A and Fig. 9B ), and expose the dummy gate electrode layer 154.

[0115] refer to Fig.11A and Fig. 11B . Remove the dummy gate electrode layer 154 and the dummy gate dielectric layer 145 (refer to Fig. 10A and Fig. 10B ), thereby exposing the epitaxial layers 122, 124, 126, and 128. During the removal of the dummy gate electrode layer 164 and the dummy gate dielectric layer 145, the ILD layer 235 protects the source / drain epitaxial structures 210 and 215. In some embodiments, the dummy gate electrode layer 154 and the dummy gate dielectric layer 145 are removed by using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), which etches the materials in the dummy gate electrode layer 154 and the dummy gate dielectric layer 145 at a faster etching rate than etching other materials (e.g., gate spacers 170 and / or ILD layer 235), thereby forming gate trenches GT1 between the corresponding gate spacers 170, and the epitaxial layers 122, 124, 126, and 128 are exposed in the gate trenches GT1.

[0116] refer to Fig. 12A and Fig. 12B Subsequently, the protection material 240 is filled in the gate trench GT1, and a planarization process (e.g., a CMP process) is performed to level the top surface of the protection material 240 with the top surface of the ILD layer 235. In some embodiments, the protection material 240 is composed of silicon nitride (SiN), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), or silicon oxycarbonitride (SiOCN). The protection material 240 includes a material different from the ILD 235 and the gate spacer 170 to prevent the top surface of the protection material 240 from being formed in a subsequent etching process (e.g., Fig. 12B , FIG. 15A to FIG. 15B , FIG. 17A to FIG. 17B as well as FIG. 19A to FIG. 19B Etching selectivity is produced in the etching process shown).

[0117] Subsequently, an opening O1 is formed in the protective material 240 to expose the first side surface of the epitaxial layers 122, 124, 126, and 128. The protective material 240 still covers the second side surface (which is opposite to the first side surface) of the epitaxial layers 122, 124, 126, and 128. In addition, the opening O1 exposes a portion of the inner sidewall of the gate spacer 170. The opening O1 is formed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof) that etches the material in the protective material 240 at a faster etching rate than etching other materials (e.g., the gate spacer 170, the CESL 230, the ILD layer 235, and / or the epitaxial layers 122, 124, 126, and 128).

[0118] refer to Fig.13A and Fig. 13B . The epitaxial layer 128 is recessed laterally or horizontally using a suitable etching technique, resulting in a plurality of lateral recesses R3 each vertically located between corresponding epitaxial layers 126. This operation may be performed using a selective etching process. By way of example and not limitation, the ILD layer 235 and the gate spacer 170 are dielectric materials, and the epitaxial layers 122, 124, and 126 are semiconductor materials, wherein the semiconductor materials have a different composition and / or concentration than the epitaxial layer 128, thereby allowing the epitaxial layer 128 to be selectively etched. The selective etching may include a peroxide-water etchant to etch Ge (e.g., epitaxial layer 128) at a faster etching rate than etching Si (e.g., epitaxial layers 122, 124, and 126). Therefore, the epitaxial layers 122, 124, and 126 extend laterally beyond the first side surface of the epitaxial layer 128.

[0119] refer to Fig.14A and Fig. 14B The plurality of dielectric barrier layers 250 are respectively filled in the plurality of recesses R3 (refer to Fig. 13B For example, a dielectric material layer is formed to fill the above Fig.13A and Fig. 13B The recess of the epitaxial layer 128 is discussed in the lateral etching. The dielectric material layer can be a low-k dielectric material (such as SiO2, SiN, SiC, SiON, SiCN, SiOCN, SiBCN, etc. or a combination of the above. The dielectric material layer can be formed by a suitable deposition method (such as ALD). The dielectric material layer can be formed using CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes.

[0120] After the dielectric material layer is deposited, an anisotropic etching process may be performed to trim the deposited dielectric material layer to leave a portion of the deposited dielectric material layer, wherein the portion left is filled in the recess left by the lateral etching of the epitaxial layer 128. After the trimming process, for simplicity, the remaining portion of the deposited dielectric material is represented as a dielectric barrier layer 250 in the recess R3. The dielectric barrier layer 250 is used to remove the epitaxial layer 122 (refer to FIG. 2 ). Fig.15A and Fig. 15B ) and forming a gate structure (reference Fig.16A and Fig. 16B ) during which the epitaxial layer 128 is sealed.

[0121] refer to Fig.15A and Fig. 15B Subsequently, the epitaxial layer 122 exposed from the opening O1 is removed by using another selective etching process (refer to Fig.14A and Fig. 14B ), this selective etching process etches the epitaxial layer 122 at a faster etching rate than etching the epitaxial layers 124 and 126, thereby forming an opening O2 between adjacent epitaxial layers (i.e., channel layers) 124 / 126. The selective etching may include a peroxide-water mixed etchant that etches Ge (e.g., epitaxial layer 122) at a faster etching rate than etching Si (e.g., epitaxial layers 124 and 126). In this way, the epitaxial layer 124 becomes a fork suspended above the substrate 110 and between the source / drain epitaxial structures 210. This operation is also referred to as a channel release process. In some embodiments, the epitaxial layer 124 may be interchangeably referred to as a nanostructure (depending on its geometry, such as a fork, nanowire, nanoplate, and nanoring or nanosheet, etc.). For example, in some other embodiments, since the selective etching process completely removes the epitaxial layer 122, the epitaxial layer 124 may be trimmed to have a substantially circular shape (i.e., a cylindrical shape) (refer to Fig. 22 ). In this case, the resulting epitaxial layer 124 may be referred to as a nanowire.

[0122] refer to Fig.16A and Fig. 16B The gate structure 260 is formed in the openings O1 and O2 (refer to Fig.15A and Fig. 15B ). The formation of the gate structure 260 may include deposition to form various gate materials and one or more liner layers, and one or more CMP processes to remove excess gate material. In detail, the gate dielectric layer of the gate structure 260 is formed in the openings O1 and O2 and around the epitaxial layer 124. The gate dielectric layer includes an interface layer (e.g., a silicon oxide layer) 262 and a high-k gate dielectric layer 264 above the interface layer 262. The high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than thermal silicon oxide (~3.9)). In some embodiments, the interface layer 262 of the gate dielectric layer may include a dielectric material such as silicon oxide (SiO2), HfSiO, silicon oxynitride (SiON), SiBCN, SiOC, SiCN, or a combination of the foregoing. The interface layer 262 may be formed by ALD, CVD and / or other suitable methods. The high-k gate dielectric layer 264 of the gate dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer 264 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3; STO), barium titanate (BaTiO3; BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), nitride oxide (SiON), PZT (lead zirconate titanate), VDF-TrFE (vinylidene fluoride-trifluoroethylene; ferroelectric polymer), or a combination of the foregoing.

[0123] The work function metal layer 266 of the gate structure 260 is formed around the high-k gate dielectric layer 264. The work function metal layer 266 may include a work function metal to provide a suitable work function for the gate structure 260. For an n-type FET, the work function metal layer 266 may include one or more n-type work function metals (N-metal). The n-type work function metal may illustratively include, but is not limited to, titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC)), aluminides, and / or other suitable materials.

[0124] The filling metal 268 of the gate structure 260 is formed on the work function metal layer 266 and fills the opening O1 (and the opening O2). In some embodiments, the filling metal 268 may illustratively include but is not limited to tungsten, platinum, aluminum, copper, nickel, cobalt, silver, gold, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, ruthenium oxide, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0125] refer to Fig.17A and Fig. 17B The protective material 240 is then removed (see Fig.16A and Fig. 16B ) to form another opening O3, wherein the opening O3 exposes the second side surface of the epitaxial layers 122, 124, 126 and 128, and the gate structure 260 and the dielectric barrier layer 250 cover the first side surface of the epitaxial layers 122, 124, 126 and 128. In addition, the opening O3 exposes another portion of the inner sidewall of the gate spacer 170. The opening O3 is formed using a selective etching process (e.g., selective dry etching, selective wet etching, or a combination thereof), wherein the selective etching process etches the protection material 240 at a faster etching rate than etching other materials (e.g., the gate spacer 170, the CESL 230, the ILD layer 235 and / or the epitaxial layers 124, 126 and 128) (see FIG. 2 ). Fig.16A and Fig. 16B ) in the materials.

[0126] refer to Fig.18A and Fig.18B . The epitaxial layer 124 is laterally or horizontally recessed using a suitable etching technique, thereby vertically creating a lateral recess between the corresponding epitaxial layers 122. This operation can be performed using a selective etching process. By way of example and not limitation, the ILD layer 235, the gate spacer 170, and the interface layer 262 of the gate structure 260 are dielectric materials, and the epitaxial layers 126 and 128 are semiconductor materials, wherein the epitaxial layers 126 and 128 have a different composition and / or concentration than the epitaxial layer 124, thereby allowing selective etching of the epitaxial layer 124. The selective etching can include an NH4OH etchant to etch Si (e.g., epitaxial layer 124) at a faster etching rate than etching Ge (e.g., epitaxial layers 126 and 128). Therefore, the gate structure 260 extends laterally beyond the second side surface of the epitaxial layer 124.

[0127] Then, the dielectric barrier layer 255 is respectively filled in the recesses. For example, a dielectric material layer is formed to fill the recesses left by the lateral etching of the epitaxial layer 124 discussed above. The dielectric material layer can be a low-k dielectric material (such as SiO2, SiN, SiC, SiON, SiCN, SiOCN, SiBCN, etc. or a combination thereof) and can be formed by a suitable deposition method (such as ALD). The dielectric material layer can be formed using CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes.

[0128] After the dielectric material layer is deposited, an anisotropic etching process may be performed to trim the deposited dielectric material layer so that some portions of the deposited dielectric material layer are left, which fill the recess left by the lateral etching of the epitaxial layer 124. After the trimming process, for simplicity, the remaining portion of the deposited dielectric material is represented as a dielectric barrier layer 255 in the recess R4. The dielectric barrier layer 255 is used to form a gate structure (refer to Fig. 20A and Fig. 20B ) during which the epitaxial layer 124 is sealed.

[0129] refer to Fig.19A and Fig.19B . Subsequently, the epitaxial layer 126 exposed by the opening O3 is removed by using a selective etching process, wherein the selective etching process etches the epitaxial layer 126 at a faster etching rate than etching the epitaxial layer 128, forming an opening O4 between adjacent epitaxial layers (i.e., channel layers) 128. The selective etching may include a fluorine-containing etchant (e.g., NF3 or other suitable etchant) to etch Ge (e.g., epitaxial layer 126) at a faster etching rate than etching Sn (e.g., epitaxial layer 128). In this way, the epitaxial layer 128 becomes a fork suspended above the substrate 110 and between the source / drain epitaxial structures 215. This operation is also referred to as a channel release process. In some embodiments, the epitaxial layer 128 may be interchangeably referred to as a nanostructure (depending on its geometry, such as a fork, nanowire, nanoplate, nanoring or nanosheet, etc.). For example, in some other embodiments, since the epitaxial layer 126 is completely removed by the selective etching process, the epitaxial layer 128 can be trimmed to have a substantially circular shape (ie, a cylindrical shape) (see FIG. Fig. 22 ). In this case, the resulting epitaxial layer 128 may be referred to as a nanowire.

[0130] refer to Fig. 20A and Fig. 20BAnother gate structure 270 is formed in the openings O3 and O4. The formation of the gate structure 270 may include deposition to form various gate materials and one or more liner layers, and one or more CMP processes to remove excess gate materials. In detail, the gate dielectric layer of the gate structure 270 is formed in the openings O3 and O4 (refer to Fig.19A and Fig.19B ) and around the epitaxial layer 128. The gate dielectric layer includes an interfacial layer (e.g., a silicon oxide layer) 272 and a high-k gate dielectric layer 274 above the interfacial layer 272. The high-k gate dielectric includes a dielectric material having a high dielectric constant (e.g., greater than thermal silicon oxide (~3.9)). In some embodiments, the interfacial layer 272 of the gate dielectric layer may include a dielectric material of silicon oxide (SiO2), HfSiO, silicon oxynitride (SiON), SiBCN, SiOC, SiCN, or a combination thereof. The interfacial layer 272 may be formed by ALD, CVD, and / or other suitable methods. The high-k gate dielectric layer 274 of the gate dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-k gate dielectric layer 274 may include other high-k dielectrics, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), lanthanum oxide (LaO), zirconium oxide (ZrO), titanium oxide (TiO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), strontium titanate (SrTiO3, STO), barium titanate (BaTiO3, BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), aluminum oxide (Al2O3), silicon nitride (Si3N4), nitride oxide (SiON), PZT, VDF-TrFE (ferroelectric polymer), or a combination of the foregoing.

[0131] The work function metal layer 276 of the gate structure 270 is formed around the high-k gate dielectric layer 274. The work function metal layer 276 may include a work function metal to provide a suitable work function for the gate structure 270. For a p-type FinFET, the work function metal layer 276 may include one or more p-type work function metals (P-metal). The p-type work function metal may illustratively include, but is not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides and / or other suitable materials.

[0132] The filling metal 278 of the gate structure 270 is formed above the work function metal layer 276 and fills the opening O3 (and O4). In some embodiments, the filling metal 278 may illustratively include, but is not limited to, tungsten, platinum, aluminum, copper, nickel, cobalt, silver, gold, ruthenium, titanium, tantalum, titanium nitride, tantalum nitride, tungsten nitride, ruthenium oxide, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN or other suitable materials.

[0133] refer to Fig.21A , Fig. 21B as well as Fig. 21C Another inter-layer dielectric (ILD) layer 280 is formed on Fig. 20A and Fig. 20B In some embodiments, the ILD layer 280 includes an oxide such as tetraethylorthosilicate (TEOS), undoped silicate glass, or a doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), etc. In some embodiments, the ILD layer 280 is made of silicon oxide (SiO x The ILD layer 280 may be deposited by a PECVD process or other suitable deposition techniques.

[0134] Next, the ILD layers 235 and 280 are patterned to form a plurality of contact trenches on opposite sides of the gate structures 260 and 270, and then the CESL 230 is patterned to expose the source / drain epitaxial structures 210 and 215. In some embodiments, a plurality of etching processes are performed to pattern the ILD layers 235 and 280 and the CESL 230. The etching process includes a dry etching process, a wet etching process, or a combination thereof. In addition, during the etching of the ILD layer 280, a plurality of via holes are formed in the ILD layer 280 to expose the gate structures 260 and 270.

[0135] Source / drain contacts 291, 293, and 295 are formed in contact trenches, respectively, and gate holes 297 and 299 are formed in a plurality of through holes, respectively. Source / drain contact 291 connects one of a plurality of source / drain epitaxial structures 215, wherein this source / drain epitaxial structure 215 contacts one of a plurality of source / drain epitaxial structures 210. Source / drain contact 293 connects to another source / drain epitaxial structure 215 above isolation layer 220. Source / drain contact 295 connects to another source / drain epitaxial structure 210 covered by isolation layer 220. In addition, spacer layer 225 may be formed before forming source / drain contact 295, so that source / drain contact 295 is electrically isolated from source / drain epitaxial structure 215. Gate hole 297 connects to gate structure 260, and gate hole 299 connects to gate structure 270.

[0136] The formation of source / drain contacts 291, 293, and 295 and gate holes 297 and 299 includes depositing one or more conductive (e.g., metal) materials, wherein the conductive materials transitionally fill the contact trenches and vias, and then performing a CMP process to remove excess metal materials outside the contact trenches and vias. In some embodiments, the formation of the spacer 225 may include blanket forming a dielectric layer and then performing an etching operation to remove a horizontal portion of the dielectric layer. The remaining vertical portion of the dielectric layer forms the spacer 225. The spacer 225 includes one or more dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, SiCN, SiC x O y N z , high-k dielectric material, or a combination thereof). The spacer layer 225 may be formed using a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or plasma enhanced atomic layer deposition (PEALD).

[0137] exist FIG. 21A to FIG. 21CIn the embodiment, the integrated circuit structure 100a includes a bottom (nanostructure) transistor Tn and a top (nanostructure) transistor Tp above the bottom transistor Tn. The bottom transistor Tn includes a channel layer (epitaxial layer) 124, a gate structure 260 surrounding the channel layer 124, and a source / drain epitaxial structure 210 located on opposite sides and connected to the channel layer 124. The top transistor Tp includes a channel layer (epitaxial layer) 128, a gate structure 270 surrounding the channel layer 128, and a source / drain epitaxial structure 215 located on opposite sides and connected to the channel layer 128. In some embodiments, the bottom transistor Tn is an N-type transistor, and the top transistor Tp is a P-type transistor. In some other embodiments, the bottom transistor Tn is a P-type transistor, and the top transistor Tp is an N-type transistor.

[0138] The gate structures 260 and 270 are fork-blade gate structures. That is, the gate structure 260 contacts three sides of each channel layer 124 and is spaced apart from one side of each channel layer 124. Similarly, the gate structure 270 contacts three sides of each channel layer 128 and is spaced apart from one side of each channel layer 128. The height H1 of the gate structure 260 is substantially the same as the height H2 of the gate structure 270. FIG. 21A to FIG. 21C As shown, some portions of the gate structure 270 are located directly above the gate structure 260. In addition, the gate structure 260 is spaced apart from the channel layer 128, and the gate structure 270 is spaced apart from the channel layer 124. The bottom surface 261 of the gate structure 260 is substantially coplanar with the bottom surface 271 of the gate structure 270. In addition, both the gate structures 260 and 270 contact the isolation structure 140, wherein the isolation structure 140 is embedded in the substrate 110. The top surface 269 of the gate structure 260 is higher than the top surface 129 of the channel layer 128. The interfacial layer 262 of the gate structure 260 contacts the interfacial layer 272 of the gate structure 270. Therefore, the gate structure 260 is electrically isolated from the gate structure 270.

[0139] The integrated circuit structure 100a further includes a dielectric barrier layer 250 directly between the channel layer 128 and the gate structure 260. That is, opposite sides of the dielectric barrier layer 250 contact the channel layer 128 and the gate structure 260, respectively. The dielectric barrier layer 250 is surrounded by the gate structures 260 and 270 and contacts the channel layer 128. In addition, a vertical thickness T1 of the dielectric barrier layer 250 is substantially the same as a vertical thickness T2 of the channel layer 128. In addition, the dielectric barrier layer 250 is directly above the channel layer 124. The integrated circuit structure 100a further includes a dielectric barrier layer 255 directly between the channel layer 124 and the gate structure 270. That is, opposite sides of the dielectric barrier layer 255 contact the channel layer 124 and the gate structure 270, respectively. The dielectric barrier layer 255 is surrounded by the gate structures 260 and 270 and contacts the channel layer 124. In addition, the vertical thickness T3 of the dielectric barrier layer 255 is substantially the same as the vertical thickness T4 of the channel layer 124. In addition, the dielectric barrier layer 255 is directly below the channel layer 128.

[0140] The integrated circuit structure 100a further includes a plurality of internal spacers 180. Fig.21A and Fig. 21C As shown, at least one of the plurality of internal spacers 180 contacts both gate structures 260 and 270 and both channel layers 124 and 128. The integrated circuit structure 100a also includes a gate spacer 170. FIG. 21A to FIG. 21C As shown, the gate spacer 170 surrounds the gate structures 260 and 270. In other words, the gate spacer 170 contacts the gate structures 260 and 270.

[0141] Fig. 22 FIG. 1 is a cross-sectional view of an integrated circuit structure (semiconductor device) 100b according to some embodiments of the present application. The difference between the integrated circuit structure 100b and the integrated circuit structure 100a lies in the shape of the channel. Fig. 22 In the embodiment, the epitaxial layer 124 and the epitaxial layer 128 are nanowires, and the opposite end surfaces of the epitaxial layer 124 and the epitaxial layer 128 can be curved (for example, convex). Therefore, the interface between the epitaxial layer 124 (or the epitaxial layer 128) and the dielectric barrier layer 250 (or the dielectric barrier layer 255) is curved, and the surface of the dielectric barrier layer 250 (or the dielectric barrier layer 255) contacting the epitaxial layer 124 (or the epitaxial layer 128) is concave. In some embodiments, the epitaxial layer 124 and the epitaxial layer 128 (both in Fig. 22 and Fig. 21B The size (width / length / diameter) of the integrated circuit structure 100b is in the range of about 0.1 nm to about 1 um. In some other embodiments, the cross-section of the channel layer 124 and the channel layer 128 can be circular, elliptical, or diamond-shaped. Figure 1 , Figure 2, Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Fig. 9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B and Fig. 21C The integrated circuit structure 100a shown in FIG. 1 is similar or identical to the integrated circuit structure 100a shown in FIG. 1 , and therefore, will not be described again below.

[0142] In some embodiments, the integrated circuit structure 100 a and the integrated circuit structure 100 b may employ a tri-state buffer logic circuit. Fig.23 is a circuit diagram of a tri-state buffer logic circuit 10 according to some embodiments of the present application, Fig.24 FIG. 1 is a top view of a tri-state buffer logic circuit 10 according to some embodiments of the present application. FIG. 25A to FIG. 25D Draw the diagrams along Fig.24 For clarity, Fig.24 Only the gate and source / drain (eg, source / drain epitaxial structure 215 ) of the tri-state buffer logic circuit 10 are shown.

[0143] Specifically, the tri-state buffer logic circuit 10 includes transistors Tn1, Tn2, Tn3, Tn4, Tp1, Tp2, Tp3, and Tp4. The transistors Tp1, Tp2, Tn2, and Tn1 are connected in series, and the transistors Tp4, Tp3, Tn3, and Tn3 are connected in series. In addition, the sources of the transistors Tp2, Tp3, Tn2, and Tn3 are connected to each other and coupled to the input signal S D1 Input signal SD Coupled to the gates Gp1 and Gn1 of the transistors Tp1 and Tn1 (reference Fig.23 , Fig.24 and Fig.25A ), input signal S en Coupled to the gates Gp2 and Gn3 of transistors Tp2 and Tn3 (reference Fig.23 , Fig.24 , Fig.25B and Fig.25C ), input signal S enb Coupled to the gates Gp3 and Gn2 of transistors Tp3 and Tn2 (reference Fig.23 , Fig.24 , Fig.25B and Fig.25C ), and the input signal S Q Coupled to the gates Gp4 and Gn4 of transistors Tp4 and Tn4 (reference Fig.23 , Fig.24 and Fig.25D ).like Fig.24 As shown, since the gates Gp2 and Gn2 can be stacked and controlled separately, the layout area of ​​the tri-state buffer logic circuit 10 is dense, thereby reducing the standard unit area of ​​the circuit.

[0144] Fig.26A and Fig.26B According to some embodiments of the present application, the Fig.24 The cross-sectional diagram of the lines AA and DD. Fig.25A ) are connected to the input signal S D Therefore, the gates of transistors Tp1 and Tn1 can be combined into a common gate G1, wherein the common gate G1 can have the same Fig. 21B The gate structure 260 (or gate structure 270) shown in FIG. 2 may be similar to or identical to the gate structure 260 (or gate structure 270) shown in FIG. 2 . Therefore, the dielectric barrier layers 250 and 255 (see FIG. 2 ) may be omitted. Fig.25A ). Similarly, due to the gate Gp4 and Gn4 (reference Fig.25D ) are connected to the input signal S Q Therefore, the gates of transistors Tp4 and Tn4 can be combined into a common gate G4, wherein the common gate G4 can have the same Fig. 21B The gate structure 260 (or gate structure 270) shown in FIG. 1 may be configured similarly or identically to the gate structure 260 (or gate structure 270) shown in FIG. Therefore, the dielectric barrier layers 250 and 255 may be omitted. Other features of the tri-state buffer logic circuit 10 are similar to those of FIG. Figure 1 , Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Fig. 7A , Figure 7B , Figure 7C , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A , Fig. 17B , Fig.18A , Fig.18B , Fig.19A , Fig.19B , Fig. 20A , Fig. 20B , Fig.21A , Fig. 21B and Fig. 21C The integrated circuit structure 100 a shown is similar or identical, and therefore, will not be described further below.

[0145] Based on the above discussion, it can be seen that the present application provides some advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages must be disclosed in the present application, and all embodiments do not require specific advantages. One advantage is a separate gate structure that allows independent gate control. In addition, the layout area of ​​the gate structure is substantially the same as the common gate structure, so that the design flexibility of the circuit is increased without increasing the layout area. In addition, the fork-sheet gate structure provides gate control as good as the nanosheet gate structure.

[0146] According to some embodiments, the integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is above the substrate and includes a first channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first channel layer. The first source / drain epitaxial structure is on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor and includes a second channel layer, a second gate structure, and a second source / drain epitaxial structure. The second channel layer is above the first channel layer. The second gate structure surrounds the second channel layer. The bottom surface of the second gate structure is substantially coplanar with the bottom surface of the first gate structure. The second source / drain epitaxial structure is on opposite sides of the second channel layer.

[0147] In some embodiments, the interfacial layer of the first gate structure contacts the interfacial layer of the second gate structure.

[0148] In some embodiments, the integrated circuit structure further includes an inner spacer, wherein the inner spacer contacts the first channel layer and the second channel layer.

[0149] In some embodiments, the inner spacer contacts the first gate structure and the second gate structure.

[0150] In some embodiments, one of the first source / drain epitaxial structures contacts one of the second source / drain epitaxial structures.

[0151] In some embodiments, the integrated circuit structure further includes a dielectric barrier layer, wherein the dielectric barrier layer is directly between the first gate structure and the second channel layer.

[0152] In some embodiments, the vertical thickness of the dielectric barrier layer is substantially the same as the vertical thickness of the second channel layer.

[0153] In some embodiments, the dielectric barrier layer is directly above the first channel layer.

[0154] In some embodiments, the second gate structure is spaced apart from the first channel layer.

[0155] In some embodiments, a top surface of the first gate structure is higher than a top surface of the second channel layer.

[0156] According to some embodiments, an integrated circuit structure includes a substrate, an isolation structure, a bottom nanostructure transistor, and a top nanostructure transistor. The isolation structure is embedded in the substrate. The bottom nanostructure transistor is above the substrate and includes a first gate structure having a first fork shape, a first channel layer surrounded by the first gate structure, and a first source / drain epitaxial structure on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor and includes a second gate structure having a second fork shape, a second channel layer surrounded by the second gate structure, and a second source / drain epitaxial structure on opposite sides of the second channel layer. The first gate structure and the second gate structure both contact the isolation structure, and the first gate structure electrically isolates the second gate structure.

[0157] In some embodiments, a portion of the second gate structure is directly above the first gate structure.

[0158] In some embodiments, the integrated circuit structure further includes a gate spacer, wherein the gate spacer surrounds the first gate structure and the second gate structure.

[0159] In some embodiments, the first channel layer of the bottom nanostructure transistor is a nanowire.

[0160] In some embodiments, a height of the first gate structure is substantially the same as a height of the second gate structure.

[0161] In some embodiments, the integrated circuit structure further includes a dielectric barrier layer, wherein the dielectric barrier layer is surrounded by the first gate structure and the second gate structure, and the dielectric barrier layer contacts the first channel layer of the bottom nanostructure transistor.

[0162] According to some embodiments, a method for manufacturing an integrated circuit structure includes forming a fin structure above a substrate, wherein the fin structure includes a first channel layer, a first sacrificial layer, a second sacrificial layer, and a second channel layer stacked in sequence from bottom to top; forming a dummy gate structure to cover the fin structure; forming a gate spacer to surround the dummy gate structure; forming a first source / drain epitaxial structure and a second source / drain epitaxial structure, wherein the first source / drain epitaxial structure is on opposite sides of the first channel layer, and the second source / drain epitaxial structure is on opposite sides of the second channel layer; removing the dummy gate structure to form a gate trench defined by the gate spacer; removing the first sacrificial layer to release the first channel layer; forming a first fork-sheet gate structure in the gate trench to surround the first channel layer, wherein the first fork-sheet gate structure contacts the second sacrificial layer; removing the second sacrificial layer to release the second channel layer; and forming a second fork-sheet gate structure in the gate trench to surround the second channel layer.

[0163] In some embodiments, the method for manufacturing an integrated circuit structure further includes forming a dielectric barrier layer on an end surface of the second channel layer before forming the first fork-piece gate structure.

[0164] In some embodiments, the method for manufacturing an integrated circuit structure further includes forming an inner spacer on an end surface of the first sacrificial layer before forming the dielectric barrier layer.

[0165] In some embodiments, the first channel layer, the first sacrificial layer, the second sacrificial layer, and the second channel layer have different germanium concentrations.

[0166] According to some embodiments, an integrated circuit structure includes a substrate, a bottom nanostructure transistor, and a top nanostructure transistor. The bottom nanostructure transistor is above the substrate, wherein the bottom nanostructure transistor includes a first channel layer, a first gate structure, and a first source / drain epitaxial structure. The first gate structure surrounds the first channel layer. The first source / drain epitaxial structure is on opposite sides of the first channel layer. The top nanostructure transistor is above the bottom nanostructure transistor, wherein the top nanostructure transistor includes a second channel layer, a second gate structure, and a second source / drain epitaxial structure. The second channel layer is above the first channel layer. The second gate structure surrounds the second channel layer, wherein the bottom surface of the second gate structure is substantially coplanar with the bottom surface of the first gate structure, and the top surface of the first gate structure is higher than the top surface of the second channel layer. The second source / drain epitaxial structure is on opposite sides of the second channel layer.

[0167] The features of multiple embodiments are summarized above so that those skilled in the art can better understand the aspects of the present application. Those skilled in the art should understand that the present application can be easily used as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present application, and various changes, substitutions and modifications herein can be made without departing from the spirit and scope of the present application.

Claims

1. An integrated circuit structure, characterized in that: Include: a substrate; A bottom nanostructure transistor is disposed above the substrate, wherein the bottom nanostructure transistor comprises: a first channel layer; a first gate structure surrounding the first channel layer; and a first source / drain epitaxial structure on opposite sides of the first channel layer; and a top nanostructure transistor above the bottom nanostructure transistor, wherein the top nanostructure transistor comprises: a second channel layer above the first channel layer; a second gate structure surrounding the second channel layer, wherein a bottom surface of the second gate structure is coplanar with a bottom surface of the first gate structure; and A second source / drain epitaxial structure is on opposite sides of the second channel layer.

2. An integrated circuit structure, characterized in that: Include: a substrate; A bottom nanostructure transistor is disposed above the substrate, wherein the bottom nanostructure transistor comprises: a first channel layer; a first gate structure surrounding the first channel layer; and a first source / drain epitaxial structure on opposite sides of the first channel layer; and a top nanostructure transistor above the bottom nanostructure transistor, wherein the top nanostructure transistor comprises: a second channel layer above the first channel layer; a second gate structure surrounding the second channel layer, wherein a bottom surface of the second gate structure is coplanar with a bottom surface of the first gate structure, and a top surface of the first gate structure is higher than a top surface of the second channel layer; as well as A second source / drain epitaxial structure is on opposite sides of the second channel layer.

3. An integrated circuit structure, characterized in that: Include: a substrate; an isolation structure embedded in the substrate; A bottom nanostructure transistor is disposed above the substrate, wherein the bottom nanostructure transistor comprises: a first gate structure having a first fork shape; a first channel layer surrounded by the first gate structure; and a first source / drain epitaxial structure on opposite sides of the first channel layer; and a top nanostructure transistor above the bottom nanostructure transistor, wherein the top nanostructure transistor comprises: a second gate structure having a second fork shape, wherein the first gate structure and the second gate structure both contact the isolation structure, and the first gate structure electrically isolates the second gate structure; a second channel layer surrounded by the second gate structure; and A second source / drain epitaxial structure is on opposite sides of the second channel layer.

4. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: An interface layer of the first gate structure contacts an interface layer of the second gate structure.

5. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: An inner spacer is also included, wherein the inner spacer contacts the first channel layer and the second channel layer.

6. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: One of the first source / drain epitaxial structures contacts one of the second source / drain epitaxial structures.

7. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: A dielectric barrier layer is also included, wherein the dielectric barrier layer is directly between the first gate structure and the second channel layer.

8. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: A height of the first gate structure is the same as a height of the second gate structure.

9. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: A portion of the second gate structure is directly above the first gate structure.

10. The integrated circuit structure according to claim 1, 2 or 3, characterized in that: A gate spacer is also included, wherein the gate spacer surrounds the first gate structure and the second gate structure.

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