Film coating support plate and film coating equipment for vacuum adsorption of silicon wafer
By designing a coated carrier plate for vacuum adsorption silicon wafers, using the combined structure of the accommodating groove and vacuum holes, the problems of low target utilization and shaking and crushing of silicon wafers are solved, and cost reduction and coating effect are improved.
Patent Information
- Application Number
- CN202421174507.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-27
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2034-05-27
AI Technical Summary
During the preparation of existing heterojunction batteries, the effective utilization rate of the target material is low, resulting in high non-silicon costs, and the shaking of the silicon wafer in the coated carrier plate may lead to breakage.
A coating carrier plate for vacuum adsorbing silicon wafers is designed. The carrier plate includes multiple accommodation grooves, each accommodation groove has a side wall through hole and a vacuum hole near the inner side wall, and the silicon wafer is embedded in the accommodation groove through vacuum adsorption.
It improves the effective utilization rate of target materials, reduces the preparation cost of heterojunction batteries, and reduces the probability of silicon wafer breaking due to shaking.
Smart Images
Figure CN222631531U_ABST
Abstract
Description
Technical Field
[0001] The utility model belongs to the technical field of photovoltaic cells, and in particular relates to a coating carrier plate and coating equipment for vacuum adsorbing silicon slices. Background Art
[0002] Heterojunction cells have the advantages of high efficiency, high opening voltage, low temperature coefficient, high bifaciality, easy thinning, low temperature production process and short process, but they have the disadvantages of high non-silicon cost and high equipment cost. In the preparation process of heterojunction cells, the target material in the non-silicon cost can play the role of reducing reflection and increasing light absorption of the blue film (TCO film), can protect the microcrystalline film amorphous silicon film, and can make up for the problem of weak lateral transmission of carriers in the microcrystalline film amorphous silicon film. The target material plays a vital role in heterojunction cells. Under the premise that the target material is indispensable, improving the effective utilization rate of the target material has become an important way to reduce the non-silicon cost.
[0003] One of the important processes in preparing heterojunction batteries is the PVD process. The existing PVD process mainly includes: the silicon wafers that have completed the CVD process are automatically loaded onto the coating carrier, the coating carrier carries the silicon wafers and is transported to the inside of the PVD equipment, the target material on the surface of the cylindrical arc is bombarded by gas Ar, and the ITO target material molecules are sputtered onto the surface of the silicon wafer. After sputtering is completed, the coating carrier is transported to the unloading station for unloading.
[0004] The coating carrier generally includes multiple step-shaped grooves. In order to allow the silicon wafer to be placed normally, the size of the step-shaped groove will be slightly larger than the size of the silicon wafer. Since there is a certain gap between the silicon wafer and the wall of the step-shaped groove, the silicon wafer will shake in the groove; in addition, due to the presence of the steps, the area of the carrier support area is increased, reducing the effective utilization rate of the target material. Utility Model Content
[0005] The utility model aims to solve one of the technical problems in the related art at least to a certain extent.
[0006] In the first aspect of the utility model, the utility model proposes a coating carrier for vacuum adsorption of silicon wafers, the coating carrier comprising at least two receiving grooves for accommodating silicon wafers, characterized in that the receiving groove comprises a bottom wall of the receiving groove and a side wall of the receiving groove extending outward from the bottom wall of the receiving groove, the side wall of the receiving groove has at least one through hole, and a vacuum hole is provided near the inner side wall of the receiving groove. Thus, the effective utilization rate of the target material can be effectively improved, the preparation cost of the heterojunction battery can be reduced, and the probability of the silicon wafer embedded in the receiving groove being broken due to shaking can be reduced.
[0007] According to some embodiments of the present invention, the bottom wall of the receiving groove does not have a through hole. Therefore, during the vacuuming process through the vacuum hole, the silicon wafer is more easily embedded in the receiving groove, which can effectively reduce the time for the silicon wafer to be embedded in the receiving groove.
[0008] According to some embodiments of the present invention, the number of the vacuum holes is 16 to 80. Therefore, during the process of evacuating the vacuum holes, the silicon wafer is more easily embedded in the receiving groove, which can effectively reduce the time for the silicon wafer to be embedded in the receiving groove.
[0009] According to some embodiments of the present invention, the cross-sectional area of a single vacuum hole is 0.00785 mm 2 -0.1256mm 2 Therefore, during the process of evacuating the vacuum through the vacuum hole, the silicon wafer can be more easily embedded in the receiving groove, which can effectively reduce the time for the silicon wafer to be embedded in the receiving groove.
[0010] According to some embodiments of the present invention, along the width direction, the vertical distance between the edge of the silicon wafer to be adsorbed and the side wall of the receiving groove is L. 1 , 0.2≤L 1 ≤1mm. In this way, the effective coating area of the coating carrier can be effectively increased, the effective utilization rate of the target material can be improved, and the probability of shaking during the movement of the coating carrier carrying the silicon wafer can be reduced.
[0011] According to some embodiments of the present invention, the size of the silicon wafer to be adsorbed along the thickness direction is H 1 , the depth of the receiving groove is H 2 , H 1 :H 2 is 1:(0.5-1.2).
[0012] According to some embodiments of the present invention, H 1 :H 2 The ratio of ITO target material to silicon wafer is 1:(0.5-1.0). In this way, the ITO target material molecules can be sputtered onto the surface of the silicon wafer, so that the silicon wafer has a better coating effect, and the silicon wafer can be effectively prevented from falling off from the receiving groove.
[0013] According to some embodiments of the present invention, the coated carrier further includes a supporting structure, wherein the supporting structure includes a first supporting portion and a second supporting portion connected to each other, wherein the first supporting portion is located between adjacent accommodating grooves, and the second supporting portion is located at an edge of the coated carrier.
[0014] According to some embodiments of the utility model, the material of the film-coated carrier plate includes stainless steel, so that the film-coated carrier plate has the advantages of being lightweight, inexpensive, not easy to oxidize, not easy to deform, etc.
[0015] According to some embodiments of the utility model, in the receiving groove, the bottom wall of the receiving groove is perpendicular to the side wall of the receiving groove, thereby effectively preventing the silicon wafer embedded in the receiving groove from falling off.
[0016] In the second aspect of the present invention, the present invention provides a coating device, wherein the coating device comprises the aforementioned coating carrier plate. Therefore, the coating device has all the advantages of the aforementioned coating carrier plate, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:
[0018] Figure 1 is a schematic diagram of an existing coated carrier board;
[0019] Figure 2 yes Figure 1 Schematic diagram of a stepped groove;
[0020] Figure 3 is a schematic diagram of a coating carrier board of some embodiments of the utility model;
[0021] Figure 4 It is a schematic diagram of a receiving groove of a coating carrier board in some embodiments of the utility model;
[0022] Figure 5 Schematic diagram of vacuum holes in some embodiments of the present invention.
[0023] Reference numerals:
[0024] 1-step-shaped groove; 1-1-step; 100-accommodating groove; 110-through hole; 200-support structure; 210-first supporting part; 220-second supporting part; 1000-silicon wafer. DETAILED DESCRIPTION
[0025] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.
[0026] In the description of the present utility model, it should be understood that the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features.
[0027] In the present invention, unless otherwise clearly defined and limited, the terms such as "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection. It can be a mechanical connection or an electrical connection. It can be directly connected or indirectly connected through an intermediate medium. It can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0028] In order to reduce the movement of the silicon wafer during the machine movement and improve the coating effect of the silicon wafer, the coating carrier generally includes a plurality of step-shaped grooves 1, referring to Figure 1 and Figure 2 , insert the silicon wafer into the step-shaped groove 1, and then coat it, so as to reduce the shaking of the silicon wafer in the coating carrier during the moving process. However, in order to put the silicon wafer in normally, the size of the step-shaped groove 1 will be slightly larger than the size of the silicon wafer. Usually, the distance between the silicon wafer and the wall of the step-shaped groove is 3 mm-4 mm. Since there is a certain gap between the silicon wafer and the wall of the step-shaped groove, the silicon wafer will still shake in the groove; in addition, due to the existence of step 1-1, the area of the carrier support area is increased, which reduces the effective utilization rate of the target material.
[0029] In order to improve the effective utilization rate of the target material, the applicant proposed the following solution.
[0030] In the first aspect of the present invention, the present invention provides a coating carrier for vacuum adsorbing silicon wafer 1000, referring to Figure 3 The coating carrier includes at least two receiving grooves 100 for receiving silicon wafers 1000. The receiving grooves 100 include a bottom wall and a side wall extending outward from the bottom wall. The side wall has at least one through hole 110. A vacuum hole is provided near the inner wall of the receiving groove 100. Thus, the effective utilization rate of the target material can be effectively improved, the preparation cost of the heterojunction battery can be reduced, and the probability of the silicon wafer 1000 embedded in the receiving groove 100 being broken due to shaking can be reduced.
[0031] The following is an explanation of how the aforementioned vacuum adsorption coating carrier of the silicon wafer 1000 can achieve the aforementioned technical effects:
[0032] The utility model provides at least one through hole 110 on the side wall of the receiving groove, and a vacuum hole is provided near the inner wall of the receiving groove 100. First, after the silicon wafer 1000 completes the CVD process, the silicon wafer 1000 will be transferred to the upper part of the receiving groove 100 of the coating carrier, and then, the vacuum hole near the inner wall of the receiving groove 100 is used for vacuuming. As the vacuuming process proceeds, the silicon wafer 1000 will gradually be embedded in the receiving groove 100. After all the silicon wafers 1000 to be coated are embedded in the corresponding receiving groove 100, the coating carrier carries the silicon wafer 1000 and is transferred to the inside of the PVD equipment. The target material on the surface of the cylindrical arc is bombarded by gas Ar, and the target material molecules are sputtered onto the surface of the silicon wafer 1000. Finally, after the sputtering is completed, the coating carrier will be transferred to the unloading area, and the vacuuming state will be ended at this moment, and the coated silicon wafer 1000 can be removed. It should be noted that during the coating process, the silicon wafer 1000 is always in a vacuuming state.
[0033] The utility model embeds the silicon wafer 1000 into the receiving groove 100 of the coating carrier by vacuum adsorption. Compared with the existing step-type groove, the utility model has the following beneficial effects: (1) the gap between the silicon wafer 1000 and the inner wall of the receiving groove 100 can be greatly reduced, thereby increasing the effective coating area of the coating carrier, improving the effective utilization rate of the target material, and reducing the preparation cost of the heterojunction battery; (2) the existence of the step in the step-type groove is eliminated, thereby increasing the effective coating area of the coating carrier, improving the effective utilization rate of the target material, and reducing the preparation cost of the heterojunction battery; (3) since the gap between the silicon wafer 1000 and the inner wall of the receiving groove 100 is extremely small, the coating carrier is not prone to shaking during the movement of the silicon wafer 1000, thereby reducing the probability of the silicon wafer 1000 being broken due to shaking.
[0034] As a preferred solution, refer to Figure 3 , the bottom wall of the receiving groove does not have a through hole 110. Therefore, during the vacuuming process through the vacuum hole, the silicon chip 1000 is more easily embedded in the receiving groove 100, which can effectively reduce the time for the silicon chip 1000 to be embedded in the receiving groove 100.
[0035] In some embodiments, reference Figure 3 In the receiving groove 100, the bottom wall of the receiving groove is perpendicular to the side wall of the receiving groove. Therefore, setting the bottom wall of the receiving groove perpendicular to the side wall of the receiving groove can effectively prevent the silicon chip 1000 embedded in the receiving groove 100 from falling off.
[0036] In some embodiments, the specific operation method of vacuuming and the specific pressure in the vacuuming environment can be set by those skilled in the art according to actual conditions and will not be described in detail here.
[0037] In some embodiments, reference Figure 3, along the width direction, the vertical distance between the edge of the silicon wafer 1000 to be adsorbed and the side wall of the receiving groove is L 1 , 0.2≤L 1 ≤1mm.
[0038] As a specific example, L 1 It can be 0.2mm, 0.3mm, 0.4mm, 0.5mm, 0.6mm, 0.7mm, 0.8mm, 0.9mm or 1mm.
[0039] L 1 Within the above range, L 1 The size of L is moderate, which can effectively increase the effective coating area of the coating carrier and improve the effective utilization rate of the target material, and can also reduce the probability of shaking during the movement of the coating carrier carrying the silicon wafer 1000. In addition, it is helpful to avoid L 1 If the coating carrier is too large, the silicon wafer 1000 may shake during the movement, causing the silicon wafer 1000 to break due to the shaking. 1 If the size is too small, the silicon chip 1000 is not easily inserted into the receiving groove 100 .
[0040] In some embodiments, along the thickness direction, the size of the silicon wafer 1000 to be adsorbed is H 1 , the depth of the receiving groove 100 is H 2 , H 1 :H 2 is 1:(0.5-1.2).
[0041] Preferably, H 1 :H 2 is 1:(0.5-1.0), for example H 1 :H 2 It can be 1:0.5, 1:0.6, 1:0.7, 1:0.8, 1:0.9 or 1:1.0.
[0042] H 1 and H 2 The ratio of is limited to the aforementioned range, which can not only sputter the ITO target molecules onto the surface of the silicon wafer 1000, so that the silicon wafer 1000 has a better coating effect, but also effectively prevent the silicon wafer 1000 from falling off from the receiving groove 100, and in addition, it is beneficial to avoid H 1 and H 2 If the ratio is too large, the silicon wafer 1000 will be embedded in the receiving groove 100, so that the silicon wafer 1000 is easy to fall out of the receiving groove 100. 1 and H 2 If the ratio is too small, the receiving groove 100 is too deep, and it is not easy to sputter the ITO target molecules onto the surface of the silicon wafer 1000, and the coating effect of the silicon wafer 1000 is poor.
[0043] It should be noted that the depth direction of the present invention is perpendicular to the width direction, and perpendicular to the paper surface and inwards.
[0044] In some embodiments, the number of vacuum holes is 16-80. For example, the number may be 16, 25, 35, 45, 55, 65, 75 or 80. Therefore, by limiting the number of vacuum holes to the aforementioned range, the silicon wafer 1000 is easily embedded in the receiving groove 100 during the vacuuming process through the vacuum holes, which can effectively reduce the time for the silicon wafer 1000 to be embedded in the receiving groove 100, and is conducive to avoiding the situation where the number of vacuum holes is too small, resulting in the silicon wafer 1000 being difficult to be embedded in the receiving groove 100, and the silicon wafer 1000 is embedded in the receiving groove 100 for a long time, or the number of vacuum holes is too large, which increases the preparation cost of the coating carrier.
[0045] In some embodiments, the cross-sectional area of a single vacuum hole is 0.00785 mm 2 -0.1256mm 2 . For example, it can be 0.00785mm 2 、0.00885mm 2 、0.00985mm 2 , 0.01mm 2 、0.011mm 2 or 0.1256mm 2 Thus, the cross-sectional area of a single vacuum hole is controlled within the aforementioned range, and during the vacuuming process through the vacuum hole, the silicon wafer 1000 is easily embedded in the receiving groove 100, which can effectively reduce the time for the silicon wafer 1000 to be embedded in the receiving groove 100.
[0046] In some embodiments, the shapes of the vacuum holes include circle, square, diamond, pentagram, etc.
[0047] In some embodiments, the coating carrier further includes a support structure 200, the support structure 200 includes a first support portion 210 and a first support portion 220 connected to each other, the first support portion 210 is located between adjacent receiving grooves 100, and the first support portion 220 is located at the edge of the coating carrier. Therefore, by providing the first support portion 210 and the first support portion 220 in the support structure 200, the first support portion 210 can effectively support the receiving groove 100, and the first support portion 220 can be used as an outer frame portion of the coating carrier, so that it is beneficial for the coating carrier to carry the silicon wafer 1000 for coating.
[0048] In some embodiments, the material of the coated carrier plate includes stainless steel, so that the coated carrier plate has the advantages of being lightweight, inexpensive, not prone to oxidation, and not prone to deformation.
[0049] In some embodiments, the number of the receiving slots 100 in the coating carrier can be multiple, for example, 2, 5, 10, 30, 50, 80, etc., and those skilled in the art can set it according to actual needs.
[0050] In the second aspect of the present invention, the present invention provides a coating device, wherein the coating device comprises the aforementioned coating carrier plate. Therefore, the coating device has all the advantages of the aforementioned coating carrier plate, which will not be described in detail here.
[0051] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the utility model. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.
[0052] Example 1
[0053] The vacuum adsorption silicon wafer coating carrier of the utility model is embedded in the M2 silicon wafer for coating. The vacuum adsorption silicon wafer coating carrier can refer to Figure 3 ;
[0054] There are 80 M2 silicon wafers on the carrier board, and the area of a single M2 silicon wafer is 24432mm 2 The total area of the M2 silicon wafer is 24432mm 2 *80 = 1954560 mm 2 During the coating process, the target material will sputter except for the carrier area of the second support portion. The gap between the silicon wafer and the inner side wall of the storage is extremely small and there is no step in the step-type groove. Target material coverage area = 1383.52mm*1724.99mm = 2384953.92mm 2 , the effective utilization rate of the target material = the total area of the M2 silicon wafer / the target material coverage area = 81.95%.
[0055] Comparative Example 1
[0056] Use the existing coating substrate to embed the M2 silicon wafer for coating. The existing coating substrate can be referenced Figure 1 ;
[0057] There are 80 M2 silicon wafers on the carrier board, and the area of a single M2 silicon wafer is 24432mm 2The total area of the M2 silicon wafer is 24432mm 2 *80 = 1954560 mm 2 Target coverage area = 1438.59mm*1793.98mm = 2580801.69mm 2 , the effective utilization rate of the target material = the total area of the M2 silicon wafer / the target material coverage area = 75.73%.
[0058] Assuming that the total consumption of the target material is 120 kg, the M2 silicon wafer (surface area of 156.75 mm*156.75 mm, thickness of 150 um) is coated, and the results in Table 1 are obtained;
[0059] Table 1
[0060]
[0061] Analyzing Table 1, compared with the existing coating carrier of comparative example 1, Example 1 adopts a coating carrier of vacuum adsorbed silicon wafers embedded in M2 silicon wafers for coating, which significantly improves the effective utilization rate of the target material; compared with the existing coating carrier of comparative example 1 for coating, the unit consumption of the target material of the utility model can be reduced by 2.51 mg / piece. Calculated based on the unit price of the target material of 2,600 yuan / kg, the cost of each GW heterojunction battery can be saved by 1.1187 million yuan per year. Therefore, the coating carrier of vacuum adsorbed silicon wafers embedded in M2 silicon wafers for coating can bring great economic benefits.
[0062] Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations of the present invention. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present invention.
Claims
1. A coating carrier for vacuum adsorbing silicon wafers, the coating carrier comprising at least two receiving grooves for accommodating silicon wafers, characterized in that: The receiving groove comprises a bottom wall and a side wall extending outwardly from the bottom wall. The side wall has at least one through hole. A vacuum hole is arranged near the inner side of the side wall.
2. The coating carrier according to claim 1, characterized in that: The bottom wall of the accommodating groove has no through hole.
3. The coating carrier according to claim 2, characterized in that: The number of the vacuum holes is 16-80; And / or, the cross-sectional area of a single vacuum hole is 0.00785 mm 2 -0.1256mm 2 .
4. The coating carrier according to any one of claims 1 to 3, characterized in that: Along the width direction, the vertical distance between the edge of the silicon wafer to be adsorbed and the side wall of the receiving groove is L1, 0.2≤L1≤1mm.
5. The coating carrier according to any one of claims 1 to 3, characterized in that: Along the thickness direction, the size of the silicon wafer to be adsorbed is H1, the depth of the receiving groove is H2, and H1:H2 is 1:0.5-1.
2.
6. The coating carrier according to claim 5, characterized in that: H1:H2 is 1:0.5-1.
0.
7. The coating carrier according to any one of claims 1 to 3, characterized in that: The coating carrier also includes a support structure, which includes a first support portion and a second support portion connected to each other, wherein the first support portion is located between adjacent accommodating grooves, and the second support portion is located at an edge of the coating carrier.
8. The coating carrier according to any one of claims 1 to 3, characterized in that: The material of the coating carrier plate includes stainless steel.
9. The coating carrier according to any one of claims 1 to 3, characterized in that: In the receiving groove, the bottom wall of the receiving groove is perpendicular to the side wall of the receiving groove.
10. A coating device, characterized in that: The invention comprises the coating carrier plate as described in any one of claims 1 to 9.