Monitoring circuit of display module and display device

Abstract

The utility model relates to the technical field of display, and discloses a monitoring circuit and method of a display module and a display device. The display module comprises a display panel and a display circuit, the display circuit comprises a main controller, a first controller, a first power manager and a level shifter, the output end of the first controller is electrically connected to the input end of the level shifter, and the first controller is configured to output a display signal required by the display panel. The first power manager is configured to provide a voltage signal to the first controller; the monitoring circuit comprises a second controller, the input end of the second controller is electrically connected to the output end of the first power manager and electrically connected to the output end of the first controller through a level shifter, and the second controller is configured to monitor the display state of the display panel according to the display signal and / or the voltage signal. The output end of the level shifter is electrically connected to the input end of the display panel and the input end of the second controller. The monitoring circuit reduces technical difficulty and user cost.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a monitoring circuit of a display module and a display device including the monitoring circuit of the display module. Background Art

[0002] At present, it is difficult to detect whether the display status of the display is normal or abnormal in time, which affects the user experience. It may be necessary to view it directly with the human eye or use machine vision to make a judgment. Direct viewing with the human eye requires staff to monitor it at all times, which wastes a lot of human resources. Using machine vision to make a judgment requires image acquisition and image processing, which requires additional equipment and is technically difficult, increasing user costs.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Utility Model Content

[0004] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and to provide a monitoring circuit of a display module and a display device including the monitoring circuit of the display module.

[0005] According to one aspect of the present disclosure, a monitoring circuit of a display module is provided, wherein the display module comprises a display panel and a display circuit, wherein the display circuit comprises a main controller, a first controller, a first power manager and a level converter, wherein an input end of the first controller is electrically connected to an output end of the first power manager and an output end of the main controller, an output end of the first controller is electrically connected to an input end of the level converter, the first controller is configured to output a display signal required by the display panel through the level converter according to an instruction of the main controller, and the first power manager is configured to provide a voltage signal to the first controller; the monitoring circuit comprises:

[0006] A second controller, wherein the input end of the second controller is electrically connected to the output end of the first power manager and is electrically connected to the output end of the first controller through the level converter, and the second controller is configured to monitor the display state of the display panel according to the display signal and / or the voltage signal, wherein the output end of the level converter is electrically connected to the input end of the display panel and the input end of the second controller.

[0007] In an exemplary embodiment of the present disclosure, the display module also includes a backlight module, and the display circuit also includes a backlight driving circuit, the backlight driving circuit is configured to provide a backlight signal to the backlight module, and the output end of the backlight driving circuit is electrically connected to the second controller and the input end of the backlight module.

[0008] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0009] A signal processing circuit, wherein the signal processing circuit comprises a first signal processing circuit, wherein the first signal processing circuit is configured to process a DC digital voltage signal in the voltage signal, and the first signal processing circuit comprises:

[0010] a first emitter follower unit, electrically connected to an output terminal of the first power manager, wherein the first emitter follower unit is configured to collect a DC digital voltage signal in the voltage signal and prevent the DC digital voltage signal from flowing back to the display circuit;

[0011] A first analog-to-digital conversion unit is electrically connected to the output end of the first emitter follower unit; the second controller is electrically connected to the output end of the first analog-to-digital conversion unit, and the second controller is configured to output the display state of the display panel as a first abnormal display state. In the first abnormal display state, the DC digital voltage signal has a first set value.

[0012] In an exemplary embodiment of the present disclosure, the first set value is less than 3.0V or greater than 3.6V.

[0013] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0014] The signal processing circuit includes a second signal processing circuit, the second signal processing circuit is configured to process a DC analog voltage signal in the voltage signal, and the second signal processing circuit includes:

[0015] a second emitter follower unit, electrically connected to the output end of the first power manager, the second emitter follower unit being configured to collect a DC analog voltage signal in the voltage signal and prevent the DC analog voltage signal from flowing back to the display circuit;

[0016] a second voltage dividing unit, electrically connected to the output end of the second emitter follower unit, and the second voltage dividing unit is configured to adjust the value of the DC analog voltage signal to a fixed voltage;

[0017] A second analog-to-digital conversion unit, electrically connected to an output end of the second voltage dividing unit;

[0018] The second controller is electrically connected to the output end of the second analog-to-digital conversion unit, and the second controller is configured to output the display state of the display panel as a second abnormal display state. In the second abnormal display state, the DC analog voltage signal has a second set value.

[0019] In an exemplary embodiment of the present disclosure, the second set value is less than 15V or greater than 17V.

[0020] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0021] A signal processing circuit, wherein the signal processing circuit includes a third signal processing circuit, wherein the third signal processing circuit is configured to process a frame start signal in the display signal, and the third signal processing circuit includes:

[0022] a third emitter follower unit, electrically connected to the output end of the level converter, wherein the third emitter follower unit is configured to collect a frame start signal in the display signal and prevent the frame start signal from flowing back to the display circuit;

[0023] a third voltage dividing unit, electrically connected to the output end of the third emitter follower unit, and configured to adjust the voltage value of the frame start signal to a fixed voltage;

[0024] A first timing unit, electrically connected to the output end of the third voltage dividing unit;

[0025] The second controller is electrically connected to the output end of the first timing unit, and is configured to output that the display state of the display panel is a third abnormal display state, in which the frequency of the frame start signal has a third set value.

[0026] In an exemplary embodiment of the present disclosure, the third setting value is less than 58 Hz or greater than 62 Hz.

[0027] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0028] A signal processing circuit, wherein the signal processing circuit includes a fourth signal processing circuit, wherein the fourth signal processing circuit is configured to process a reset signal in the display signal, and the fourth signal processing circuit includes:

[0029] a fourth emitter follower unit, electrically connected to the output end of the level converter, wherein the fourth emitter follower unit is configured to collect a reset signal in the display signal and prevent the reset signal from flowing back to the display circuit;

[0030] a fourth voltage dividing unit, electrically connected to the output end of the fourth emitter follower unit, and configured to adjust the voltage value of the reset signal to a fixed voltage;

[0031] A second timing unit, electrically connected to the output end of the fourth voltage dividing unit;

[0032] The second controller is electrically connected to the output end of the second timing unit, and the second controller is configured to output the display state of the display panel as a fourth abnormal display state. In the fourth abnormal display state, the frequency of the reset signal has a fourth set value.

[0033] In an exemplary embodiment of the present disclosure, the fourth setting value is less than 56 Hz or greater than 60 Hz, or the fourth setting value is less than 1.5 kHz or greater than 1.9 kHz.

[0034] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0035] A signal processing circuit, wherein the signal processing circuit includes a plurality of fifth signal processing circuits, wherein the fifth signal processing circuit is configured to process a clock signal in the display signal, and the fifth signal processing circuit includes:

[0036] a fifth emitter follower unit, electrically connected to the output end of the level converter, wherein the fifth emitter follower unit is configured to collect a clock signal in the display signal and prevent the clock signal from flowing back to the display circuit;

[0037] a fifth voltage dividing unit, electrically connected to the output end of the fifth emitter follower unit, and configured to adjust the voltage value of the clock signal to a fixed voltage;

[0038] A plurality of third timing units, electrically connected to the output ends of the plurality of fifth voltage dividing units in a one-to-one correspondence;

[0039] The second controller is electrically connected to the output ends of the plurality of third timing units; the second controller is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal has a fifth set value.

[0040] In an exemplary embodiment of the present disclosure, the fifth set value is less than 22.5 kHz or greater than 22.9 kHz.

[0041] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0042] A signal processing circuit, wherein the signal processing circuit comprises a sixth signal processing circuit, wherein the sixth signal processing circuit is configured to process a cathode voltage signal in the backlight signal, and the sixth signal processing circuit comprises:

[0043] a sixth emitter follower unit, electrically connected to the backlight driving circuit, the sixth emitter follower unit being configured to collect a cathode voltage signal in the backlight signal and prevent the cathode voltage signal from flowing back to the display circuit;

[0044] A third analog-to-digital conversion unit, electrically connected to the output end of the sixth emitter follower unit;

[0045] The second controller is electrically connected to the output end of the third analog-to-digital conversion unit, and the second controller is configured to output that the display state of the display panel is a sixth abnormal display state, and in the sixth abnormal display state, the cathode voltage signal has a sixth preset value.

[0046] In an exemplary embodiment of the present disclosure, the sixth preset value is less than 0.25V or greater than 0.5V.

[0047] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0048] A signal processing circuit, wherein the signal processing circuit is configured to process a working signal, the signal processing circuit comprises an emitter follower unit and a voltage divider unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage divider unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current, and the voltage divider unit is configured to adjust the voltage of the working signal;

[0049] The working signal includes at least any one of the voltage signal, the display signal, and the backlight signal;

[0050] The second controller is configured to determine whether the voltage signal, the display signal and the backlight signal in the working signal are all normal, and if so, determine that the display state of the display panel is a normal display state.

[0051] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0052] A signal processing circuit, wherein the signal processing circuit is configured to process a working signal, the signal processing circuit comprises an emitter follower unit and a voltage divider unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage divider unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current, and the voltage divider unit is configured to adjust the voltage of the working signal;

[0053] The working signal at least includes any one of the DC digital voltage signal and the DC analog voltage signal in the voltage signal, the frame start signal, the reset signal and the clock signal in the display signal, and the cathode voltage signal in the backlight signal;

[0054] The second controller is configured to determine whether the working signal satisfies all the following conditions, and if so, determines that the display state of the display panel is a normal display state: the DC digital voltage signal is greater than or equal to 3.0V and less than or equal to 3.6V; the DC analog voltage signal is greater than or equal to 15V and less than or equal to 17V; the frame start signal is greater than or equal to 58Hz and less than or equal to 62Hz; the reset signal is greater than or equal to 56Hz and less than or equal to 60Hz, or the reset signal is greater than or equal to 1.5kHz and less than or equal to 1.9kHz; the clock signal is greater than or equal to 22.5kHz and less than or equal to 22.9kHz; the cathode voltage signal is greater than or equal to 0.25V and less than or equal to 0.5V.

[0055] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0056] The second power manager is electrically connected to the signal processing circuit and the second controller, and the second power manager is configured to supply power to the signal processing circuit and the second controller.

[0057] In an exemplary embodiment of the present disclosure, the monitoring circuit further includes:

[0058] The second power manager is electrically connected to the monitoring circuit, and the second power manager is configured to supply power to the monitoring circuit.

[0059] In an exemplary embodiment of the present disclosure, at least a portion of the monitoring circuit and at least a portion of the display circuit are disposed on a same circuit board.

[0060] In an exemplary embodiment of the present disclosure, the display circuit further includes:

[0061] a backlight driving controller, wherein an output end of the backlight driving controller is electrically connected to an input end of the second controller and the backlight driving circuit, and the backlight driving controller is configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller;

[0062] The input end of the second controller is electrically connected to the output end of the backlight driving controller and is electrically connected to the output end of the first controller through the level converter. The second controller is configured to determine the display state of the display panel by judging whether the second error identification signal is received.

[0063] In an exemplary embodiment of the present disclosure, the display module further includes a backlight module, the display circuit further includes a backlight driving controller, and an output end of the backlight driving controller is electrically connected to an input end of the second controller and the backlight module;

[0064] The backlight driving controller is configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller, and the first controller is configured to output a display signal required by the display panel or a first error identification signal according to a working state of the level converter;

[0065] The input end of the second controller is electrically connected to the output end of the backlight drive controller, and is electrically connected to the output end of the first controller through the level converter. The second controller is configured to determine the display state of the display panel by judging whether the first error identification signal and / or the second error identification signal is received.

[0066] According to another aspect of the present disclosure, a monitoring circuit of a display module is provided, wherein the display module comprises a backlight module, a display panel and a display circuit, wherein the display circuit comprises a main controller, a first controller, a backlight driving controller and a level converter, wherein an input end of the first controller is electrically connected to an output end of the main controller, an output end of the first controller is electrically connected to an input end of the level converter, and an output end of the backlight driving controller is electrically connected to an input end of the backlight module; the first controller is configured to output a display signal or a first error identification signal required by the display panel according to a working state of the level converter, and the backlight driving controller is configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller;

[0067] The monitoring circuit comprises:

[0068] A second controller, wherein the input end of the second controller is electrically connected to the output end of the backlight drive controller and is electrically connected to the output end of the first controller through the level converter, and the second controller is configured to determine the display state of the display panel by determining whether the first error identification signal and / or the second error identification signal is received.

[0069] According to another aspect of the present disclosure, there is provided a display device, comprising:

[0070] Display module, including display panel and display circuit;

[0071] The monitoring circuit is any one of the monitoring circuits described above, and the monitoring circuit is electrically connected to the display circuit.

[0072] In the monitoring circuit of the display module disclosed in the present invention, the input end of the second controller is electrically connected to the output end of the first power manager, and is electrically connected to the output end of the first controller through a level converter. The second controller is configured to monitor the display status of the display panel according to the display signal and / or the voltage signal. There is no need to observe whether the display module displays normally through human eyes, thus avoiding waste of human resources. There is no need to judge whether the display is normal through machine vision, thus avoiding image processing, thus reducing technical difficulty and user costs.

[0073] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0074] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0075] Figure 1 It is a schematic structural diagram of an exemplary implementation of a display module.

[0076] Figure 2 It is a schematic diagram of the structure of the monitoring circuit and display module disclosed in the present invention.

[0077] Figure 3 The figure is a schematic diagram of the connection structure of an exemplary embodiment of the monitoring circuit and the display circuit disclosed in the present invention.

[0078] Figure 4 It is a structural diagram of an exemplary implementation of a signal processing circuit and a processor in the monitoring circuit of the present disclosure.

[0079] Figure 5for Figure 4 Schematic diagram of the circuit structure of the first signal processing circuit, the second signal processing circuit and the sixth signal processing circuit.

[0080] Figure 6 for Figure 4 Schematic diagram of the circuit structure of the third signal processing circuit and the fourth signal processing circuit.

[0081] Figure 7 for Figure 4 Schematic diagram of the circuit structure of two fifth signal processing circuits.

[0082] Figure 8 FIG. 1 is a schematic diagram of a connection structure of another exemplary embodiment of a monitoring circuit and a display circuit disclosed in the present invention.

[0083] Fig. 9 It is a structural diagram of another exemplary implementation of a signal processing circuit and a processor in the monitoring circuit of the present disclosure.

[0084] Fig.10 It is a flow chart of the monitoring method of the display module disclosed in the present invention.

[0085] Description of reference numerals:

[0086] 1. Display circuit; PMIC1, first power manager; TCON, first controller; LSIC, level converter; BLU-Con, backlight converter; LED-D, backlight driver controller;

[0087] 2. signal processing circuit; 21. first signal processing circuit; 211. first emitter follower unit; 22. second signal processing circuit; 221. second emitter follower unit; 222. second voltage divider unit; 23. third signal processing circuit; 231. third emitter follower unit; 232. third voltage divider unit; 24. fourth signal processing circuit; 241. fourth emitter follower unit; 242. fourth voltage divider unit; 25. fifth signal processing circuit; 251. fifth emitter follower unit; 252. fifth voltage divider unit; 26. sixth signal processing circuit; 261. sixth emitter follower unit; 27. seventh signal processing circuit; 271. seventh emitter follower unit; 272. seventh voltage divider unit;

[0088] MCU, processor; ADC1, first analog-to-digital conversion unit; ADC2, second analog-to-digital conversion unit; ADC3, third analog-to-digital conversion unit; Timer1, first timing unit; Timer2, second timing unit; Timer3, third timing unit; CPU, second controller; GPIO1, first input port; GPIO2, second input port;

[0089] PMIC2, second power manager;

[0090] 3. Display panel; 31. Backlight module; 32. Array substrate; 33. Liquid crystal layer; 34. Color film substrate; 351. First printed circuit board; 352. Second printed circuit board. DETAILED DESCRIPTION

[0091] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0092] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0093] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0094] In this application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. "And / or" is just a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the previous and next associated objects are in an "or" relationship.

[0095] The inventors found through experiments and investigations that the main reason for the display module failure is that the first power manager PMIC1, the logic board and the chip-on-film binding are directly related. Among them, the first power manager PMIC1 and the logic board account for a relatively high proportion, and the main display failures include black screen abnormalities related to the input signal or reception of the logic board, black screen abnormalities related to the voltage abnormality of the first power manager PMIC1, and screen abnormalities related to the gate driver circuit (GOA: Gate Driver On Array).

[0096] The exemplary embodiment of the present disclosure provides a monitoring circuit of a display module, referring to Figure 1-Figure 9 As shown, the display module may include a display panel 3 and a display circuit 1, and the display circuit 1 may include a main controller, a first controller TCON, a first power manager PMIC1 and a level converter LSIC, the input end of the first controller TCON is electrically connected to the output end of the first power manager PMIC1 and the output end of the main controller, the output end of the first controller TCON is electrically connected to the input end of the level converter LSIC, the first controller TCON is configured to output the display signal required by the display panel 3 through the level converter LSIC according to the instruction of the main controller, and the first power manager PMIC1 is configured to provide a voltage signal to the first controller TCON; the monitoring circuit may include a second controller CPU, the input end of the second controller CPU is electrically connected to the output end of the first power manager PMIC1, and is electrically connected to the output end of the first controller TCON through the level converter LSIC, the second controller CPU is configured to monitor the display state of the display panel 3 according to the display signal and / or the voltage signal, wherein the output end of the level converter LSIC is electrically connected to the input end of the display panel 3 and the input end of the second controller CPU.

[0097] The monitoring circuit of the display module disclosed in the present invention, the second controller CPU monitors the display status of the display panel 3 according to the display signal and / or the voltage signal. There is no need to observe whether the display module displays normally through human eyes, thus avoiding waste of human resources. There is no need to judge whether the display is normal through machine vision, thus avoiding image processing, reducing technical difficulty and user cost. Moreover, the judgment result is output, so that the user can directly know the abnormal type of the abnormal display, which is convenient for subsequent maintenance.

[0098] In this example implementation, refer to Figure 1 As shown, the display panel 3 may be a liquid crystal display panel 3, and the display panel 3 may include an array substrate 32, a color filter substrate 34, and a liquid crystal layer 33 disposed between the array substrate 32 and the color filter substrate 34. The display module may also include a backlight module 31.

[0099] The backlight module 31 may include a plurality of backlight sources arranged in a row, and the backlight source may be an LED (Light-Emitting Diode). The backlight module 31 may be set to only one partition, that is, the plurality of backlight sources of the backlight module 31 are uniformly controlled, and the voltages input to the plurality of backlight sources are substantially the same, so that the luminous brightness of the plurality of backlight sources of the backlight module 31 is substantially the same.

[0100] For the backlight module 31 of Local Dimming, the backlight source can be adjusted according to the brightness of the image, so that the brightness of the highlighted part of the displayed image can reach the maximum, while the dark part can reduce the brightness or even turn off to achieve the best contrast. In this way, the reduction of the brightness of the dark area reduces the power consumption of the backlight. Therefore, the backlight module 31 can also be set to two partitions, three partitions or more partitions, and multiple backlight sources in the same partition are uniformly controlled, that is, the voltages input to the multiple backlight sources in the same partition are basically the same, so that the luminous brightness of the multiple backlight sources in the same partition is basically the same.

[0101] The display panel 3 has a display area and a non-display area surrounding the display area. In the display area, the array substrate 32 may include a plurality of pixel circuits arranged in a row, and the pixel circuit may include a transistor and a pixel electrode. The transistor may include a gate, a source, and a drain. The gate of the transistor is connected to the corresponding gate line, the source of the transistor is connected to the corresponding data line, and the drain of the transistor is connected to the pixel electrode. A common electrode is also provided in the display area, and the common electrode may be located on the array substrate 32 or on the color filter substrate 34.

[0102] The signal loaded by the gate line controls the transistor to conduct, so as to write the data voltage provided by the data line to the corresponding pixel electrode. An electric field can be formed between the pixel electrode and the common electrode to drive the liquid crystal molecules in the corresponding area to deflect, thereby realizing grayscale control. In order to realize the precise control of the grayscale displayed by the sub-pixel, the data voltage provided by the data line needs to be accurately written to the pixel electrode of the sub-pixel.

[0103] A gate driver circuit (GOA: Gate Driver On Array) is provided in the non-display area of ​​the array substrate 32. The gate driver circuit may include a plurality of cascaded shift registers. The signal output end of each level of the shift register is connected to the corresponding gate line to provide a display signal to the corresponding gate line. The display signal provided by the gate driver circuit controls the gate switching of transistors in different rows. The data signal provided by the source driver chip (Source Driver IC) is sent to the source of transistors in different columns. When the scan line signal turns on the transistor, the signal line charges the liquid crystal and the storage capacitor from the source to save the data; when the scan line signal turns off the transistor, the high impedance ROFF cuts off the loop to prevent the data from being changed.

[0104] Reference Figure 2 As shown, the display module can be a 1920x360 rail transit strip screen, and the display module can also include a first printed circuit board 351, on which a part of the display circuit 1 is arranged. The display circuit 1 can include a backlight driving circuit, a main controller, a first controller TCON (Timing controller, Tcon), a first power manager PMIC1 (Power Management IC, PMIC), a level converter LSIC (Leve Shifter IC), capacitors, resistors, etc. The main controller can be a SoC (System on Chip) motherboard, and the first power manager PMIC1 supplies power to other components of the display circuit 1. The first printed circuit board 351 can be a logic board, on which the first printed circuit board 351 is arranged a first power manager PMIC1, a first controller TCON, and a level converter LSIC, etc.

[0105] The first printed circuit board 351 can be connected to the left X-printed circuit board assembly XPCBA-L (X-printed circuit board assembly, XPCBA) and the right X-printed circuit board assembly XPCBA-R through two flexible circuit boards FPCB. The left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R are then coupled to the conductive connection terminals located in the binding area on the array substrate 32 through two flip film COFs (a total of four flip film COFs). The input end of the first printed circuit board 351 is electrically connected to the SoC mainboard. Specifically, the input end of the first controller TCON is electrically connected to the output end of the first power manager PMIC1 and the output end of the main controller. The first controller TCON is configured to output the display signal required by the display panel 3 through the level converter LSIC according to the instruction of the main controller; the output end of the first printed circuit board 351 is connected to the source driver chip SDIC (Source Driver IC, SDIC) and the gate driver circuit to realize the signal input to the pixel circuit. The source driver chip SDIC can be set on the flip film COF, and a total of four source driver chips SDIC are set. The display module may also have other structures, which are not described here one by one.

[0106] Reference Figure 2 As shown, the display circuit may also include a backlight driving circuit. Specifically, the display module may also include a second printed circuit board 352. The second printed circuit board 352 may be a cross-flow board. A backlight driving circuit is provided on the second printed circuit board 352. The backlight driving circuit is configured to provide a backlight signal to the backlight module 31. The output end of the backlight driving circuit is electrically connected to the second controller CPU and the input end of the backlight module 31. The backlight driving circuit may include a backlight converter BLU-Con (Back Light Unit Converter). The second printed circuit board 352 may be electrically connected to the first printed circuit board 351 through a wire, so that the backlight driving circuit on the second printed circuit board 352 may be electrically connected to the monitoring circuit. Moreover, the backlight driving circuit is electrically connected to the backlight module 31, and the control of the backlight module 31 is realized through the backlight driving circuit. For example, the backlight driving circuit may be electrically connected to the backlight module 31 through the first printed circuit board 351.

[0107] At least part of the monitoring circuit and at least part of the display circuit 1 are arranged on the same circuit board, referring to Figure 2As shown, in this example implementation, the monitoring circuit is also arranged on the first printed circuit board 351. Specifically, the signal processing circuit 2, the processor MCU and the second power manager PMIC2 are all arranged on the first printed circuit board 351, that is, the signal processing circuit 2, the processor MCU and the second power manager PMIC2 are arranged on the same first printed circuit board 351 as the first power manager PMIC1, the first controller TCON and the level converter LSIC. Of course, in some other example implementations of the present disclosure, the signal processing circuit 2, the processor MCU and the second power manager PMIC2 can also be arranged separately on another monitoring printed circuit board, and the monitoring printed circuit board and the first printed circuit board 351 can be electrically connected by binding, or by a chip-on-film or a flexible circuit board.

[0108] Reference Figure 3 As shown, the first controller TCON converts the video signal transmitted from the main controller (SOC motherboard) into the data signal format required by the data driving circuit, for example, converting LVDS (Low Voltage Differential Signaling) into RSDS (Reduced Swing Differential Signaling), or into Mini-LVDS (Mini Low Voltage Differential Signaling), and then connects to the array substrate through the micro-low voltage differential signal connector (Mini-LVDS Connector) of the left X-printed circuit board assembly XPCBA-L and the right X-printed circuit board assembly XPCBA-R for display module data driving, and also provides display signals for the gate and source.

[0109] The main controller (SOC mainboard) provides a 12V power supply voltage (VDD) to the first power manager PMIC1 and the second power manager PMIC2. In addition, the processor MCU can output the judgment result to the main controller (SOC mainboard).

[0110] In this example embodiment, the monitoring circuit may also include a signal processing circuit 2, which is electrically connected between the display circuit 1 of the display module and the processor MCU. The signal processing circuit 2 is configured to process a working signal. The signal processing circuit 2 may include an emitter follower unit and a voltage divider unit. The emitter follower unit is electrically connected to the output end of the display circuit, and the voltage divider unit is electrically connected to the output end of the emitter follower unit. The emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current. The voltage divider unit is configured to adjust the voltage of the working signal; the working signal includes at least any one of a voltage signal, a display signal, and a backlight signal; so that the signal processing circuit 2 is used to collect any one of the voltage signal, the display signal, and the backlight signal of the display circuit 1.

[0111] The working signal includes at least any one of the DC digital voltage signal DVDD and the DC analog voltage signal AVDD in the voltage signal, the frame start signal STV1, the reset signal STV2 and the clock signal CLK in the display signal, and the cathode voltage signal LED- in the backlight signal.

[0112] In this example implementation, the voltage signal may include a DC analog voltage signal and a DC digital voltage signal. For example, in general, the voltage signal may be a DC voltage signal, and the voltage signal may include a DC analog voltage signal AVDD, a DC digital voltage signal DVDD, a gate drive high level VGH, a gate drive low level VGL, an analog operating half voltage HAVDD, a reference voltage VCOM, a correction voltage Gamma, etc. If all voltage signals are detected, seven signal processing circuits need to be set, and the processor MCU also needs to select a chip with more interfaces, which will lead to a significant increase in hardware costs, and the occupied area of ​​the first printed circuit board 351 will also increase significantly. Since the DC analog voltage signal AVDD and the DC digital voltage signal DVDD are the basic voltages for generating the gate drive high level VGH, the gate drive low level VGL, the analog working half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, that is, the DC analog voltage signal AVDD and the DC digital voltage signal DVDD are the sources of other voltages, if the DC analog voltage signal AVDD and the DC digital voltage signal DVDD are abnormal, then the other voltages must be abnormal, and if the DC analog voltage signal AVDD and the DC digital voltage signal DVDD are normal, then the other voltages are also normal without special circumstances. Therefore, monitoring the DC analog voltage signal AVDD and the DC digital voltage signal DVDD can realize the monitoring of the first power manager PMIC1 of the display module, and the processor MCU does not need to select a chip with more interfaces, the hardware cost will not increase significantly, and the occupied area of ​​the first printed circuit board 351 will not increase much.

[0113] Of course, in some other example embodiments of the present disclosure, for example, when the monitoring requirements are high, the voltage signal may include not only the DC analog voltage signal AVDD and the DC digital voltage signal DVDD, but also may include one, two or more of the gate drive high level VGH, the gate drive low level VGL, the analog operating half voltage HAVDD, the reference voltage VCOM, and the correction voltage Gamma, which are not explained one by one here.

[0114] In this case, refer to Figure 3 As shown, since the connection lines in the figure are crossed, the ones with black dots at the crossing positions are cross-connected, and the ones without black dots at the crossing positions are only crossed without connection. The signal processing circuit 2 is electrically connected to the output end of the first power manager PMIC1, and is used to collect the DC analog voltage signal AVDD. The signal processing circuit 2 is also electrically connected to the output end of the first power manager PMIC1, and is used to collect the DC digital voltage signal DVDD.

[0115] Specifically, refer to Figure 4 As shown, the signal processing circuit 2 may include a first signal processing circuit 21 and a second signal processing circuit 22. The first signal processing circuit 21 is configured to process a DC digital voltage signal DVDD in the voltage signal. The second signal processing circuit 22 is configured to process a DC analog voltage signal AVDD in the voltage signal.

[0116] The first signal processing circuit 21 may include a first emitter follower unit 211, which is electrically connected to the output terminal of the first power manager PMIC1. The first emitter follower unit 211 is used to collect the DC digital voltage signal DVDD output by the first power manager PMIC1, that is, the first emitter follower unit 211 is configured to collect the DC digital voltage signal DVDD and prevent the DC digital voltage signal DVDD from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0 to 3.3V, and the DC digital voltage signal DVDD is approximately 3.3V, the DC digital voltage signal DVDD can be directly connected to the processor MCU, that is, the output terminal of the first signal processing circuit 21 is directly electrically connected to the input terminal of the processor MCU.

[0117] The second signal processing circuit 22 may include a second emitter follower unit 221 and a second voltage divider unit 222. The second emitter follower unit 221 is electrically connected to the output end of the first power manager PMIC1. The second emitter follower unit 221 is used to collect the DC analog voltage signal AVDD, that is, the second emitter follower unit 221 is configured to collect the DC analog voltage signal AVDD in the voltage signal and prevent the DC analog voltage signal AVDD from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0 to 3.3V, and the DC analog voltage signal AVDD is approximately 16V, the DC analog voltage signal AVDD cannot be directly connected to the processor MCU, and needs to be divided by the second voltage divider unit 222 before being connected to the processor MCU; therefore, the second voltage divider unit 222 is set to be electrically connected to the output end of the second emitter follower unit 221, and the second voltage divider unit 222 is used to adjust the voltage value of the DC analog voltage signal AVDD to within the first required range, that is, the second voltage divider unit 222 is configured to adjust the voltage value of the DC analog voltage signal AVDD to a fixed voltage.

[0118] It should be noted that the second voltage divider unit 222 can adjust the DC analog voltage signal AVDD in proportion, generally the maximum value is less than 3.3V, and the adjusted value is a fixed voltage when the voltage value of the DC analog voltage signal AVDD is a certain value. Of course, the voltage value of the DC analog voltage signal AVDD is different, and the adjusted voltage value will also change. In the present disclosure, the fixed voltage is a voltage that the processor MCU can accept, for example, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V.

[0119] In this example implementation, the display signal may include a frame start signal STV1, a reset signal STV2, and a plurality of clock signals CLK. Since the gate drive circuit is disposed in the array substrate 32, if the output signal is led from the output end of the gate drive circuit to the first printed circuit board 351 for detection, it will increase the difficulty of setting up the display panel 3 and the manufacturing cost, and the output signal of the gate drive circuit is generated by the input control signal, and the input control signal of the gate drive circuit is generated on the first printed circuit board 351. Therefore, the input control signal of the gate drive circuit can be monitored, that is, the frame start signal STV1, the reset signal STV2, and the plurality of clock signals CLK1-6 of the gate drive circuit can be monitored. The frame start signal STV1 and the reset signal STV2 are fixed frequency pulse signals, and the clock signals CLK1-6 are fixed frequency square wave signals. By monitoring whether their frequencies are normal, the display signal of the display module can be monitored, and then the display state of the display panel 3 can be monitored.

[0120] Of course, in some other exemplary embodiments of the present disclosure, the output signal of the gate driving circuit may also be detected.

[0121] In this case, refer to Figure 3 As shown, the first controller TCON generates a frame start signal STV1, a reset signal STV2 and a plurality of clock signals CLK1-6 and transmits them to the level converter LSIC, and then inputs them to the gate driving circuit through the level converter LSIC. Figure 4 As shown, the signal processing circuit 2 is electrically connected to the output end of the level converter LSIC, and is used to collect the frame start signal STV1, the reset signal STV2 and multiple clock signals CLK1~6; so that the second controller CPU is electrically connected to the first controller TCON through the level converter LSIC to receive the electrical signals (frame start signal STV1, reset signal STV2 and multiple clock signals CLK1~6) of the first controller TCON.

[0122] Specifically, the signal processing circuit 2 may include a third signal processing circuit 23, a fourth signal processing circuit 24, and a plurality of fifth signal processing circuits 25. The third signal processing circuit 23 is configured to process a frame start signal STV1 in the display signal, the fourth signal processing circuit 24 is configured to process a reset signal STV2 in the display signal, and the fifth signal processing circuit 25 is configured to process a clock signal CLK in the display signal.

[0123] The third signal processing circuit 23 may include a third emitter follower unit 231 and a third voltage divider unit 232. The third emitter follower unit 231 is electrically connected to the output end of the level converter LSIC. The third emitter follower unit 231 is used to collect the frame start signal STV1, that is, the third emitter follower unit 231 is configured to collect the frame start signal STV1 in the display signal and prevent the frame start signal STV1 from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0 to 3.3V, although the frame start signal STV1 is a fixed frequency pulse signal, it is also realized by voltage jump. Therefore, when the high level of the frame start signal STV1 is high, it cannot be directly connected to the processor MCU, and needs to be divided by the third voltage divider unit 232 before being connected to the processor MCU; therefore, the third voltage divider unit 232 is set to be electrically connected to the output end of the third emitter follower unit 231, and the third voltage divider unit 232 is used to adjust the voltage value of the frame start signal STV1 to within the second required range, that is, the third voltage divider unit 232 is configured to adjust the voltage value of the frame start signal to a fixed voltage. Furthermore, when the third voltage dividing unit 232 adjusts the voltage value of the frame start signal STV1 , the frequency of the frame start signal STV1 is not affected.

[0124] It should be noted that the third voltage divider unit 232 can adjust the voltage value of the frame start signal STV1 proportionally, and generally the maximum value can be less than 3.3V. When the voltage value of the frame start signal STV1 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the frame start signal STV1 is different, and the adjusted voltage value will also change.

[0125] The fourth signal processing circuit 24 may include a fourth emitter follower unit 241 and a fourth voltage divider unit 242. The fourth emitter follower unit 241 is electrically connected to the output end of the level converter LSIC. The fourth emitter follower unit 241 is used to collect the reset signal STV2, that is, the fourth emitter follower unit 241 is configured to collect the reset signal STV2 in the display signal and prevent the reset signal STV2 from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0 to 3.3V, although the reset signal STV2 is a fixed frequency pulse signal, it is also realized by voltage jump. Therefore, when the high level of the reset signal STV2 is high, it cannot be directly connected to the processor MCU, and needs to be divided by the fourth voltage divider unit 242 before being connected to the processor MCU; therefore, the fourth voltage divider unit 242 is set to be electrically connected to the output end of the fourth emitter follower unit 241, and the fourth voltage divider unit 242 is used to adjust the voltage value of the reset signal STV2 to within the third required range, that is, the fourth voltage divider unit 242 is configured to adjust the voltage value of the reset signal STV2 to a fixed voltage. Moreover, during the process of adjusting the voltage value of the reset signal STV2 by the fourth voltage dividing unit 242 , the frequency of the reset signal STV2 will not be affected.

[0126] It should be noted that the fourth voltage divider unit 242 can adjust the voltage value of the reset signal STV2 proportionally, and generally the maximum value can be less than 3.3V. When the voltage value of the reset signal STV2 is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the reset signal STV2 is different, and the adjusted voltage value will also change.

[0127] The fifth signal processing circuit 25 includes a fifth emitter follower unit 251 and a fifth voltage divider unit 252. The fifth emitter follower unit 251 is electrically connected to the output end of the level converter LSIC. The fifth emitter follower unit 251 is used to collect the clock signal CLK, that is, the fifth emitter follower unit 251 is configured to collect the clock signal CLK in the display signal and prevent the clock signal CLK from flowing back to the display circuit 1. Since the processor MCU can only withstand a voltage of 0 to 3.3V, and the clock signal CLK is approximately -4V to 32V, the clock signal CLK cannot be directly connected to the processor MCU, and needs to be divided by the fifth voltage divider unit 252 before being connected to the processor MCU; therefore, the fifth voltage divider unit 252 is set to be electrically connected to the output end of the fifth emitter follower unit 251, and the fifth voltage divider unit 252 is used to adjust the voltage value of the clock signal CLK to within the fourth required range, that is, the fifth voltage divider unit 252 is configured to adjust the voltage value of the clock signal CLK to a fixed voltage. Furthermore, during the process of adjusting the voltage value of the clock signal CLK by the fifth voltage dividing unit 252 , the frequency of the clock signal CLK will not be affected.

[0128] It should be noted that the fifth voltage divider unit 252 can adjust the voltage value of the clock signal CLK proportionally, generally the minimum value is greater than 0V and the maximum value is less than 3.3V; when the voltage value of the clock signal CLK is a certain value, the adjusted value is a fixed voltage. Of course, the voltage value of the clock signal CLK is different, and the adjusted voltage value will also change.

[0129] The number of fifth signal processing circuits 25 can be set according to the number of clock signals CLK. The number of fifth signal processing circuits 25 is equal to the number of clock signals CLK. One fifth signal processing circuit 25 collects one clock signal CLK. For example, when six clock signals CLK are set, six fifth signal processing circuits 25 can be set; when ten clock signals CLK are set, ten fifth signal processing circuits 25 can be set. Figure 4 Only two fifth signal processing circuits 25 are shown, and the middle part is replaced by an ellipsis.

[0130] In this example embodiment, the backlight signal may include cathode voltage signals LED- of each partition of the backlight module 31. Since the cathode voltage signals LED- in the same partition are the same, for example, when the backlight module 31 is set to only one partition, the backlight signal may be one cathode voltage signal LED-. When the backlight module 31 is set to only two partitions, the backlight signal may be two cathode voltage signals LED-. Similarly, when the backlight module 31 is set to three or more partitions, the backlight signal may be three or more cathode voltage signals LED-.

[0131] In this case, the signal processing circuit 2 is electrically connected to the backlight driving circuit of the backlight module 31, and is used to collect the cathode voltage signal LED- of each partition.

[0132] Specifically, refer to Figure 4 As shown, the signal processing circuit 2 may include a sixth signal processing circuit 26, and the sixth signal processing circuit 26 is configured to process the cathode voltage signal LED- in the backlight signal.

[0133] The sixth signal processing circuit 26 may include a sixth emitter follower unit 261, which is electrically connected to the backlight driving circuit of the backlight module 31. Specifically, the sixth emitter follower unit 261 is electrically connected to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is used to collect the cathode voltage signal LED- of each partition of the backlight module 31, that is, the sixth emitter follower unit 261 is configured to collect the cathode voltage signal LED- in the backlight signal and prevent the cathode voltage signal LED- from flowing back to the display circuit 1. Since the cathode voltage signal LED- is usually less than 1V, the cathode voltage signal can be directly connected to the processor MCU, that is, the output end of the sixth signal processing circuit 26 is directly electrically connected to the input end of the processor MCU.

[0134] The number of the sixth signal processing circuits 26 can be set according to the number of cathode voltage signals, that is, the number of the sixth signal processing circuits 26 can be equal to the number of partitions of the backlight module 31. For example, when the backlight module 31 is provided with two partitions, two sixth signal processing circuits 26 need to be provided to collect cathode voltage signals of the two partitions in a one-to-one correspondence; when the backlight module 31 is provided with three or more partitions, three or more sixth signal processing circuits 26 need to be provided to collect cathode voltage signals of the three or more partitions in a one-to-one correspondence.

[0135] The monitoring circuit may further include a first analog-to-digital conversion unit ADC1, a second analog-to-digital conversion unit ADC2, a third analog-to-digital conversion unit ADC3, a first timing unit Timer1, a second timing unit Timer2, a second controller CPU, and a plurality of third timing units Timer3. Figure 4As shown, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the second controller CPU, and the plurality of third timing units Timer3 may be included in the processor MCU. Of course, in some other example implementations of the present disclosure, the first analog-to-digital conversion unit ADC1, the second analog-to-digital conversion unit ADC2, the third analog-to-digital conversion unit ADC3, the first timing unit Timer1, the second timing unit Timer2, the second controller CPU, and the plurality of third timing units Timer3 may also be separately set as a component; and one, two, or more of them may be selected according to different signals to be monitored.

[0136] The first analog-to-digital conversion unit ADC1 is electrically connected to the output end of the first emitter follower unit 211; the first analog-to-digital conversion unit ADC1 is used to convert the DC digital voltage signal DVDD into a digital signal. The second controller CPU is electrically connected to the output end of the first analog-to-digital conversion unit ADC1, and the second controller CPU is configured to output that the display state of the display panel is a first abnormal display state, in which the DC digital voltage signal DVDD has a first set value; that is, the second controller CPU is configured to determine whether the voltage of the DC digital voltage signal DVDD meets the first set value, and if so, determine that the display state of the display panel 3 is the first abnormal display state.

[0137] The first set value is less than 3.0V or greater than 3.6V.

[0138] The second analog-to-digital conversion unit ADC2 is electrically connected to the output end of the second voltage divider unit 222; the second analog-to-digital conversion unit ADC2 is used to convert the DC analog voltage signal AVDD into a digital signal. The second controller CPU is electrically connected to the output end of the second analog-to-digital conversion unit ADC2, and the second controller CPU is configured to output the display state of the display panel as the second abnormal display state. In the second abnormal display state, the DC analog voltage signal AVDD has a second set value; that is, the second controller CPU is configured to determine whether the voltage of the DC analog voltage signal AVDD meets the second set value, and if so, it is determined that the display state of the display panel 3 is the second abnormal display state. The second set value is less than 15V or greater than 17V.

[0139] The third analog-to-digital conversion unit ADC3 is electrically connected to the output end of the sixth emitter follower unit 261; the third analog-to-digital conversion unit ADC3 is used to convert the cathode voltage signal LED- into a digital signal. The second controller CPU is electrically connected to the output end of the third analog-to-digital conversion unit ADC3, and the second controller CPU is configured to output that the display state of the display panel is the sixth abnormal display state. In the sixth abnormal display state, the cathode voltage signal LED- has a sixth preset value, that is, the second controller CPU is configured to determine whether the cathode voltage signal LED- meets the sixth preset value, and if so, it is determined that the display state of the display panel 3 is the sixth abnormal display state. The sixth preset value is less than 0.25V or greater than 0.5V.

[0140] The first timing unit Timer1 is electrically connected to the output end of the third voltage divider unit 232; the first timing unit Timer1 is used to identify the frequency of the frame start signal STV1. The second controller CPU is electrically connected to the output end of the first timing unit Timer1, and the second controller CPU is configured to output that the display state of the display panel is a third abnormal display state, in which the frequency of the frame start signal STV1 has a third set value; that is, the second controller CPU is configured to determine whether the frequency of the frame start signal STV1 meets the third set value, and if so, the display state of the display panel 3 is determined to be the third abnormal display state. The third set value is less than 58Hz or greater than 62Hz.

[0141] The second timing unit Timer2 is electrically connected to the output end of the fourth voltage divider unit 242; the second timing unit Timer2 is used to identify the frequency of the reset signal STV2. The second controller CPU is electrically connected to the output end of the second timing unit Timer2, and the second controller CPU is configured to output that the display state of the display panel is the fourth abnormal display state, and in the fourth abnormal display state, the frequency of the reset signal STV2 has a fourth set value; that is, the second controller CPU is configured to determine whether the frequency of the reset signal STV2 meets the fourth set value, and if so, it is determined that the display state of the display panel 3 is the fourth abnormal display state. The fourth set value is less than 56Hz or greater than 60Hz, or the fourth set value is less than 1.5kHz or greater than 1.9kHz.

[0142] A plurality of third timing units Timer3 are electrically connected to the output ends of a plurality of fifth voltage-dividing units 252 in a one-to-one correspondence; the third timing unit Timer3 is used to identify the frequency of the clock signal CLK. The second controller CPU is electrically connected to the output ends of the plurality of third timing units Timer3, and the second controller CPU is configured to output that the display state of the display panel is the fifth abnormal display state, in which the frequency of the clock signal CLK has a fifth set value; that is, the second controller CPU is configured to determine whether the frequency of the clock signal CLK satisfies the fifth set value, and if not, the display state of the display panel 3 is determined to be the fifth abnormal display state. The fifth set value is less than 22.5kHz or greater than 22.9kHz.

[0143] The second controller CPU is configured to determine whether the voltage signal, display signal and backlight signal in the working signal are all normal. If so, it is determined that the display state of the display panel 3 is a normal display state; otherwise, the display state of the display panel 3 is an abnormal display state, and the abnormal display state may include multiple types, which have been illustrated above.

[0144] Moreover, the second controller CPU is configured to determine whether all the working signals meet the following conditions. If so, it is determined that the display state of the display panel 3 is a normal display state: the DC digital voltage signal DVDD value is greater than or equal to 3.0V and less than or equal to 3.6V; the DC analog voltage signal AVDD is greater than or equal to 15V and less than or equal to 17V; the frame start signal STV1 is greater than or equal to 58Hz and less than or equal to 62Hz; the reset signal STV2 is greater than or equal to 56Hz and less than or equal to 60Hz, or, the reset signal STV2 is greater than or equal to 1.5kHz and less than or equal to 1.9kHz; the clock signal CLK is greater than or equal to 22.5kHz and less than or equal to 22.9kHz; the cathode voltage signal LED- is greater than or equal to 0.25V and less than or equal to 0.5V.

[0145] The specific judgment process of the second controller CPU is described in the monitoring method and will not be repeated here.

[0146] The emitter follower unit (the first emitter follower unit 211, the second emitter follower unit 221, the third emitter follower unit 231, the fourth emitter follower unit 241, the fifth emitter follower unit 251 and the sixth emitter follower unit 261) has an isolation function, that is, preventing the signal from flowing back to the display circuit 1, ensuring that the signal does not affect the normal operation of the original display circuit 1 after being connected to the monitoring circuit, and utilizing the high input impedance characteristics of the emitter follower unit to isolate the two circuits; in addition, the output voltage of the emitter follower unit is equal to its input voltage, so that signal parameter acquisition can be accurately realized.

[0147] Of course, in some other exemplary embodiments of the present disclosure, the signal processing circuit 2 may not be provided, so that the processor MCU is directly electrically connected to the display circuit 1 .

[0148] Reference Figure 5 As shown, the first emitter follower unit 211, the second emitter follower unit 221 and the sixth emitter follower unit 261 can be arranged on a first chip IC1. VOUTA, VINA- and VINA+ are three pins of the second emitter follower unit 221, which are used to collect the DC analog voltage signal AVDD. VOUTB, VINB- and VINB+ are three pins of the first emitter follower unit 211, which are used to collect the DC digital voltage signal DVDD. VOUTC, VINC- and VINC+ are three pins of the first six emitter follower units 261, which are used to collect the cathode voltage signal LED1- of the first partition. VOUTD, VIND- and VIND+ are three pins of the second six emitter follower units 261, which are used to collect the cathode voltage signal LED2- of the second partition. Moreover, a 0 ohm resistor 0R0 is connected to these input terminals, and these signals can be isolated from the display circuit 1 through the 0 ohm resistor 0R0 to prevent these signals from affecting the normal operation of the original display circuit 1.

[0149] Among them, AVDD, DVDD, LED1- and LED2- are signals input to the first chip IC1, AVDD_M, DVDD_M, LED1_M and LED2_M are signals output by the first chip IC1, and, Figure 5 The arrows in the middle also represent input and output. Similarly, a 0 ohm resistor 0R0 is also set at the output end of these signals (except AVDD_M), and the 0 ohm resistor 0R0 can be used to isolate the signals from each other to prevent the latter signal from affecting the former signal.

[0150] The DC analog voltage signal AVDD needs to be divided. The first resistor R1 and the second resistor R2 form a second voltage dividing unit 222 to divide the DC analog voltage signal AVDD.

[0151] Furthermore, a first clamping diode D1 is connected to the connection end of AVDD_M, and the size of AVDD_M is limited by the first clamping diode D1. A second clamping diode D2 is connected to the connection end of DVDD_M, and the size of DVDD_M is limited by the second clamping diode D2.

[0152] VSS+ and VSS- are the positive and negative power supply terminals of the first chip IC1, and the AVDD-OP output by the second power manager PMIC2 is input into the first chip IC1 through VSS+. Moreover, VSS+ is grounded through capacitor C, and AVDD-OP can be filtered through capacitor C to ensure the stability of AVDD-OP.

[0153] Reference Figure 6 As shown, the third emitter follower unit 231 and the fourth emitter follower unit 241 can be arranged on a second chip IC2. OUTA, INA- and INA+ are three pins of the third emitter follower unit 231, which are used to collect the frame start signal STV1. OUTB, INB- and INB+ are three pins of the fourth emitter follower unit 241, which are used to collect the reset signal STV2. Moreover, a 0 ohm resistor 0R0 is connected to each of these input terminals, and these signals can be isolated from the display circuit 1 through the 0 ohm resistor 0R0 to prevent these signals from affecting the normal operation of the original display circuit 1.

[0154] Among them, STV1 and STV2 are signals input to the second chip IC2, STV1_M and STV2_M are signals output by the second chip IC2, and, Figure 6 The arrows in the middle also represent input and output.

[0155] Both the frame start signal STV1 and the reset signal STV2 need to be divided, and both the frame start signal STV1 and the reset signal STV2 have negative voltage and positive voltage, and the negative voltage needs to be adjusted to a positive voltage. The third voltage divider unit 232 is formed by the third resistor R3 and the fourth resistor R4 to divide the frame start signal STV1, and the negative voltage of the frame start signal STV1 is adjusted to a positive voltage through the third clamping diode D3, the fifth resistor R5 and the sixth resistor R6. The fourth voltage divider unit 242 is formed by the seventh resistor R7 and the eighth resistor R8 to divide the reset signal STV2, and the negative voltage of the reset signal STV2 is adjusted to a positive voltage through the fourth clamping diode D4, the ninth resistor R9 and the tenth resistor R10.

[0156] VS+ and VS- are the positive and negative power supply terminals of the second chip IC2. The VGH_OP output by the second power manager PMIC2 is input to the second chip IC2 through VS+. The VGL_OP output by the second power manager PMIC2 is input to the second chip IC2 through VS-. Moreover, both VS+ and VS- are grounded through capacitor C, and capacitor C can filter VGH_OP and VGL_OP to ensure the stability of VGH_OP and VGL_OP.

[0157] Reference Figure 7As shown, two fifth emitter follower units 251 can be set on a third chip IC3. OUTA, INA- and INA+ are three pins of a fifth emitter follower unit 251, which are used to collect a clock signal CLK1. OUTB, INB- and INB+ are three pins of another fifth emitter follower unit 251, which are used to collect another clock signal CLK. Moreover, a 0 ohm resistor 0R0 is connected to each of these input terminals, and these signals can be isolated from the display circuit 1 through the 0 ohm resistor 0R0 to prevent these signals from affecting the normal operation of the original display circuit 1.

[0158] Among them, CLK1 and CLK2 are signals input to the third chip IC3, CLK1_M and CLK2_M are signals output by the third chip IC3, and, Figure 7 The arrows in the middle also represent input and output.

[0159] Both clock signals CLK1 and CLK2 need to be divided, and both clock signals CLK1 and CLK2 have negative voltage and positive voltage, and the negative voltage needs to be adjusted to a positive voltage. A fifth voltage-dividing unit 252 is formed by the eleventh resistor R11 and the twelfth resistor R12 to divide the voltage of a clock signal CLK1, and the negative voltage of a clock signal CLK1 is adjusted to a positive voltage through the fifth clamping diode D5, the thirteenth resistor R13 and the fourteenth resistor R14. Another fifth voltage-dividing unit 252 is formed by the fifteenth resistor R15 and the sixteenth resistor R16 to divide the voltage of another clock signal CLK2, and the negative voltage of another clock signal CLK2 is adjusted to a positive voltage through the sixth clamping diode D6, the seventeenth resistor R17 and the eighteenth resistor R18.

[0160] VS+ and VS- are the positive and negative power supply terminals of the third chip IC3, and the VGH_OP output by the second power manager PMIC2 is input to the third chip IC3 through VS+. The VGL_OP output by the second power manager PMIC2 is input to the third chip IC3 through VS-. Moreover, both VS+ and VS- are grounded through capacitor C, and capacitor C can filter VGH_OP and VGL_OP to ensure the stability of VGH_OP and VGL_OP.

[0161] The circuit connection structure of the fifth signal processing circuit 25 for collecting other clock signals CLK4-CLK6 can be connected with Figure 7 The circuit connection structure shown is the same, so it will not be repeated here.

[0162] In some other exemplary embodiments of the present disclosure, the number of clock signals CLK of the gate drive circuit of the ultra-large-size display module and the ultra-high-resolution display module is relatively large, for example, twelve clock signals CLK may be provided, and eighteen clock signals CLK may also be provided. If these clock signals CLK are directly monitored, the number of signal processing circuits used will increase, and the interface of the processor MCU will also need to increase, thereby increasing the hardware cost and increasing the area of ​​the first printed circuit board 351.

[0163] In this case, the specific conditions of the first signal processing circuit 21 and the second signal processing circuit 22 included in the voltage signal and the signal processing circuit 2 are the same as those in the above exemplary embodiment, and thus will not be described in detail here.

[0164] The details of the frame start signal STV1, the reset signal STV2 in the display signal and the third signal processing circuit 23 and the fourth signal processing circuit 24 included in the signal processing circuit 2 are the same as those in the above exemplary embodiments, and thus will not be described again.

[0165] The first controller TCON is configured to output the display signal or the first error identification signal LS-F required by the display panel 3 according to the working state of the level converter LSIC. When the level converter LSIC is in over-temperature protection (OTP) and over-current protection (OCP), the first error identification signal LS-F can be triggered, and the high level of normal operation changes to a low level. When the level converter LSIC is in over-temperature protection, it is easy for the level converter LSIC to burn out. When the gate drive circuit GOA has a signal short circuit, it is easy to trigger the level converter LSIC to have a poor over-current protection.

[0166] The second controller CPU is configured to determine the display state of the display panel by judging whether the first error identification signal LS-F is received. Specifically, if the first error identification signal LS-F is received, it is determined that the display panel 3 is in the seventh abnormal display state.

[0167] In this case, the signal processing circuit 2 is electrically connected to the output terminal of the level converter LSIC.

[0168] Specifically, refer to Figure 8 and Fig. 9As shown, the signal processing circuit 2 may include a seventh signal processing circuit 27, and the seventh signal processing circuit 27 is configured to process the first error identification signal LS-F. The seventh signal processing circuit 27 may include a seventh emitter follower unit 271 and a seventh voltage divider unit 272; the seventh emitter follower unit 271 is electrically connected to the output end of the level converter LSIC, and the seventh emitter follower unit 271 is configured to collect the first error identification signal LS-F and prevent the first error identification signal LS-F from flowing back to the display circuit; the seventh voltage divider unit 272 is electrically connected to the output end of the seventh emitter follower unit 271, and the seventh voltage divider unit 272 is configured to adjust the voltage value of the first error identification signal LS-F to a fixed voltage, that is, the seventh voltage divider unit 272 is configured to adjust the voltage value of the first error identification signal LS-F to a required range.

[0169] By monitoring a first error identification signal LS-F instead of monitoring a number of clock signals CLK, that is, no matter how many clock signals CLK are set, only one first error identification signal LS-F needs to be monitored, so that the number of signal processing circuits used is reduced, the number of interfaces of the processor MCU is also reduced, the hardware cost is reduced, and the area of ​​the first printed circuit board 351 can also be set smaller.

[0170] In this case, since the first error identification signal LS-F changes from a high level in normal operation to a low level, it is not necessary to accurately obtain the voltage of the first error identification signal LS-F, and it is not necessary to use a timing unit to accurately collect the frequency of the clock signal CLK. Therefore, the processor MCU may include a first input port GPIO1. The first input port GPIO1 is electrically connected to the output end of the seventh voltage divider unit 272.

[0171] The second controller CPU is electrically connected to the output end of the seventh voltage dividing unit 272, specifically, the second controller CPU is electrically connected to the first input port GPIO1; the second controller CPU determines the display state of the display panel 3 according to whether the first error identification signal LS-F is received, that is, the second controller CPU is configured to determine whether the first error identification signal LS-F is received, and if so, it is determined that the display state of the display panel 3 is an abnormal display caused by an abnormal level converter LSIC. The specific process is described in the monitoring method and will not be repeated here.

[0172] In some other example embodiments of the present disclosure, the backlight module 31 of the highlight display module has more partitions. For example, the number of partitions of the Local Dimming backlight module 31 is usually dozens of partitions. If the cathode voltage signal LED- of each partition is monitored, the number of signal processing circuits used will increase, and the interface of the processor MCU will also need to be increased, thereby increasing the hardware cost and increasing the area of ​​the first printed circuit board 351.

[0173] In this case, the specific conditions of the first signal processing circuit 21 and the second signal processing circuit 22 included in the voltage signal and the signal processing circuit 2 are the same as those in the above exemplary embodiment, and thus will not be described in detail here.

[0174] In this case, the display circuit may also include a backlight driver controller LED-D (LED Driver), the output end of the backlight driver controller LED-D is electrically connected to the input end of the second controller CPU and the input end of the backlight driver circuit, and the output end of the backlight driver controller LED-D is electrically connected to the backlight converter BLU-Con; the backlight driver controller LED-D is configured to output a second error identification signal LED-DF or a backlight signal according to the working status of the backlight driver controller LED-D.

[0175] The input end of the second controller CPU is electrically connected to the output end of the backlight drive controller LED-D, and is electrically connected to the output end of the first controller TCON through the level converter LSIC. The second controller CPU is configured to determine the display status of the display panel by judging whether the second error identification signal LED-DF is received.

[0176] The monitoring circuit also includes a signal processing circuit 2, which is electrically connected between the backlight driving controller LED-D and the second controller CPU and is used to process the second error identification signal LED-DF.

[0177] Specifically, refer to Figure 8 and Fig. 9 As shown, the signal processing circuit 2 may include a sixth signal processing circuit 26, and the sixth signal processing circuit 26 may include a sixth emitter follower unit 261, which is electrically connected to the output end of the backlight driving controller LED-D. Specifically, the sixth emitter follower unit 261 is electrically connected to the backlight converter BLU-Con of the backlight driving circuit of the backlight module 31. The sixth emitter follower unit 261 is used to collect the second error identification signal LED-DF.

[0178] When the backlight drive controller LED-D is in over-temperature protection (OTP) or the backlight source is open or short-circuited, the second error identification signal LED-DF can be triggered, and the second error identification signal LED-DF changes from a high level of normal operation to a low level.

[0179] By monitoring a second error identification signal LED-DF instead of monitoring multiple cathode voltage signals LED-, no matter how many partitions the backlight module 31 is set with and how many backlight drive controllers LED-D are used, the error signals of each backlight drive controller LED-D can be connected together to become a second error identification signal LED-DF. Therefore, only one second error identification signal LED-DF needs to be monitored, which reduces the number of signal processing circuits used, reduces the number of interfaces of the processor MCU, reduces hardware costs, and the area of ​​the first printed circuit board 351 can also be set smaller.

[0180] In this case, since the second error identification signal LED-DF changes from a high level in normal operation to a low level, it is not necessary to accurately obtain the voltage of the second error identification signal LED-DF, and it is not necessary to use an analog-to-digital conversion unit to accurately collect the voltage of the second error identification signal LED-DF. Therefore, the processor MCU may include a second input port GPIO2, and the second input port GPIO2 is electrically connected to the output end of the sixth emitter follower unit 261.

[0181] The second controller CPU is configured to determine the display state of the display panel 3 by determining whether the second error identification signal LED-DF is received; the second controller CPU is electrically connected to the second input port GPIO2, and the second controller CPU determines whether the backlight is normal or the backlight abnormality causes abnormal display according to whether the second error identification signal is received. The specific process is described in the monitoring method and will not be repeated here.

[0182] It should be noted that in the example implementation of monitoring the second error identification signal LED-DF, the clock signal CLK can be monitored; of course, in the example implementation of monitoring the first error identification signal LS-F, the cathode voltage signal LED- of each partition of the backlight module 31 can be monitored.

[0183] In addition, the output UART of the processor MCU can be connected to the SoC mainboard, and the monitoring results can be transmitted to the SoC mainboard, so that the SoC mainboard can know the display status in the first time, and achieve the technical effect of real-time automatic monitoring of the display status of the display module. Moreover, the SoC mainboard can also be connected to the control center, which can be a customer after-sales platform, a railway central control platform, etc. For example, the SoC mainboard can upload the monitoring results to the cloud platform and send the abnormal information to the after-sales personnel, so that the display can be repaired and replaced in the first time after the abnormality occurs to avoid adverse effects on consumers.

[0184] In some example embodiments of the present disclosure, reference is made to Figure 2 and Figure 3 As shown, the monitoring circuit may also include a second power manager PMIC2, which is electrically connected to the monitoring circuit and configured to supply power to the monitoring circuit; for example, the second power manager PMIC2 is electrically connected to the signal processing circuit 2 and the second controller CPU and configured to supply power to the signal processing circuit 2 and the second controller CPU; or, the second power manager PMIC2 is electrically connected to the signal processing circuit 2 and the processor MCU and is used to supply power to the signal processing circuit 2 and the processor MCU, so that the power supply of the signal processing circuit 2 and the processor MCU is not the same as that of the first controller TCON and the level converter LSIC, and in the event of an abnormality in the first power manager PMIC1, the normal operation of the signal processing circuit 2 and the processor MCU will not be affected.

[0185] A jumper cap is also provided on the first printed circuit board 351. The on-off of the electrical signal can be simulated by plugging and unplugging the jumper cap. The status of each simulated electrical signal can be monitored in real time by the processor MCU.

[0186] Based on the same inventive concept, an example embodiment of the present disclosure provides a monitoring circuit for a display module, wherein the display module may include a backlight module 31, a display panel 3 and a display circuit 1, wherein the display circuit 1 may include a main controller, a first controller TCON, a backlight drive controller LED-D and a level converter LSIC, wherein the input end of the first controller TCON is electrically connected to the output end of the main controller, the output end of the first controller TCON is electrically connected to the input end of the level converter LSIC, and the output end of the backlight drive controller LED-D is electrically connected to the input end of the backlight module 31; the first controller TCON is configured to output a display signal required by the display panel or a first error identification signal LS-F according to the working state of the level converter LSIC, and the backlight drive controller LED-D is configured to output a second error identification signal LED-DF or a backlight signal according to the working state of the backlight drive controller LED-D.

[0187] In this case, the monitoring circuit may include a second controller CPU, the input end of the second controller CPU is electrically connected to the output end of the backlight drive controller LED-D, and is electrically connected to the output end of the first controller TCON through the level converter LSIC, and the second controller CPU is configured to determine the display state of the display panel 3 by determining whether the first error identification signal LS-F and / or the second error identification signal LED-DF are received, that is, it can be determined by the first error identification signal LS-F and the second error identification signal LED-DF together, or it can be determined by any one of the first error identification signal LS-F and the second error identification signal LED-DF. The generation principle and judgment criteria of the first error identification signal LS-F and the second error identification signal LED-DF are also described in detail above, and will not be repeated here.

[0188] Based on the same inventive concept, an exemplary embodiment of the present disclosure provides a method for monitoring a display module. The monitoring method is used for any of the monitoring circuits described above. The monitoring method may include the following steps: collecting display signals and / or voltage signals of the display circuit, and judging whether the display panel displays normally and the abnormal type of abnormal display based on the display signals and / or voltage signals, and outputting the judgment result.

[0189] The following are examples to illustrate the various steps of the monitoring method.

[0190] Reference Fig.10 As shown, when the system (i.e., the display device) is powered on and stable, the voltage signal of the display circuit 1 is collected. Specifically, the voltage signal may include a DC analog voltage signal AVDD and a DC digital voltage signal DVDD. Therefore, the DC analog voltage signal AVDD and the DC digital voltage signal DVDD of the display circuit 1 are collected.

[0191] If the voltage signal is within the set range, the voltage is determined to be normal; that is, if the voltage of the DC analog voltage signal AVDD meets the first preset value and the voltage of the DC analog voltage signal AVDD meets the second preset value, the voltage is determined to be normal and output.

[0192] Specifically, the first preset value of the DC analog voltage signal AVDD may be greater than or equal to 15V and less than or equal to 17V. The second preset value of the DC digital voltage signal DVDD may be greater than or equal to 3V and less than or equal to 3.6V. That is, if the voltage of the collected DC analog voltage signal AVDD is greater than or equal to 15V and less than or equal to 17V, and the voltage of the collected DC digital voltage signal DVDD is greater than or equal to 3V and less than or equal to 3.6V, then the voltage is determined to be normal. That is, the DC analog voltage signal AVDD and the DC digital voltage signal DVDD are both within their respective corresponding setting ranges, then the voltage can be determined to be normal.

[0193] If the voltage signal is not within the set range, the voltage is determined to be abnormal and output; that is, if the voltage of the DC digital voltage signal DVDD does not meet the first preset value, and / or the voltage of the DC analog voltage signal AVDD does not meet the second preset value, the voltage is determined to be abnormal and output.

[0194] Specifically, if the voltage of the collected DC analog voltage signal AVDD is less than 15V or greater than 17V, or the value of the collected DC digital voltage signal DVDD is less than 3V or greater than 3.6V, the voltage is determined to be abnormal and output. That is, as long as one of the DC analog voltage signal AVDD and the DC digital voltage signal DVDD is not within the corresponding setting range, the voltage is determined to be abnormal and output; of course, if the voltage of the DC digital voltage signal DVDD does not meet the first preset value, and the voltage of the DC analog voltage signal AVDD does not meet the second preset value, the voltage is also determined to be abnormal and output; for example, the hexadecimal code 0x01 can be output as the code for voltage abnormality; of course, it can also be output through binary code, and can also be directly output in Chinese or English, which is not limited here.

[0195] In addition, in some other exemplary implementations of the present disclosure, only one of the DC analog voltage signal AVDD and the DC digital voltage signal DVDD may be monitored.

[0196] It should be noted that, since the voltage value of the DC analog voltage signal AVDD is adjusted to a fixed voltage by the second voltage divider unit 222, the fixed voltage is greater than or equal to 0 and less than or equal to 3.3V, and the second preset value can be greater than or equal to 3V and less than or equal to 3.6V, therefore, a mapping table between the adjusted value and the actual value of the DC analog voltage signal AVDD can be established. Before comparing the DC analog voltage signal AVDD with the second preset value, the adjusted value of the DC analog voltage signal AVDD can be mapped to the actual value and then compared.

[0197] Reference Fig.10 As shown, after determining that the voltage is normal, the display signal of the display circuit 1 is collected; since the display signal must be abnormal if the voltage is abnormal, it is not necessary to collect the display signal when the voltage is abnormal, and it is necessary to collect the display signal when the voltage is normal. The display signal may include a frame start signal STV1, a reset signal STV2, and a plurality of clock signals CLK, therefore, the frame start signal STV1, the reset signal STV2, and a plurality of clock signals CLK of the display circuit 1 are collected.

[0198] If the display signal is within the set range, the drive is determined to be normal; that is, if the frequency of the frame start signal STV1 meets the third preset value, and the frequency of the reset signal STV2 meets the fourth preset value, and the frequency of multiple clock signals CLK meets the fifth preset value, the drive is determined to be normal and output.

[0199] Specifically, the third preset value of the frame start signal STV1 may be greater than or equal to 58 Hz and less than or equal to 62 Hz. The fourth preset value of the reset signal STV2 may be greater than or equal to 56 Hz and less than or equal to 60 Hz, or the fourth preset value of the reset signal STV2 may be greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz. The fifth preset value of the clock signal CLK may be greater than or equal to 22.5 kHz and less than or equal to 22.9 kHz. That is, if the value of the collected frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz, and the value of the collected reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz, and the value of the collected clock signal CLK is greater than or equal to 22.5 kHz and less than or equal to 22.9 kHz, then it is determined that the drive is normal. That is, the frame start signal STV1, the reset signal STV2 and the multiple clock signals CLK are all within their respective corresponding setting ranges, and then the drive can be determined to be normal.

[0200] If the display signal is not within the set range, the drive is determined to be abnormal and output; that is, if the frequency of the frame start signal STV1 does not meet the third preset value, and / or the frequency of the reset signal STV2 does not meet the fourth preset value, and / or the frequency of multiple clock signals CLK does not meet the fifth preset value, the drive is determined to be abnormal and output.

[0201] Specifically, if the value of the collected frame start signal STV1 is less than 58Hz or greater than 62Hz, or the value of the collected reset signal STV2 is less than 56Hz or greater than 60Hz, or less than 1.5kHz or greater than 1.9kHz, or the value of the collected clock signal CLK is less than 22.5kHz or greater than 22.9kHz, the drive abnormality is determined and output. That is, as long as the frame start signal STV1, the reset signal STV2 and one of the multiple clock signals CLK are not within their respective corresponding set ranges, the drive abnormality is determined and output; of course, it can also be that the frame start signal STV1, the reset signal STV2, and two or more of the multiple clock signals CLK are not within their respective corresponding set ranges, the drive abnormality is determined and output; for example, the hexadecimal code 0x02 can be output as the code for the drive abnormality; of course, it can also be output through binary code, and it can also be directly output in Chinese or English, which is not limited here.

[0202] In addition, in some other exemplary embodiments of the present disclosure, only one, two or more of the frame start signal STV1, the reset signal STV2, and the multiple clock signals CLK may be monitored.

[0203] In some other example embodiments of the present disclosure, the monitoring method may further include: after determining that the voltage is normal, collecting the first error identification signal LS-F of the display circuit 1; if the first error identification signal LS-F is collected, determining that the drive is abnormal and outputting it.

[0204] In this case, the display signal may include a frame start signal STV1 and a reset signal STV2, the setting range and judgment criteria of which have been described in detail above, so they will not be repeated here. The generation principle of the first error identification signal LS-F has also been described in detail above, so it will not be repeated here.

[0205] Specifically, if the frequency of the collected frame start signal STV1 is greater than or equal to 58 Hz and less than or equal to 62 Hz, and the frequency of the collected reset signal STV2 is greater than or equal to 56 Hz and less than or equal to 60 Hz, or greater than or equal to 1.5 kHz and less than or equal to 1.9 kHz, and the first error identification signal LS-F is not collected, it is determined that the drive is normal. That is, the frame start signal STV1, the reset signal STV2 and the first error identification signal LS-F all meet the above conditions to determine that the drive is normal.

[0206] If the frequency of the collected frame start signal STV1 is less than 58Hz or greater than 62Hz, and / or the frequency of the collected reset signal STV2 is less than 56Hz or greater than 60Hz, or less than 1.5kHz or greater than 1.9kHz, and / or the first error identification signal LS-F is collected, the drive abnormality is determined and output. That is, as long as one of the frame start signal STV1, the reset signal STV2 and the first error identification signal LS-F does not meet the above conditions, the drive abnormality is determined and output, for example, the hexadecimal code 0x02 can be output as the code of the drive abnormality; of course, it can also be output through binary code, and can also be directly output in Chinese or English, which is not limited here.

[0207] In addition, in some other exemplary embodiments of the present disclosure, when acquiring the first error identification signal LS-F of the display circuit 1 , the display signal may include one of a frame start signal STV1 and a reset signal STV2 .

[0208] Reference Fig.10As shown, the monitoring method may further include: collecting a backlight signal of the display circuit 1, and judging whether the display panel 3 displays normally and the abnormal type of the abnormal display according to the backlight signal, and outputting the judgment result.

[0209] Specifically, while collecting the voltage signal, the backlight signal of the display circuit 1 is collected; the backlight signal may include the cathode voltage signal LED- of each partition of the backlight module 31, therefore, the cathode voltage signal LED- of each partition of the backlight module 31 of the display circuit 1 is collected.

[0210] If the cathode voltage signal LED- meets the sixth preset value, the backlight is determined to be normal; the sixth preset value of the backlight signal may be greater than or equal to 0.25V and less than or equal to 0.5V. That is, if the values ​​of the cathode voltage signal LED- of each partition of the backlight module 31 collected are greater than or equal to 0.25V and less than or equal to 0.5V, the backlight is determined to be normal.

[0211] If the cathode voltage signal LED- does not meet the sixth preset value, the backlight is determined to be abnormal and output; that is, as long as one of the values ​​of the cathode voltage signal LED- of each partition of the collected backlight module 31 is less than 0.25V or greater than 0.5V, the backlight is determined to be abnormal and output. For example, in the case where the backlight module 31 is provided with three partitions, as long as the value of the cathode voltage signal LED- of one partition is less than 0.25V or greater than 0.5V, the backlight is determined to be abnormal and output. For example, the hexadecimal code 0x04 can be output as the backlight abnormality code; of course, it can also be output through binary code, and can also be directly output in Chinese or English, which is not limited here.

[0212] It should be noted that, when the backlight module 31 has only one partition, it is sufficient to determine the cathode voltage signal LED- of one partition; when the backlight module 31 has two or more partitions, it is necessary to determine the cathode voltage signal LED- of all partitions. As long as the cathode voltage signal LED- of one partition does not meet the set range, the backlight is determined to be abnormal and output.

[0213] In some other example embodiments of the present disclosure, the monitoring method may further include: acquiring a second error identification signal LED-DF of the display circuit 1, and judging whether the display panel 3 displays normally and the abnormal type of the abnormal display according to the second error identification signal LED-DF, and outputting the judgment result.

[0214] Specifically, while collecting the voltage signal, the second error identification signal LED-DF is collected; if the second error identification signal LED-DF is not collected, the backlight is determined to be normal; if the second error identification signal LED-DF is collected, the backlight is determined to be abnormal and output. For example, the hexadecimal code 0x04 can be output as the code for the backlight abnormality; of course, it can also be output through binary code, and can also be output directly in Chinese or English, which is not limited here.

[0215] In the case that the backlight module 31 is provided with two or more partitions, only one second error identification signal LED-DF needs to be collected.

[0216] When it is determined that the voltage is normal, the drive is normal, and the backlight is normal, the output displays normal. For example, the hexadecimal code 0xFF can be output as a normal display code. Of course, it can also be output through binary code, or directly in Chinese or English, which is not limited here.

[0217] Of course, in some other exemplary embodiments of the present disclosure, when only one or two of the voltage signal, the display signal, and the backlight signal are monitored, as long as one or both of the monitored signals are normal, the output may indicate that the display is normal.

[0218] Reference Fig.10 As shown, in some example embodiments of the present disclosure, the monitoring method may also include: setting the refresh rate of the built-in self-test display mode to a set value different from the refresh rate of the normal display. For example, if the refresh rate of the normal display is 60 Hz, then the refresh rate of the built-in self-test display mode (STV1 special frequency) is set to 70 Hz, 65 Hz, 50 Hz or 48 Hz, etc.

[0219] The built-in self-test (BIST) display mode can be used to detect abnormalities during the use of the display module and automatically detect the operating status of a large area screen. The built-in self-test display mode is generally a black screen or a black-white, red-green-blue cycle screen.

[0220] After determining that the voltage is normal, the frame start signal STV1 is collected, that is, the refresh rate of the built-in self-test display mode is identified through the frame start signal STV1.

[0221] If the frame start signal (STV1 special frequency) is equal to the set value, it is determined that the built-in self-test is abnormal and output due to the abnormal signal provided by the SoC motherboard; if the frame start signal (STV1 special frequency) is not equal to the set value, it is determined that the built-in self-test is normal.

[0222] Reference Fig.10As shown, when performing a built-in self-test judgment, when it is judged that the voltage is normal, the built-in self-test is normal, the drive is normal and the backlight is normal, the output display is normal. For example, the hexadecimal code 0xFF can be output as a normal display code; of course, it can also be output through binary code, and can also be directly output in Chinese or English, which is not limited here.

[0223] The monitoring method may further include: after collecting the above signal of the display circuit 1, adjusting the voltage value of the above signal to within a required range. Since the processor MCU can only withstand a voltage of 0 to 3.3V, the voltage value of the collected signal should be adjusted to within a required range to avoid damage to the processor MCU.

[0224] It should be noted that the continuous acquisition time of various signals in the above signals is about 5 seconds, and the acquisition and judgment are carried out simultaneously; after completing one round of acquisition and judgment, the next round of acquisition and judgment is carried out, that is, after completing the acquisition and judgment of the voltage signal, the display signal (no acquisition and judgment is required when the voltage signal is abnormal) and the backlight signal, the next round of voltage signal, display signal and backlight signal acquisition and judgment is carried out. Moreover, the above data are only examples and explanations of the logic. Different data can be set according to different display modules, and the specific values ​​are different after the voltage is divided by the voltage divider unit, so they will not be explained one by one here.

[0225] It should be noted that, although the steps of the monitoring method of the display module in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0226] Based on the same inventive concept, an exemplary embodiment of the present disclosure provides a display device, which may include a display module and a monitoring circuit of any of the above display modules. The specific structures of the display module and the monitoring circuit have been described in detail above, so they will not be repeated here.

[0227] The specific type of the display device is not particularly limited and any type of display device commonly used in the art can be used, such as rail transit display screens, outdoor advertising machines, home appliances such as refrigerator display screens, vehicle display screens, mobile devices such as mobile phones, wearable devices such as watches, VR devices, etc. Those skilled in the art can make corresponding choices based on the specific purpose of the display device, which will not be elaborated here.

[0228] For example, display devices in rail transit, display devices in subway stations / bus stations / parking lots, etc., are used to provide pedestrians with vehicle arrival and station guidance information. If a display failure cannot be discovered and repaired in the first time, it will cause long-term inconvenience to travelers.

[0229] For example, many outdoor advertising machines are used in sparsely populated areas, and consumers and operators cannot find display failures in time. The above monitoring method and monitoring circuit are more suitable.

[0230] It should be noted that the display device may also include other necessary components and components, such as a housing, a circuit board, a power cord, etc., taking the display as an example. Those skilled in the art may make corresponding supplements according to the specific use requirements of the display device, which will not be repeated here.

[0231] Compared with the prior art, the beneficial effects of the display device provided by the exemplary embodiment of the present utility model are the same as the beneficial effects of the monitoring circuit of the display module provided by the above exemplary embodiment, which will not be elaborated here.

[0232] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the utility model disclosed herein. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A monitoring circuit for a display module, characterized in that: The display module includes a display panel and a display circuit, the display circuit includes a main controller, a first controller, a first power manager and a level converter, the input end of the first controller is electrically connected to the output end of the first power manager and the output end of the main controller, the output end of the first controller is electrically connected to the input end of the level converter, the first controller is configured to output a display signal required by the display panel through the level converter according to an instruction of the main controller, and the first power manager is configured to provide a voltage signal to the first controller; the monitoring circuit includes: A second controller, wherein the input end of the second controller is electrically connected to the output end of the first power manager and is electrically connected to the output end of the first controller through the level converter, and the second controller is configured to monitor the display state of the display panel according to the display signal and / or the voltage signal, wherein the output end of the level converter is electrically connected to the input end of the display panel and the input end of the second controller.

2. The monitoring circuit of the display module according to claim 1, characterized in that: The display module also includes a backlight module, and the display circuit also includes a backlight driving circuit, which is configured to provide a backlight signal to the backlight module, and an output end of the backlight driving circuit is electrically connected to an input end of the second controller and the backlight module.

3. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit comprises a first signal processing circuit, wherein the first signal processing circuit is configured to process a DC digital voltage signal in the voltage signal, and the first signal processing circuit comprises: a first emitter follower unit, electrically connected to an output terminal of the first power manager, wherein the first emitter follower unit is configured to collect a DC digital voltage signal in the voltage signal and prevent the DC digital voltage signal from flowing back to the display circuit; A first analog-to-digital conversion unit is electrically connected to the output end of the first emitter follower unit; the second controller is electrically connected to the output end of the first analog-to-digital conversion unit, and the second controller is configured to output the display state of the display panel as a first abnormal display state. In the first abnormal display state, the DC digital voltage signal has a first set value.

4. The monitoring circuit of the display module according to claim 3, characterized in that: The first set value is less than 3.0V or greater than 3.6V.

5. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: The signal processing circuit includes a second signal processing circuit, the second signal processing circuit is configured to process a DC analog voltage signal in the voltage signal, and the second signal processing circuit includes: a second emitter follower unit, electrically connected to the output end of the first power manager, the second emitter follower unit being configured to collect a DC analog voltage signal in the voltage signal and prevent the DC analog voltage signal from flowing back to the display circuit; a second voltage dividing unit, electrically connected to the output end of the second emitter follower unit, and the second voltage dividing unit is configured to adjust the value of the DC analog voltage signal to a fixed voltage; A second analog-to-digital conversion unit, electrically connected to an output end of the second voltage dividing unit; The second controller is electrically connected to the output end of the second analog-to-digital conversion unit, and the second controller is configured to output the display state of the display panel as a second abnormal display state. In the second abnormal display state, the DC analog voltage signal has a second set value.

6. The monitoring circuit of the display module according to claim 5, characterized in that: The second set value is less than 15V or greater than 17V.

7. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit includes a third signal processing circuit, wherein the third signal processing circuit is configured to process a frame start signal in the display signal, and the third signal processing circuit includes: a third emitter follower unit, electrically connected to the output end of the level converter, wherein the third emitter follower unit is configured to collect a frame start signal in the display signal and prevent the frame start signal from flowing back to the display circuit; a third voltage dividing unit, electrically connected to the output end of the third emitter follower unit, and configured to adjust the voltage value of the frame start signal to a fixed voltage; A first timing unit, electrically connected to the output end of the third voltage dividing unit; The second controller is electrically connected to the output end of the first timing unit, and is configured to output that the display state of the display panel is a third abnormal display state, in which the frequency of the frame start signal has a third set value.

8. The monitoring circuit of the display module according to claim 7, characterized in that: The third setting value is less than 58 Hz or greater than 62 Hz.

9. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit includes a fourth signal processing circuit, wherein the fourth signal processing circuit is configured to process a reset signal in the display signal, and the fourth signal processing circuit includes: a fourth emitter follower unit, electrically connected to the output end of the level converter, wherein the fourth emitter follower unit is configured to collect a reset signal in the display signal and prevent the reset signal from flowing back to the display circuit; a fourth voltage dividing unit, electrically connected to the output end of the fourth emitter follower unit, and configured to adjust the voltage value of the reset signal to a fixed voltage; A second timing unit, electrically connected to the output end of the fourth voltage dividing unit; The second controller is electrically connected to the output end of the second timing unit, and the second controller is configured to output the display state of the display panel as a fourth abnormal display state. In the fourth abnormal display state, the frequency of the reset signal has a fourth set value.

10. The monitoring circuit of the display module according to claim 9, characterized in that: The fourth setting value is less than 56 Hz or greater than 60 Hz, or the fourth setting value is less than 1.5 kHz or greater than 1.9 kHz.

11. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit includes a plurality of fifth signal processing circuits, wherein the fifth signal processing circuit is configured to process a clock signal in the display signal, and the fifth signal processing circuit includes: a fifth emitter follower unit, electrically connected to the output end of the level converter, wherein the fifth emitter follower unit is configured to collect a clock signal in the display signal and prevent the clock signal from flowing back to the display circuit; a fifth voltage dividing unit, electrically connected to the output end of the fifth emitter follower unit, and configured to adjust the voltage value of the clock signal to a fixed voltage; A plurality of third timing units, electrically connected to the output ends of the plurality of fifth voltage dividing units in a one-to-one correspondence; The second controller is electrically connected to the output ends of the plurality of third timing units; the second controller is configured to output the display state of the display panel as a fifth abnormal display state, in which the frequency of the clock signal has a fifth set value.

12. The monitoring circuit of the display module according to claim 11, characterized in that: The fifth setting value is less than 22.5 kHz or greater than 22.9 kHz.

13. The monitoring circuit of the display module according to claim 2, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit comprises a sixth signal processing circuit, wherein the sixth signal processing circuit is configured to process a cathode voltage signal in the backlight signal, and the sixth signal processing circuit comprises: a sixth emitter follower unit, electrically connected to the backlight driving circuit, the sixth emitter follower unit being configured to collect a cathode voltage signal in the backlight signal and prevent the cathode voltage signal from flowing back to the display circuit; A third analog-to-digital conversion unit, electrically connected to the output end of the sixth emitter follower unit; The second controller is electrically connected to the output end of the third analog-to-digital conversion unit, and the second controller is configured to output that the display state of the display panel is a sixth abnormal display state, and in the sixth abnormal display state, the cathode voltage signal has a sixth preset value.

14. The monitoring circuit of the display module according to claim 13, characterized in that: The sixth preset value is less than 0.25V or greater than 0.5V.

15. The monitoring circuit of the display module according to claim 2, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit is configured to process a working signal, the signal processing circuit comprises an emitter follower unit and a voltage divider unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage divider unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current, and the voltage divider unit is configured to adjust the voltage of the working signal; The working signal includes at least any one of the voltage signal, the display signal, and the backlight signal; The second controller is configured to determine whether the voltage signal, the display signal and the backlight signal in the working signal are all normal, and if so, determine that the display state of the display panel is a normal display state.

16. The monitoring circuit of the display module according to claim 2, characterized in that: The monitoring circuit also includes: A signal processing circuit, wherein the signal processing circuit is configured to process a working signal, the signal processing circuit comprises an emitter follower unit and a voltage divider unit, the emitter follower unit is electrically connected to the output end of the display circuit, the voltage divider unit is electrically connected to the output end of the emitter follower unit, the emitter follower unit is configured to collect the working signal and prevent the backflow of the working signal current, and the voltage divider unit is configured to adjust the voltage of the working signal; The working signal at least includes any one of the DC digital voltage signal and the DC analog voltage signal in the voltage signal, the frame start signal, the reset signal and the clock signal in the display signal, and the cathode voltage signal in the backlight signal; The second controller is configured to determine whether the working signal satisfies all the following conditions, and if so, determines that the display state of the display panel is a normal display state: the DC digital voltage signal is greater than or equal to 3.0V and less than or equal to 3.6V; the DC analog voltage signal is greater than or equal to 15V and less than or equal to 17V; the frame start signal is greater than or equal to 58Hz and less than or equal to 62Hz; the reset signal is greater than or equal to 56Hz and less than or equal to 60Hz, or the reset signal is greater than or equal to 1.5kHz and less than or equal to 1.9kHz; the clock signal is greater than or equal to 22.5kHz and less than or equal to 22.9kHz; the cathode voltage signal is greater than or equal to 0.25V and less than or equal to 0.5V.

17. The monitoring circuit of the display module according to any one of claims 3 to 16, characterized in that: The monitoring circuit also includes: The second power manager is electrically connected to the signal processing circuit and the second controller, and the second power manager is configured to supply power to the signal processing circuit and the second controller.

18. The monitoring circuit of the display module according to claim 1, characterized in that: The monitoring circuit also includes: The second power manager is electrically connected to the monitoring circuit, and the second power manager is configured to supply power to the monitoring circuit.

19. The monitoring circuit of the display module according to claim 1, characterized in that: At least part of the monitoring circuit and at least part of the display circuit are arranged on the same circuit board.

20. The monitoring circuit of the display module according to claim 2, characterized in that: The display circuit further includes: a backlight driving controller, wherein an output end of the backlight driving controller is electrically connected to an input end of the second controller and the backlight driving circuit, and the backlight driving controller is configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller; The input end of the second controller is electrically connected to the output end of the backlight driving controller and is electrically connected to the output end of the first controller through the level converter. The second controller is configured to determine the display state of the display panel by judging whether the second error identification signal is received.

21. The monitoring circuit of the display module according to claim 1, characterized in that: The display module further includes a backlight module, and the display circuit further includes a backlight driving controller, wherein an output end of the backlight driving controller is electrically connected to an input end of the second controller and the backlight module; The backlight driving controller is configured to output a second error identification signal or a backlight signal according to a working state of the backlight driving controller, and the first controller is configured to output a display signal required by the display panel or a first error identification signal according to a working state of the level converter; The input end of the second controller is electrically connected to the output end of the backlight drive controller, and is electrically connected to the output end of the first controller through the level converter. The second controller is configured to determine the display state of the display panel by judging whether the first error identification signal and / or the second error identification signal is received.

22. A monitoring circuit for a display module, characterized in that: The display module comprises a backlight module, a display panel and a display circuit, the display circuit comprises a main controller, a first controller, a backlight driving controller and a level converter, the input end of the first controller is electrically connected to the output end of the main controller, the output end of the first controller is electrically connected to the input end of the level converter, and the output end of the backlight driving controller is electrically connected to the input end of the backlight module; the first controller is configured to output a display signal or a first error identification signal required by the display panel according to the working state of the level converter, and the backlight driving controller is configured to output a second error identification signal or a backlight signal according to the working state of the backlight driving controller; The monitoring circuit comprises: A second controller, wherein the input end of the second controller is electrically connected to the output end of the backlight drive controller and is electrically connected to the output end of the first controller through the level converter, and the second controller is configured to determine the display state of the display panel by determining whether the first error identification signal and / or the second error identification signal is received.

23. A display device, characterized in that: include: Display module, including display panel and display circuit; The monitoring circuit is the monitoring circuit according to any one of claims 1 to 22, and the monitoring circuit is electrically connected to the display circuit.

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